QII53003-13.0.0

© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIare trademarks of Altera Corporation and registered in the U.Strademarks or service marks are the property of their respectivsemiconductor products to current specifications in accordanceservices at any time without notice. Altera assumes no responsdescribed herein except as expressly agreed to in writing by Alon any published information and before placing orders for pr

Quartus II Handbook Version 13.1Volume 3: VerificationMay 2013

May 2013QII53003-13.0.0

4. Cadence Incisive Enterprise SimulatorSupport

This chapter provides specific guidelines for simulation of Quartus® II designs withthe Cadence Incisive Enterprise (IES) software. You can also refer to the following formore information about EDA simulation:

■ For overview and version support information, Simulating Altera Designs in theQuartus II Handbook and About Using EDA Simulators in Quartus II Help.

■ For detailed GUI steps, Preparing for EDA Simulation and Running EDA Simulatorsin Quartus II Help.

Quick Start Example (NC-Verilog)You can adapt the following RTL simulation example to get started quickly with IES:

1. Specify your EDA simulator and executable path in the Quartus II software:set_user_option -name EDA_TOOL_PATH_NCSIM <ncsim executable path>rset_global_assignment -name EDA_SIMULATION_TOOL "NC-Verilog (Verilog)"r

2. Compile simulation model libraries using one of the following:

■ Run NativeLink RTL simulation to compile required design files, simulationmodels, and run your simulator. Verify results in your simulator. Skip steps 3through 4.

■ Use Simulation Library Compiler to compile all required simulation models.

■ Map Altera simulation libraries by adding the following commands to acds.lib file:include ${CDS_INST_DIR}/tools/inca/files/cds.libDEFINE <lib1>_ver <lib1_ver>

Then, compile Altera simulation models manually:vlog -work <lib1_ver>r

3. Elaborate your design and testbench with IES:ncelab <work library>.<top-level entity name>r

4. Run the simulation:ncsim <work library>.<top-level entity name>r

Cadence Incisive Enterprise GuidelinesThe following guidelines apply to simulation of Altera designs in the IES software.

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ibility or liability arising out of the application or use of any information, product, or servicetera. Altera customers are advised to obtain the latest version of device specifications before relyingoducts or services.

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4–2 Chapter 4: Cadence Incisive Enterprise Simulator SupportCadence Incisive Enterprise Guidelines

Simulation Tool InterfacesAltera supports both the IES GUI and command-line simulator interfaces. To start theIES GUI, type the following command at a command prompt:

nclaunchr

Table 4–1 lists the ISE command-line programs supported for IES simulation.

Elaborating Your DesignThe simulator automatically reads the .sdo file during elaboration of theQuartus II-generated Verilog HDL or SystemVerilog HDL netlist file. The ncelabexecutable recognizes the embedded system task $sdf_annotate and automaticallycompiles and annotates the .sdo file (runs ncsdfc automatically). VHDL netlist filesdo not contain system task calls to locate your .sdf file; therefore, you must compilethe standard .sdo file manually. Locate the .sdo file in the same directory where yourun elaboration or simulation. Otherwise, the $sdf_annotate task cannot reference the.sdo file correctly. If you are starting an elaboration or simulation from a differentdirectory, you can either comment out the $sdf_annotate and annotate the .sdo filewith the GUI, or add the full path of the .sdo file.

1 If you use NC-Sim for post-fit VHDL functional simulation of a Stratix V design thatincludes RAM, an elaboration error might occur if the component declarationparameters are not in the same order as the architecture parameters. Use the-namemap_mixgen option with the ncelab command to match the componentdeclaration parameter and architecture parameter names.

Back-Annotating Simulation Timing Data (VHDL Only)You can back annotate timing information in a Standard Delay Output File (.sdo) forVHDL simulators. To back annotate the .sdo timing data at the command line, followthese steps:

1. To compile the .sdo with the ncsdfc program, type the following command at thecommand prompt:

ncsdfc <project name>_vhd.sdo –output <output name>r

The ncsdfc program generates an <output name>.sdf.X compiled .sdo file.

1 If you do not specify an output name, ncsdfc uses <project name>.sdo.X.

Table 4–1. ISE Command-Line Programs

Program Function

ncvlogncvhdl

ncvlog compiles your Verilog HDL code and performs syntax and staticsemantics checks.

ncvhdl compiles your VHDL code and performs syntax and static semanticschecks.

ncelab Elaborates the design hierarchy and determines signal connectivity.

ncsdfc Performs back-annotation for simulation with VHDL simulators.

ncsimRuns mixed-language simulation. This program is the simulation kernel thatperforms event scheduling and executes the simulation code.

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Chapter 4: Cadence Incisive Enterprise Simulator Support 4–3Cadence Incisive Enterprise Guidelines

2. Specify the compiled .sdf file for the project by adding the following command toan ASCII SDF command file for the project:

COMPILED_SDF_FILE = "<project name>.sdf.X" SCOPE = <instance path>

Example 4–1 shows an example of an SDF command file.

After you compile the .sdf file, type the following command to elaborate the design:

ncelab worklib.<project name>:entity –SDF_CMD_FILE <SDF Command File>r

Disabling Timing Violations on RegistersIn certain situations, you may want to ignore timing violations on registers anddisable the “X” propagation that occurs (for example, timing violations in internalsynchronization registers in asynchronous clock-domain crossing).

By default, the x_on_violation_option logic option applying to all design registers isOn, resulting in an output of “X” at timing violation. To disable “X” propagation attiming violations on a specific register, set the x_on_violation_option logic option toOff for that register. The following command is an example from the Quartus IISettings File (.qsf):

set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to \<register_name>

Simulating Pulse Reject DelaysBy default, the IES software filters out all pulses that are shorter than the propagationdelay between primitives. Setting the pulse reject delays options in the IES softwareprevents the simulation tool from filtering out these pulses. Use the following optionsto ensure that all signal pulses are seen in the simulation results.

Table 4–2 describes the pulse reject delay options.

1 The -PULSE_R and -PULSE_INT_R options apply by default during NativeLinkgate-level timing simulation.

Example 4–1. SDF Command File

// SDF command file sdf_fileCOMPILED_SDF_FILE = "lpm_ram_dp_test_vhd.sdo.X",SCOPE = :tb,MTM_CONTROL = "TYPICAL",SCALE_FACTORS = "1.0:1.0:1.0",SCALE_TYPE = "FROM_MTM";

Table 4–2. Pulse Reject Delay Options

Option Description

-PULSE_RUse when simulation pulses are shorter than the delay in agate-level primitive. The argument is the percentage ofdelay for pulse reject limit for the path.

-PULSE_INT_R

Use when simulation pulses are shorter than theinterconnect delay between gate-level primitives. Theargument is the percentage of delay for pulse reject limit forthe path.

May 2013 Altera Corporation Quartus II Handbook Version 13.1Volume 3: Verification

4–4 Chapter 4: Cadence Incisive Enterprise Simulator SupportCadence Incisive Enterprise Guidelines

To perform a gate-level timing simulation with the device family library, type thefollowing IES software command:

ncelab worklib.<project name>:entity –SDF_CMD_FILE <SDF Command File> \-TIMESCALE 1ps/1ps -PULSE_R 0 -PULSE_INT_R 0r

Viewing a Simulation WaveformIES generates a.trn file automatically following simulation. You can use the .trn forgenerating the SimVision waveform view.

To view a waveform from a .trn file through SimVision, follow these steps:

1. Type simvision at the command line. The Design Browser dialog box appears.

2. In the File menu, click Open Database and click the .trn file.

3. In the Design Browser dialog box, select the signals that you want to observe fromthe Hierarchy.

4. Right-click the selected signals and click Send to Waveform Window.

1 You cannot view a waveform from a .vcd file in SimVision, and the .vcd file cannot beconverted to a .trn file.

Simulation Setup Script ExampleThe Quartus II software can generate a ncsim_setup.sh simulation setup script for IPcores in your design. The script contains shell commands that compile the requireddevice libraries, IP, or Qsys simulation models in the correct order. The script thenelaborates the top-level design and runs the simulation for 100 time units by default.You can run these scripts from a Linux command shell.

To set up the simulation script for a design, you can use the command-line to passvariable values to the shell script, as illustrated in Example 4–2.

Read the generated .sh script to see the variables that are available for you to overridewhen you source the script or that you can redefine directly in the generated .shscript. For example, you can specify additional elaboration and simulation optionswith the variables USER_DEFINED_ELAB_OPTIONS and USER_DEFINED_SIM_OPTIONS.

Example 4–2. Example Top-Level Simulation Shell Script for Incisive (NCSIM)

# Run script to compile libraries and IP simulation files# Skip elaboration and simulation of the IP variationsh ./ip_top_sim/cadence/ncsim_setup.sh SKIP_ELAB=1 SKIP_SIM=1QSYS_SIMDIR="./ip_top_sim"

#Compile the top-level testbench that instantiates your IPncvlog -sv ./top_testbench.sv

#Elaborate and simulate the top-level designncelab <elaboration control options> top_testbenchncsim <simulation control options> top_testbench

Quartus II Handbook Version 13.1 May 2013 Altera CorporationVolume 3: Verification

Chapter 4: Cadence Incisive Enterprise Simulator Support 4–5Document Revision History

Document Revision HistoryTable 4–3 shows the revision history for this chapter.

Table 4–3. Document Revision History

Date Version Changes

May 2013 13.0.0 Added note about parameter mismatch workaround.

November 2012 12.1.0 Relocated general simulation information to Simulating Altera Designs.

June 2012 12.0.0 Removed survey link.

November 2011 11.0.1 Template update. Minor editorial updates.

May 2011 11.0.0

■ Changed chapter title

■ Linked to Help for Stratix V Libraries

■ Added SystemVerilog HDL information

■ Other minor changes throughout

December 2010 10.0.1 Changed to new document template. No change to content.

July 2010 10.0.0

■ Linked to Help where appropriate

■ Minor text edits

■ Removed Referenced Documents section

November 2009 9.1.0

■ Removed NativeLink information and referenced new Simulating Designs with EDATools chapter in volume 3 of the Quartus II Handbook

■ Added “RTL Functional Simulation for Stratix IV Devices” and “Gate-Level TimingSimulation for Stratix IV Devices” sections

■ Minor text edits

March 2009 9.0.0

■ Removed “Compile Libraries Using the Altera Simulation Library Compiler”

■ Added “Compile Libraries Using the EDA Simulation Library Compiler” on page 4–5

■ Added “Generate Simulation Script from EDA Netlist Writer” on page 4–35

■ Added “Viewing a Waveform from a .trn File” on page 4–36

November 2008 8.1.0

■ Added “Compile Libraries Using the Altera Simulation Library Compiler” on page 4–5.

■ Added information about the --simlib_comp utility.

■ Minor editorial updates.

■ Updated entire chapter using 8½” × 11” chapter template.

May 2008 8.0.0.

■ Updated Table 4–1.

■ Updated Figure 4–1.

■ Updated “Compilation in Command-Line Mode” on page 4–9.

■ Updated “Generating a Timing Netlist with Different Timing Models” on page 4–18.

■ Added “Disable Timing Violation on Registers” on page 4–20.

■ Updated “Simulating Designs that Include Transceivers” on page 4–23.

■ Updated “Performing a Gate Level Simulation Using NativeLink” on page 4–30.

■ Added “Generating a Timing VCD File for PowerPlay” on page 4–33.

■ Added hyperlinks to referenced documents throughout the chapter.

■ Minor editorial updates.

May 2013 Altera Corporation Quartus II Handbook Version 13.1Volume 3: Verification

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f For previous versions of the Quartus II Handbook, refer to the Quartus II HandbookArchive.

Quartus II Handbook Version 13.1 May 2013 Altera CorporationVolume 3: Verification