3GFDDLib Mathworks Manual

8/6/2019 3GFDDLib Mathworks Manual

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3rd Generation Partnership Project (3GPP) Standard Compliant

3G FDD Library

Toolbox for MATLAB

&

Blockset for

3GPP:fdd

Version 5.0


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iii

Table of Contents

Table of Contents iii

List of Figures vii

Scope of this Document ix

3GPP FDD Library Version Number ix

Distribution and Support ix

3GPP Standard Documentation ix

3GPP Web Site ix

Key FDD Standard Document Numbers x

Comments and Support Requests x

This Document Licence xi

1 Introduction 1

1.1 3GPP Standard Compliance 1

1.2 FDD Library Version 1

1.3 Library Application 1

1.4 Installing the 3GPP:fdd Library 2

1.5 FDD Library Directory Structure 2

2 Why FDD? - The 3GPP Proposal for IMT2000 3

2.1 Universal Mobile Telephone System (UMTS) 3

2.2 IMT-2000 Standardisation 4

2.3 Global Standardisation - Partnership Projects - 3GPP 5

2.4 Spectrum Allocation 5

3 FDD Block Overview 6

3.1 Systems 6

3.2 PHY Channels 6

3.3 PHY Channel Components 63.3.1 Transport Channels 6

3.3.2 Physical Channels 6

3.3.3 General 7

3.4 Propagation Channel 7

3.5 Measurements & Synchronisation 7

3.6 HSUPA 7

4 Using the Library 8

4.1 Uplink Transmit and Receive. 8

4.2 Downlink Transmit and Receive. 11

4.3 Block Processing 14


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iv

4.3.1 The Delay Offset feature. 14

4.3.2 The No Leading Output feature 15

5 The 3GPP:fdd Library Blocks 16

5.1 Spectrum Spreading and Channelisation Waveform Generators 165.1.1 Orthogonal Variable Spreading Function (OVSF) Code Generator 17

5.1.2 Uplink Short Scrambling Code Generator 20

5.1.3 Uplink Long Scrambling Code Generator 24

5.1.4 Downlink Long Scrambling Code Generator 285.1.5 Spreader/Despreader 35

5.1.6 OVSF Fast Hadamard Transform 45

5.2 Code and Channel Generators 485.2.1 Pilot Symbol Generator 50

5.2.2 Uplink Random Access Channel Preamble Generator 55

5.2.3 Synchronisation Code Generator 58

5.2.4 Physical Channel Generator / Multiplexer 62

5.2.5 Downlink Dedicated Channel Generator 68

5.3 Channel Coding 775.3.1 Cyclic Redundancy Coding (CRC) - Encoder/Decoder 78

5.3.2 Convolutional Encoder 835.3.3 Convolutional Decoder (Viterbi Algorithm) 86

5.3.4 Turbo Encoder 90

5.3.5 Turbo Decoder 93

5.3.6 Rate Matcher 96

5.3.7 Interleaver 99

5.3.8 De-Interleaver (DeIntLeave) 102

5.3.9 Transport Channel Coder 104

5.3.10 Transport Channel Multiplexer 110

5.4 Channel Generators 1145.4.1 Uplink Generator 115

5.4.2 Downlink Generator 122

5.4.3 HSDPA Transmission Generator 134

5.5 Channel Models 1405.5.1 Complex Gain 141

5.5.2 Rayleigh Fading Channel 143

5.5.3 Moving Channel 147

5.5.4 Birth-Death Channel 150

5.6 Synchronisation 1535.6.1 Synchronisation Acquisition 154

5.6.2 Clock Generator 158

5.7 Physical Measurements 1635.7.1 Adjacent Channel Leakage 164

5.7.2 Bit Error Rate 167

5.8 Multiplexers, Demultiplexers and Integrators 169

5.8.1 I/Q Splitter 170

5.8.2 I/Q Combiner 172

5.8.3 1 to 2 Demultiplexer 173

5.8.4 Slot Field Demultiplexer 176

5.9 Averaging Blocks 181

5.9.1 Integrate and Dump 182

5.9.2 Frame Averaging 185


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v

6 Block-driven 3GPP:fdd Library Blocks 187

6.1 Frame Scrambler 188

6.2 Frame Spreader 189

6.3 E-AGCH Coder 190

6.4 E-HICH Coder 192

6.5 E-RGCH Coder 193

6.6 E-DPCCH Coder 195

6.7 E-DCH Coder 196

7 Matlab Toolbox Functions 197

7.1 FddCRC 199

7.2 FddHSBitScrambling 201

7.3 FddTrCHCoding 202

7.4 FddTurboDecoding 203

7.5 FddConvolutionalDecoding 205

7.6 FddHSHarq 206

7.7 FddHSHarqRecovery 207

7.8 FddEHarq 208

7.9 FddEHarqRecovery 209

7.10 FddPhyChSegmentation 210

7.11 FddPhyChInterleaving 211

7.12 FddPhyChDeinterleaving 212

7.13 FddConstellationRearranging 213

7.14 FddConstellationDearranging 214

7.15 FddDLModulation 215

7.16 FddDLDemodulation 216

7.17 FddULModulation 217

7.18 FddULDemodulation 218

7.19 FddSpreading 219

7.20 FddDespreading 220

7.21 FddScrambing 221

7.22 FddDescrambling 222

7.23 FddHSSCCHCoding 223

7.24 FddHSSCCHCodingType3 224

7.25 FddHSSCCH 226

7.26 FddHSHARQACKEncoding 230

7.27 FddHSCQIEncoding 231

7.28 FddEDCHCoding 232

7.29 FddEDPCCHCoding 233

7.30 FddERGCHCoding 234

7.31 FddEHICHCoding 235

7.32 FddEAGCHCoding 236

7.33 FddHSDSCH 237

7.34 FddHSDSCHDecode 239

7.35 FddHSPDSCH 240

7.36 FddHSPDSCHDecode 242

7.37 FddFadingChan 244

Appendix A:3GPP Definitions 247


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vi

Appendix B:3GPP Abbreviations 251


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vii

List of Figures

1 Introduction 1

Figure 1.3.1: Simulation groupings for the library. 1

Figure 1.5.1: FDD Library directory structure. 2

2 Why FDD? - The 3GPP Proposal for IMT2000 3

3 FDD Block Overview 6

4 Using the Library 8Figure 4.1.1: Uplink transmit - critical block paths in transport and physical channels. 9

Figure 4.1.2: Uplink receive: critical block paths in transport and physical channels. 10

Figure 4.2.1: Downlink transmit: critical block paths in transport and physical channels. 12

Figure 4.2.2: Downlink receive: critical block paths in transport and physical channels. 13

Figure 4.3.1: Interleaving with delay 14

5 The 3GPP:fdd Library Blocks 16

Figure 5.1.1: Orthogonal code generation structure 19

Figure 5.1.2: The modulo-4 and two modulo-2 sequence generators. 22

Figure 5.1.3: Uplink short scrambling code generator. 23

Figure 5.1.4: Uplink long scrambling code generator. 26Figure 5.1.5: Downlink long scrambling code generator. 34

Figure 5.1.6: Output of spreader block in spreading mode 39

Figure 5.1.7: Effect of the timing offset parameter in the operation of the spreader block 40

Figure 5.1.8: Effect of the delay offset parameter in the operation of the spreader block 41

Figure 5.1.9: Downlink spreading structure. 42

Figure 5.1.10: DPCH uplink spreading structure 42

Figure 5.1.11: Code tree for fast Hadamard transform. 45

Figure 5.2.1: Effect of clock on data option. 52

Figure 5.2.2: DPCCH slot structure 52

Figure 5.2.3: DL DPCH slot format 53

Figure 5.2.4: CPICH slot format 53

Figure 5.2.5: Symbol sequence used in CPICH 53

Figure 5.2.6: S-CCPCH slot format 54

Figure 5.2.7: Random access transmission structure 56

Figure 5.2.8: RACH generation. 57

Figure 5.2.9: Position of primary SCH in slot 59

Figure 5.2.10: Structure of SCH frame 59

Figure 5.2.11: Dedicated Physical Channel Mapping. 65

Figure 5.2.12: DPDCH and DPCCH on the uplink DPCH. 65

Figure 5.2.13: DPDCH and DPCCH on the downlink DPCH. 65

Figure 5.2.14: Uplink PRACH control channel. 66Figure 5.2.15: Downlink S-CCPCH. 66

Figure 5.3.1: Output block structure of CRC encoder. 79

Figure 5.3.2: CRC parity generator. 81

Figure 5.3.3: CRC syndrome generator. 81

Figure 5.3.4: The steps performed by the convolutional encoders block. 84

Figure 5.3.5: The structure of the convolutional coder function generators. 85

Figure 5.3.6: Turbo Coder. 92

Figure 5.3.7: Turbo Decoder. 94

Figure 5.3.8: Transport Channel Coder Functions (Downlink) 108

Figure 5.3.9: Multiplexing of logical channels into a transport channel. 111

Figure 5.3.10: Multiplexing of 3 transport channels into a radio frame. 112Figure 5.5.1: Multipath fading channel structure. 144

Figure 5.5.2: Moving channel path positions. 148

Figure 5.5.3: Path birth and death in birth-death channel. 151


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viii

Figure 5.6.1: Chip, symbol and slot clock signals. 160

Figure 5.6.2: Relation between input/internal clock and chip clock 160

Figure 5.6.3: Use of advance input and its effect on the chip clock. 161

Figure 5.6.4: Use of retard input and its effect on the chip clock. 161

Figure 5.7.1: Positioning of adjacent channels. 165

Figure 5.8.1: Operation of IQ splitting. 171

Figure 5.8.2: Demultiplexing three bit fields using two Demux12 block 174

Figure 5.8.3: Demultiplexing of a DTCH using the Demux12 block 175Figure 5.8.4: Structure of downlink DPCH slot at 30 kbps 177

Figure 5.8.5: Demultiplexing the DPCH slot into the different blocks outputs 178

Figure 5.8.6: Parameters used to demultiplex DLDPCH slots at 30 kbps 179

Figure 5.8.7: Assigning fields to outputs 179

Figure 5.8.8: Assigning slot fields to outputs 180

Figure 5.9.1: Integrate and dump operation over six samples (N = 6) 183

Figure 5.9.2: General form for integrate and dump. 184

Figure 5.9.3: Operation of the Frame Averaging block 186

6 Block-driven 3GPP:fdd Library Blocks 187

7 Matlab Toolbox Functions 197


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ix

i Scope of this Document

This document is the users manual for the Steepest Ascent 3rd GenerationPartnership Project (3GPP) Frequency Division Duplex (FDD) simulation library- 3GPP:fdd. The aim of the document is to define, describe and demonstrate byexample the proper use of the various blocks within the 3GPP:fddlibrary.

ii 3GPP FDD Library Version Number

This manual is the FDD Library Version 5.0. You can establish the library versionnumber of your installed software by right-mouse-clicking on the file:

\FDD\fdd.dll

To use this library you require Windows 2000 (or later) and Matlab/SimulinkVersion 7.3 (R2006b) or later for Windows.

iii Distribution and Support

For pre and post sales support please contact:

iv 3GPP Standard Documentation

The functionality of this software library is defined by the standard releasedocuments from the 3rd Generation Partnership Project (3GPP) TechnicalSpecification Group (TSG) RAN WG4. The document numbers are from the TS-25 series technical specification.

v 3GPP Web SiteThe standard documents used for the development and specification of thissimulation library are available from http://www.3gpp.org

Steepest Ascent LtdLadywell94 Duke Street

GlasgowG4 0UWUnited Kingdom

Tel: +44 (0) 141 552 8855Fax: +44 (0) 141 552 8855Email: [email protected]: www.steepestascent.com


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x

vi Key FDD Standard Document Numbers

The reference documents used for the verification of the 3GPP:fddlibrary are:

The FDD Library Version 5.0 is compliant with Release 6 3GPP specificationsincluding HSDPA and HSUPA, which indicates it is compliant with V6 series ofthe physical layer description documents TS25.211, TS25.212, TS25.213 andTS25.214.

vii Comments and Support Requests

Please contact Steepest Ascent ([email protected]) or your localdistributor with comments and for support information.

DocumentNumber Title Short Descriptor

TS25.101UE Radio Transmission andReception (FDD)

Establishes the minimum RF charac-teristics of the FDD mode of UTRAfor the user equipment.

TS25.104UTRA (BS) FDD; Radio Transmis-sion and Reception

Establishes the base station mini-mum RF characteristics of the FDDmode of UTRA.

TS25.133RF Parameters in Support ofRadio Resource Management

Transmission

Establishes the base station mini-mum RF characteristics of the FDD

mode of UTRA.

TS 25.201Physical Layer - General Descrip-ton

Presents a general description of thephysical layer of the UTRA radiointerface.

TS 25.211Physical channels and mapping oftransport channels onto physicalchannels (FDD)

Describes the characterisation of thelayer 1 transport channels and phys-ical channels in the FDD mode ofUTRA.

TS 25.212Multiplexing and channel coding(FDD)

Describes the characteristics of the

layer 1 multiplexing and channelcoding in the FDD more of UTRA

TS 25.213 Spreading and Modulation (FDD)Describes the spreading a modula-tion for UTRA physical layer FDDmode.

TS 25.214 Physical layer proceduresSpecifies and establishes the char-acteristics of the physical layer pro-cedures in the FDD mode of UTRA.

TS 25.302Services provided by the physical

layer.

Services provided by the physical

layer of UTRA to the upper layers.


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xi

viii This Document Licence

As the owner of the FDD library you have ownership of both a printed and anAcrobat PDF electronic version of this document. Duplication and/or distributionof either paper or electronic format is prohibited.

The FDD Library is copyright Steepest Ascent Ltd 2005-2011.All asserted IPR Rights are reserved and retained by the owners and materialdevelopers.


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11 Introduction

1 Introduction

This manual specifies the components of the 3GPP:fdd (3rd GenerationPartnership Project - Frequency Division Duplex) library. The library provides ameans of simulation of the physical layer between the basestation (BS) and mobilestation (MS) (or user equipment(UE) terminals). Hence the FDD library containsa number of defined source and input/output blocks which can be used as buildingblocks to produce a complete standard compliant FDD system simulation as both abaseband simulation or an RF modulated simulation.

1.1 3GPP Standard Compliance

The FDD software library described in this document is standard compliant to the3rd Generation Partnership Project (3GPP) release documents listed in Section iv

on page xi of this document. The latest release of the standard documents areavailable at:

http://www.3gpp.org

1.2 FDD Library Version

For the latest revision of this library please check the Steepest Ascent website:

http://www.steepestascent.com/downloads

1.3 Library Application

The library is likely to be used in a number of applications within Universal MobileTerminal System (UMTS) TerrestrialRadioAccess (UTRA) design. Typically theuplink and downlink physical layer implementations (summarised in Figure 1.3.1)for the transmit and receive of UTRA can be simulated and analysed with the

3GPP:fddlibrary.

Universal Mobile Telephone System (UMTS)

Figure 1.3.1: Simulation groupings for the library.

Uplink Downlink

Transmit Receive Transmit Receive

Terrestrial Radio Access with Frequency Division Duplex


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21 Introduction

1.4 Installing the 3GPP:fddLibrary

To install the FDD library, (assuming you have a valid licence for the simulator),ensure that the simulator isNOTrunning, and execute the installer from:

FDDLib_installer_vX.X.X.exe

This is the file which you will have downloaded from the website, or that wasdelivered on the FDD CD.

1.5 FDD Library Directory Structure

The directory structure of the installed FDD library is shown in Figure 1.5.1.

The directory docs contains Adobe Acrobat portable document format (pdf)version of this manual. The latest Adobe Acrobat Reader can be downloaded fromhttp://www.adobe.com. This document you are reading or viewing now is the filefdd.pdf.

The FDDLib directory contain all necessary files to ensure the FDD library will runwithin the simulation environment.

3G simulation example files are located in the directory Examples. Thesesimulations illustrate correct and typical use of the blocks and also include completeand advanced simulation designs for base station (BS) and mobile station (MS)physical layer implementations.

FDDLib

Examples

General

Downlink

Compressed Mode

docs

Figure 1.5.1: FDD Library directory structure.

procedures

spreading

HSDPA

Uplink

channel coding


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32 Why FDD? - The 3GPP Proposal for IMT2000


For the third generation (3G) mobile radio systems, the consumer market isexpected to show an increasing demand for services ranging from low data ratevoice communication (as provided by 2G standards such as GSM) to high data ratesto support multimedia applications with integrated audio and videocommunications. These emerging demands lead to the technical requirements forIMT2000 - International Mobile Telephones in the Year 2000, which are now beingstandardised worldwide. Both dedicated circuit and packet switched services willbe available and they will operated in environments with the aim of allowing datacommunication, anyplace, anytime, anywhere.

Due to spectrum availability different parts of the world may be using differentfrequency bands and therefore an absolute fundamental standard is unlikely to be

produced. However, in the different regions of the world (Europe, USA, Korea,Japan) very similar proposals have been put forward, and most recently the 3GPP(3rd Generation Partnership Projects) have had the objective of converging thevarious detailed standards. The evolution from 2G to 3G is being very carefullyplanned, as far as possible the 2G investment will be deployed and retained whereappropriate.

2.1 Universal Mobile Telephone System (UMTS)

UMTS is the name of the European version of IMT-2000. Currently the UMTSgroup expect that in the year 2000 there will be more than 400 million 2Gsubscribers, and by 2010, some 1800 million. The 2G standards use digital datatransmission and in Europe the standard is GSM, Global System for Mobilecommunications (in the USA it is IS-136 and IS-95, and PDC (personal digitalcellular) and Personal Handyphone System (PHS) technology in Japan). The firstgeneration (1G) mobile technology was based on analogue signalling and is nowbeginning to be phased out. 2G traffic and numbers of users are still on the increase,

however data rates are limited - a single channel data rate with a GSM telephone(mobile station) is 9.6kbits/s.

UMTS will bring a number of new services by virtue of its high data rates:

Internet access, email, multimedia document transfer;

Mobile video teleconferencing;

Audio, video narrowcasting (download videos, computer games, newspapers).

The data rates from UMTS are planned as high as 2Mbits/sec (some 200 xs GSMcapability, and almost 40 xs faster than a 56k modem). More precisely, due tovarious environments that mobile stations will be used in, three upper limit datarates will emerge:


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144kbits/sec: For vehicular (high speed) mobile stations environments;

384 kbits/sec: For outdoor and slow roaming environments;

2.048Mbits/sec: For indoor and wireless area network (WAN) environments

(picocells).

It is planned that 3G services will operate in all environments such as downtownurban areas, hilly and mountainous areas, and in indoor building environments.Therefore, with high data rates, global operating environments 3G will see an evenwider application and exploitation than the current 2G.

2.2 IMT-2000 Standardisation

The standardisation for IMT-2000 has been carried out primarily in Europe, China,

Japan, Korea and America:

European Telecommunications Standard Institute (ETSI) - Special Mobile

Group (SMG); Europe;

Research Institute of Telecommunications Transmission (RITT), China;

Association of Radio Industry and Business (ARIB), Japan

Telecommunication Technology Committee (TTC), Japan;

Telecommunications Technology Association (TTA), Korea;

Telecommunication Industry Association (TIA), USAT1P1, USA.

The International Telecommunication Union Radio CommunicationStandardisation Sector (ITU-R) called for proposals for radio transmissiontechnology by June 1998 and for evaluation in late 1998. ETSI-SMG have beenconsidering their input since 1996, and proposed wideband CDMA (WCDMA) inboth paired bands (called FDD) and a shared band (called TDD) in January 1998.

A key consideration was of course the economic feasibility and the compatibilitywith existing GSM systems, and emerging GSM-Edge. ETSI SMG have thereforesubmitted this proposal of UMTS Terrestrial Radio Access (UTRA) concept to theITU-R for inclusion in IMT-2000.

The Japanese ARIB standard is closed related to the European WCDMA, and wassubmitted to the ITU-R and subsequently frozen in mid-1999 - Japan aims to deploycommercial WCDMA services in mid-2001. The Chinese RITT has proposed atime-division (TD) CDMA technique for TDD services and wireless local loop

applications. The TTA in Korea has two proposals, one very close to the JapaneseARIB WCDMA and one similar to the American TIA cdma2000 proposal. In theUSA there are a number of proposals. In particular the TIA support the evolutionand extension of the existing IS-95 standard (a 2G CDMA implementation) into


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what is denoted cdma2000. TIA also have proposed a WCDMA standard calledWIMS and UWC-136, which is an evolution of the 2G IS-136 DAMPs standard.The T1P1 support WCDMA-NA, which corresponds to UTRA FDD from ETSI.

2.3 Global Standardisation - Partnership Projects - 3GPP

If the various regional standards can be harmonised then a partial/quasi-globalstandard would be in place. This would of course lead to economical andconvenience advantages for customers, equipment manufacturers, and networkoperators. Therefore two projects have been established:

The Third Generation Partnership Project (3GPP): To harmonise and

standardise in detail the similar proposals from ETSI, ARIB, TTC, TTA, T1P1.

3GPP2: To harmonise the cdma2000 proposals from TIA and TTA.

In addition, major international operators have invoked a process of cooperationbetween 3GPP and 3GPP2 with the aim of a globally harmonised concept.

2.4 Spectrum Allocation

Following the 1992 World Administrative Radio Conference (WARC) thespectrum for 3G systems was identified. At present, all regions have NOT adheredto the this suggested allocation of bandwidth, and therefore no absolutely commonspectrum band is available for 3G mobile radio.


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63 FDD Block Overview


3GPP:fdd provides powerful, flexible and easy to use blocks to implement thelatest release of the 3GPP standard for FDD. The blocks can be integrated with anystandard blocks from the simulator, such as modulators, adaptive equalisers, and soon. The blocks in the library provide the functionality outlined below.

3.1 Systems

Uplink Generator

Downlink Generator

HSDPA Transmission Generator

3.2 PHY Channels

Dedicated Physical Control Channel (DPCCH) Generator

Transport Channel Coder

Downlink Dedicated Channel Generator

3.3 PHY Channel Components

3.3.1 Transport Channels

Cyclic Redundancy Coding (CRC) - Encoder/Decoder

Convolutional Encoder

Convolutional Decoder (Viterbi Algorithm)

Turbo Encoder

Turbo Decoder

Rate Matcher Interleaver

De-Interleaver (DeIntLeave)

Transport Channel Multiplexer

3.3.2 Physical Channels

Physical Channel Slot Field Demultiplexer

Clock Generator Orthogonal Variable Spreading Function (OVSF) Code Generator

Uplink Short Scrambling Code Generator

Uplink Long Scrambling Code Generator

DPCHGEN

UL

DPCHGEN

DL

HSDPA

PHYCH

CHCODEC

CRC

RM

OVSF

SSCC

UL

LSCC

UL


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Downlink Long Scrambling Code Generator

Spreader/Despreader

Pilot Symbol Generator

Random Access Channel Preamble Generator

Downlink Synchronisation Code Generator

Orthogonal Variable Spreading Factor (OVSF) Transform

Frame Scrambler

Frame Spreader

3.3.3 General

I/Q Splitter

I/Q Combiner

1 to 2 Demultiplexer

Integrate and Dump

3.4 Propagation Channel

Complex Gain

Rayleigh Fading Channel

Moving Channel Birth-Death Channel

3.5 Measurements & Synchronisation

Adjacent Channel Leakage Power

Bit Error Rate Counter

Frame Averaging

Sychronisation Acquisition

3.6 HSUPA

E-AGCH Coder

E-RGCH Coder

E-HICH Coder

E-DPCCH Coder E-DCH Coder

LSCC

DL

SPDR

PILOT

RACH

UL

SCHDL

OVSFFHT

MPTH

MOV

BD

ACLR

BER

SyncDL


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84 Using the Library

4 Using the Library

4.1 Uplink Transmit and Receive.

Figure 4.1.1 shows the generic functionality of the blocks to produce an uplink

transmitter simulation, and in Figure 4.1.2 the uplink receiver is shown. Note thatthese figures only indicate the critical block path and do not illustrate, forexample multiuser or noisy simulations.

It should also be noted that there is more than one way to produce the same desiredoutput. Therefore in cases where a designer wishes to specify each component,discrete single function blocks are provided. If a standard compliant full uplink isrequired, then a single fully parameterised block is available.


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Information Bits

Cyclic Redundancy Coding

Convolutional Coding

1st Interleaving

Rate Matching

2nd Interleaving

OVSF

Transport

CRCGen

ConvEnc

IntLeave

RateM

IntLeave

Fading

DPCCHGen

TrChCdr

Complex Gain,

Channel Models

CRC

CHCODEC

PHYCH

MPTH

RM

Turbo Coding

TurboEnc

RealandImaginary

ChannelCodec

3GPP FDD - Uplink Transmit

DPCHGEN

UL

UpLink

RF Output

IntLeave

Transport Channel MuxPhysical Control Chan Gen.

TChMux

Figure4.1.1:

Upl

inktransmit-criticalblockpathsintransportandphysicalch

annels.

BDMOV

Control Data

Imag RealSPDR

Complex Data Output

Pulse Shaping

RF Modulation

Complex data path

In-Phase Data

RF Output

or

Short Code Gen.Long Code Gen.

ULSCGen ULLCGen

SSCC

UL

LSCC

UL

or

Quadrature data

Cos

Sin

CplxMpy

SPRDR

Moving Birth/Death Cplx Gain

or

or

or or or

OVSF

OVSF

Spreader


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4.2 Downlink Transmit and Receive.

Figure 4.2.1 shows the generic functionality of the blocks that produce a downlinktransmitter simulation, whilst in Figure 4.2.2 the downlink receiver is shown. Notethat again, these figures only indicate the critical block path and do not illustrate,for example, multiuser or noisy simulations. Also note that there is more than one

way to produce the same desired output. Therefore in cases where a designer wishesto specify each component, discrete single function blocks are provided. Howeverif a standard compliant full downlink link is required, then a single fullyparameterised block is available.


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Orthogonal Variable

Downlink

OVSF

DLLCGen

OVSF

LSCC

DL

Spreading Function

3GPP FDD - Downlink Transmit

DPCHGEN

DL

DownLink

RF Output

Cyclic Redundancy Coding

Convolutional Coding

1st Interleaving

Rate Matching

2nd Interleaving

Transport

CRCGen

ConvEnc

IntLeave

RateM

IntLeave

IQSplit

DPCCHGen

TrChCdr

CRC

CHCODEC

PHYCH

RM

Turbo Coding

TurboEnc

ChannelCodec

IntLeave

Transport Channel MuxPhysical Control Chan Gen.

TChMux

Figure4.2.1:

Downlinktransmit:criticalblockpa

thsintransportandphysicalc

hannels.

Information bits

SPRDR

SPDRSpreader

RF Output

Pulse ShapingRF Modulation

Cos

Sin

ClockGen

ClockGenerator

Complex data path

Fading

Complex Gain,

Channel ModelsMPTH BDMOV

Moving Birth/Death Cplx Gain

CplxMpyCode Gen.

Complex data path

Complex Data Output

or

or or or

or

or


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OVSF

OVSF

Cyclic Redundancy Decode

Convolutional Decoding

1st Deinterleaving

Rate Recovery

2nd Deinterleaving

Transport

CRCGen

ConvDec

DeIntLev

RateM

DeIntLev

TrChCdr

CRC

CHCODEC

RM

Turbo Decoding

TurboDec

ChannelCodec

3GPP FDD - Downlink Receive

Demultiplexing

Demux12

Figure4.2.2:

Downlinkreceive:criticalblockpathsintransportandphysicalchannels.

Information bits

Pulse Shaping

RF Demodulation

Cos

Sin

Complex Data InputRF Input

CplxMpy

SPDR

SPRDR

or ClockGen

ClockGenerator

Complex Symbols

IntDump Cmplx Gain

or

or

or

Downlink

DLLCGen

LSCCDL

Code Gen.


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4.3 Block Processing

All the library blocks operate in a sample by sample processing fashion. If a blockis required to operate on a specific frame of data (e.g. a block interleaver) then itwill serialize and de-serialize this array of data internally during processing. Toensure that the boundaries of data frames remain aligned as they pass through

consecutive processing blocks, the library provides a number of parameters tocontrol the synchronization.

4.3.1 The Delay Offset feature.

Consider the following simple system, shown in Figure 4.3.1, consisting of a sourcewhich is interleaved and deinterleaved with an arbitrary delay in between. Assumethat the interleaving and deinterleaving block lengths are 804 bits.

In the case of the delay being zero ( ), the deinterleaver will see a perfectly

aligned block to deinterleave and the input and output will simply be shifted relativeto each other by 1608 bits - just double the block length. However, if the delay isnon-zero, say sample delays, the data into the de-interleaver will be mis-aligned and a corrupted output will be produced. One method of working aroundthis situation is to introduce enough further delay to resynchronise. In this case 804-5 = 799 samples. This is an awkward solution and will mean an extra 799 sampleswill have to be processed before output data is available, thus unnecessarilyextending the simulation length. In the case of blocks with the delay offsetfeature, all that is required is to enable the feature by specifying 5 in the delay offset

and enabling the delay in samples check box. Alternatively, the time for 5samples could be entered in the delay offset and the delay in samples check boxleft unchecked.

See Section 5.3.8 on page 102 for dialog box example of these parameters.

The delay offset mechanism is therefore an effective mechanism for coping withdelays in data that requires to be synchronised for processing.

zNinput output

Figure 4.3.1: Interleaving with delay

N 0=

N 5=


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4.3.2 The No Leading Output feature

The No Leading Output functionality is not support in Simulink. The library isavailable for a number of different simulation platforms however not a simulatorsoffer the same kind of scheduling features. The No Leading Output feature is onlysupported on platforms which combine both data-flow and event-driven aspects intheir model of computation.


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165 The 3GPP:fdd Library Blocks

5 The 3GPP:fddLibrary Blocks

This section specifies the parametric and functional operation of the FDD libraryblocks. The library blocks are outlined in the following subsections:

5.1 Spectrum Spreading and Channelisation Waveform Generators

5.2 Code and Channel Generators

5.3 Channel Coding

5.4 Channel Generators

5.5 Channel Models

5.6 Synchronisation

5.7 Physical Measurements

5.8 Signal Multiplexors and Demultiplexors

5.1 Spectrum Spreading and Channelisation Waveform Generators

The library provides a number of blocks which will produce standard compliantspreading codes for the uplink and downlink, and also orthogonal codes forchannelisation. The following blocks are provided:

Orthogonal Variable Spreading Function Code Generator (OVSF)

Uplink Short Scrambling Code Generator (ULSCGen)

Uplink Long Scrambling Code Generator (ULLCGen)

Downlink Long Scrambling Code Generator (DLLCGen)

Spreader/Despreader (Spreader)

Orthogonal Variable Spreading Function Fast Hadamard Transform

(OVSFTran)

The blocks allow the designer to build the scrambling/spreading usingcombinations of blocks or to use the SPRDR block which provides a single blockthat will implement the standard compliant, short, long, and orthogonal codes asappropriate for either the uplink or downlink. Figure 4.1.1 to Figure 4.2.2 illustratethe cross-over functionality between these blocks.

OVSF

SSCC

UL

LSCC

UL

LSCCDL

SPDR

OVSFFHT


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5.1.1 Orthogonal Variable Spreading Function (OVSF) Code Generator

Block Name: OVSFGen

Abbreviation: OVSF

Synopsis: This block generates OVSF code sequences according to the specifiedclass/spreading factor and code number within the class.

Block Inputs: Clock: Normally the chip rate clock. The code advances on therising edge of the clock input.

Block Outputs: Output: The code output sequence, updated on the rising edges

of the clock input.

Parameter RangeDefaultValue

Definition

Code Class/Spreading factorC1..C12

SF=2..4096C7/128

The OVSF code class andlength. This determines thesize of the Hadamard matrix

SF x SF

Code Number 0..(SF-1) 16The code number. Selects a

row within the Hadamardmatrix

Input Threshold All 0 Input high/low threshold

True Output All -1 True output voltage

False Output All 1 False output voltage

OVSF


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Discussion: The OVSF codes are used as channelisation codes to maintainorthogonality between different physical channels. They are also known as Walshcodes or OVSF codes and are generated from a Hadamard matrix as show below:

[5.1.1]

[5.1.2]

[5.1.3]

[5.1.4]

where is a power of two and denotes the binary complement of . The

channelisation code is the th row of whose binary elements havebeen mapped into real values where and . The different codesgenerated are

, for [5.1.5]

, for [5.1.6]

, for [5.1.7]

H1 0=

H20 0

0 1=

H4

0 0 0 0

0 1 0 1

0 0 1 1

0 1 1 0

=

H2N

HNHN

HNHN

=

N HN HN

Cch SF k, , k HSF0 +1 1 1

Cch 1 0, , 1= SF 1=

Cch 2 0, ,

Cch 2 1, ,

Cch 1 0, , Cch 1 0, ,

Cch 1 0, , C ch 1 0, ,

1 1

1 1= = SF 2=

Cch 2

n 1+( )0, ,

Cch 2

n 1+( )1, ,

Cch 2

n 1+( )2, ,

Cch 2

n 1+( )3, ,

C

ch 2n 1+( )

2n 1+( )

2, ,

Cch 2

n 1+( )2

n 1+( )1, ,

Cch 2

n0, ,

Cch 2

n0, ,

Cch 2

n0, ,

Cch 2

n0, ,

Cch 2

n1, ,

Cch 2

n1, ,

Cch 2

n1, ,

Cch 2

n1, ,

C

ch 2n

2n

1, ,C

ch 2n

2n

1, ,

Cch 2

n2

n1, ,

Cch 2

n2

n1, ,

= SF 2n 1+( )

=


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where . For a given SF, there are SF different orthogonal codes.The orthogonal channelisation codes can be easily generated using the tree structureshown in Figure 5.1.1.

The spreading code period is the symbol period, hence, for a given chip rate, thespreading code period depends on the symbol rate.

Parameter Dialog Box: Default parameters shown.

References:

3G TS 25.213: Spreading and Modulation (FDD)

n 1 2 12, , ,=

Cch 1 0, , 1( )=

Cch 2 0, , 1 1,( )=

Cch 2 1, , 1 1,( )=

Cch 4 0, , 1 1 1 1, , ,( )=

Cch 4 1, , 1 1 1 1, , ,( )=

Cch 4 2, , 1 1 1 1, , ,( )=

Cch 4 3, , 1 1 1 1, , ,( )=

Cch 8 0, ,

Cch 8 1, ,Cch 8 2, ,

Cch 8 3, ,

Cch 8 4, ,

Cch 8 5, ,Cch 8 6, ,

Cch 8 7, ,

SF 1= SF 2= SF 4= SF 8=

Figure 5.1.1: Orthogonal code generation structure


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5.1.2 Uplink Short Scrambling Code Generator

Block Name: UplinkSCGen

Abbreviation: ULSCGen

Synopsis: Uplink Short Scrambling Code Generator

See Also: Uplink Long Scrambling Code Generator

Block Inputs: Clock: Normally the chip-rate clock. The code advances on therising edge of the clock input.

Block Outputs: Real: Real (I) code sequence updated on the rising edge of theinput clock signal.

Imaginary: Imaginary (Q) code sequence updated on the risingedge of the input clock signal.

Discussion: The uplink short scrambling code is a 256 chip length code generatedfrom two sequences and , which are obtained from aquaternary sequence . The th quaternary sequenceis calculated by adding three modulo 4 sequences, a quaternary sequence andtwo binary sequences and . The initial value of the sequences is

Parameter RangeDefaultvalue

Definition

User Index 0x1, 0x2,0x3

24 bit user index in hexadec-imal




SSCC

UL

0 n 224 1

cshort 1 n, , i( ) cshort 2 n, , i( )z i( ) n zn i( ) 0 n 16777215 ,

a i( )b i( ) d i( )


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determined from the code number (specified in the parameter dialog box as 24 bituser index n). If is the 24-bit binary representation of the codenumber , the initial values of the registers are loaded as specified below:

[5.1.8]

[5.1.9]

[5.1.10]

[5.1.11]

The sequences , and are generated recursively according to thefollowing equations

[5.1.12]

[5.1.13]

[5.1.14]

is generated as

[5.1.15]

and is extended to length 256 chips by setting . is thenmapped into the real sequences and by using the tablebelow.

0 +1 +1

1 -1 +1

2 -1 -1

3 +1 -1

nn23 n22 n0, , ,

n

a 0( ) 2n0 1 modulo 4+=

a i( ) 2ni modulo 4 i, 1 2 7, , ,= =

b i( ) n8 i+ modulo 2 i, 0 1 7, , ,= =

d i( ) n16 i+ modulo 2 i, 0 1 7, , ,= =

a i( ) b i( ) d i( )

a i( ) a i 3( ) a i 5( ) 3a i 6( )+ +=

2+ a i 7( ) 3a i 8( ) mod 4 i,+ 8 9 254, , ,=

b i( ) b i 1( ) b i 3( )+=

b+ i 7( ) b i 8( ) mod 2 i,+ 8 9 254, , ,=

d i( ) d i 1( ) d i 3( )+=

d+ i 4( ) d i 8( ) mod 2 i,+ 8 9 254, , ,=

zn i( )

zn i( ) a i( ) 2b i( ) 2d i( ) mod 4 i,+ + 0 1 254, , ,= =

zn 255( ) zn 0( )= zn i( )cshort 1 n, , i( ) cshort 2 n, , i( )

zn i( ) cshort 1 n, , i( ) cshort 1 n, , i( )


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Finally the complex valued uplink short scrambling sequence is defined as

[5.1.16]

for , where denotes rounding to nearest lower integer.

The system to generate the 255 chip sequence is shown in the block schematicsection, the generated sequence still needs to be extended by one chip to obtain therequired 256 chip sequence.

Initial Values: The binary representation of the initial value is

loaded in the shift registers as shown below

Cshort n,

Cshort n, i( ) cshort 1 n, , i mod 256( ) 1 j 1( )icshort 2 n, , 2 i mod 256( ) 2( )+

=

i 0 1 255, , ,=

n23 n22 n0, , , n

d 0( )

mod 2mod 2 mod 2

b 0( )

mod 4 mod 4 mod 4 mod 4

33 32

a 0( )

2n0 1+( )mod42n1mod4

2n2mod4

2n3mod4

2n4mod4

2n5mod4

2n6mod4

2n7mod4

n8n9n10n11n12n13n14n15

n16n17n18n19n20n21n22n23

mod 2 mod 2 mod 2

mod n addition

multiplication

delay

Figure 5.1.2: The modulo-4 and two modulo-2 sequence generators.


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Block Schematic:


References:


d i( )

mod 2mod 2 mod 2

b i( )

mod 4 mod 4 mod 4 mod 4

33 32

a i( )

mod 2 mod 2 mod 2

2

2

mod 4

zn i( )mapper

cshort 1 n, , i( )

cshort 2 n, , i( )

mod n addition

multiplication

delay

Figure 5.1.3: Uplink short scrambling code generator.


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5.1.3 Uplink Long Scrambling Code Generator

Block Name: UplinkLCGen

Abbreviation: ULLCGen

Synopsis: This block generates the uplink long scrambling code sequence.

See Also: Uplink Short Scrambling Code Generator

Block Inputs: Clock: Normally the chip-rate clock. The code advances on therising edge of the clock input.

Block Outputs: Real: Real (I) phase of the code sequence, updated on the risingedges of the clock input.

Imaginary: Imaginary (Q) phase of the code sequence, updatedon the rising edges of the clock input.

Discussion: This block generates the long scrambling code used in the uplink. Allphysical channels can be scrambled by a long or a short scrambling code. There are224 long and 224 short scrambling codes.

The long scrambling codes and are Gold sequences, which arethe result of adding modulo 2 two m-sequences, and generated from twogenerator polynomials of degree 25. is a 16777232 chip shifted version

of the sequence .


Definition

Code Number 0 - (225-2) 10 Scrambling code number

Code Period Positive 38400 Code repetition period




LSCC

UL

clong 1 n, , clong 2 n, ,x y

clong 2 n, ,

clong 1 n, ,


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Let be the binary representation of the code number provided bythe user in the parameter dialog box. This value is used as initial condition togenerate the sequence in a linear shift register. If is the th symbol of thesequence , then

[5.1.17]

The initial conditions for sequence are

[5.1.18]

Once the registers have been initialized, the following recursions are used

[5.1.19]

[5.1.20]

By adding and modulo 2, a Gold sequence is obtained

[5.1.21]

takes he values . A real valued Gold sequence that takes values

is defined

[5.1.22]

the sequences and can now be defined as

[5.1.23]

[5.1.24]

The shift register structure used to generate and is shown in theblock schematic section. The uplink complex valued long scrambling sequence

is finally generated as

[5.1.25]

for , and where denotes rounding to the nearest lowerinteger.

n23 n22 n0, , , n

xn xn i( ) ixn

xn 0( ) n0 xn 1( ), n1 xn 23( ), , n23 xn 24( ), 1= = = =y

y 0( ) y 1( ) y 23( ) y 24( ) 1= = = = =

xn i 25+( ) xn i 3+( ) xn i( ) mod 2, i+ 0 225

27, ,= =

y i 25+( ) y i 3+( ) y i 2+( ) y i 1+( ) mod 2, i+ + 0 225

27, ,= =

xn i( ) y i( ) zn

zn i( ) xn i( ) y i( ) modulo 2, i+ 0 1 225

2, , ,= =

zn 0 1,{ } Zn i( )

1 1,{ }

Zn i( )+1 ifzn i( ) 0=

1 ifzn i( ) 1=for i

0 1 225

2, ,= =

clong 1 n, , clong 2 n, ,

clong 1 n, , Zn i( ) i, 0 1 225

2, , ,= =

clong 2 n, , Zn i 16777232+( ) modulo 225

1( )( ) i, 0 1 225

2, , ,= =

clong 1 n, , clong 2 n, ,

Clong n, i( )

Clong n, i( ) clong 1 n, , i( ) 1 j 1( )i

clong 2 n, , 2 i 2( )+( )=

i 0 1 225

2, , ,=


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5.1.4 Downlink Long Scrambling Code Generator

Block Name: DownlinkLCGen

Abbreviation: DLLCGen

Synopsis: Generates the downlink complex scrambling sequence.

Block Inputs: Clock: Normally the chip rate clock. The code advances on the

rising edge of the clock input.

Block Outputs: Real: Real (I) phase of the code sequence, updated on the risingedges of the clock input.


Definition

Scrambling Code Group 1 - 64 1

Group of scrambling code,each consists of 8 primarycodes and 120 secondary

codes

Primary Code Cp0 - Cp7 Cp0 Primary code group

Secondary Code Pri., Cs1 - Cs15 Pri. Secondary code group

Code No. 0-218-1 0 No. of scrambling code

Code Period Positive 38400 Scrambling code periodbefore repeating

Compressed Mode Enable/Disable DisableEnables the use of the

compressed mode

Left Alt. Code Enable/Disable EnableThe left alternative code isused (only in compressed

mode is enabled)

Right Alt. Code Enable/Disable Disable

The right alternative code is

used (only in compressedmode is enabled)




LSCC

DL


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Imaginary: Imaginary (Q) phase of the code sequence, updatedon the rising edges of the clock input.

Discussion: The structure used to generate the downlink scrambling code is shownin the Block Schematic section. It can be seen that a total ofdifferent codes can be generated, but not all of them are used. Only 8192 are used,which are divided into 64 groups of 128 codes. Each group has 8 primary code and120 secondary codes. There is a one to one correspondence between each primarycode and 15 secondary codes, therefore there are secondary codes ineach code group. Table 5.1.1 shows the correspondence between the code numbergenerated and the code group, the primary and the secondary codes.

It can be seen that the primary codes are codes number with

. The secondary codes are codes number with, therefore only codes are used.

In compressed mode each of the scrambling codes has two codes associateddepending on whether left or right alternative codes are used. This can be specifiedin the parameter dialog box when the compressed mode is selected. Thecorrespondence of compressed mode codes with the code group number, theprimary code, the secondary code and the code number are shown in Table 5.1.2.Alternative codes may be used for compressed frames.

Left alternative codes corresponding to code are codes number , whileright alternative codes are codes number . If the channelisation code usedfor non-compressed frames is , left codes are used if and rightcodes if .

The complex valued scrambling sequence is generated by combining two realvalued Gold sequences, which are constructed from two m-sequences generated bymeans of two generator polynomials of degree 18.

Let the two m-sequences be and . These sequences are generated with thefollowing initial conditions

[5.1.26]

[5.1.27]

The recursive expressions which determine the value of subsequent symbols are

[5.1.28]

[5.1.29]

218 1 262143=

15 8 120=

n 16i=

i 0 1 511, , ,= 16i k+k 1 15, ,= n 0 1 8191, , ,=

n n 8192+n 16384+

cch, SF m, m SF 2=0

A numeric identifier for this

transport channel.

TTI {10,20,40,80}Specifies the Transmit TimeInterval (TTI) in milliseconds.

CRC {0,8,12,16,24} Specifies the CRC length in bits.

Coding {conv2,conv3,turbo}Specifies the type of channel

coding: 1/2 rate convolutional, 1/3rate convolutional or turbo.

RMAttribute 1...256

Rate matching attribute, involvedin rate matching calculation anddetermines rate matcher output

block sizes.

SourceType, SourceValue See section on Source Configuration.

DynamicPartList must occur onceDefines the aspects of the

transport channel configurationwhich can change from TTI to TTI.

Element: DynamicPartList

Element Range Definition

TBSmust occur at least

once, may occur morethan once

Specifies the configuration oftransport blocks for a TTI.

Element: TBS

Attribute Range Definition

BlockSize 1...163840Size of an individual transport

block at the input to the channelcoding.

BlockSetSize1...163840 and aninteger multiple of

BlockSize

Total size of the set of transportblocks for channel coding.


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Compressed Mode schedule XML Configuration File Format:

Element: Patterns

Element Range Definition

Patternmust occur at leastonce, may occurmore than once

Specifies the configuration of the acompressed mode pattern.

Element: Pattern

Attribute Range Definition

Active {0,1}Specifies whether or not this

pattern is active; if not it is ignored.

TGCFN 0...255 Connection Frame Number.

TGSN 0...14Starting Slot Number, the start of

Gap 1.

TGL1 0...14 Gap 1 Length.

TGD integerGap Distance, the distance

between the start of Gap 1 andGap 2.

TGL2 0...14 Gap 2 Length.

TGPL1 integer Period of Pattern 1.

TGPL2 integer Period of Pattern 2.a

a. TGPL1 and TGPL2 cannot both be zero.

TGPRC integer Pattern Repetition Count.

CompressionType {SFR,HLS,PUNC}

Specifies the manner in whichCompression is achieved:

Spreading Factor Reduction,Higher Layer Signalling or

Puncturing.

FrameType {A,B}

Specifies the frame type A or B;results in a modified slot format.

See the table of DPCH slot formatsbelow.


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DPCH Slot Formats: This table shows the slot formats resulting from the choiceof SlotFormat attribute in the PhyCH XML configuration element and theFrameType attribute in the Compressed Mode Pattern XML configuration element:


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Source Configuration:

The table below shows the valid combinations of SourceType and SourceValueelements to generate source data. All sources produce a sequence of values 0 and 1i.e. representing bits. In the case of finite-length definition of sources such asbitfield and file, the bit sequence generated will repeat when more bits are requestedfrom this source than are defined by it.

SourceTypea

a. The strings describing SourceType are case-insensitive.

SourceValueinterpretation

SourceValueRange

Definition

pn9integer seed forPN initialisationb

b. If a seed value of 0 is given for any of the PN sequence sources, a randomly chosen seed will be internally generated.

0...511

Generates the bit sequencefrom PN generator with

polynomial with

starting state given by

SourceValue.

pn15integer seed forPN initialisation

0...32767


polynomial with

starting state given bySourceValue.

filestring specifying

filename

a valid filename specifying a file containingwhitespace separated characters 0 and 1

representing bits.

bitfieldstring specifying

bitfieldSee Source Configuration Examples.

zeros -- -- A source producing zeros.

ones -- -- A source producing ones.

pn9_itu integer seed forPN initialisation 0...511


polynomial with

starting state given bySourceValue.

pn23integer seed forPN initialisation

0...8388607


polynomial

with starting state given bySourceValue.

x9 x4 1+ +

x15 x 1+ +

x9 x5 1+ +

x23 x18 1+ +


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Source Configuration Examples:

Example CCTrCH / PhyCH XML configuration:

SourceType SourceValueSource bit sequence

generatedInterpretation

bitfield 1001 1,0,0,1,1,0,0...

SourceValue

interpreted as a binaryvector of bits

bitfield 0xA5 1,0,1,0,0,1,0,1,1,0,1...

SourceValueinterpreted as a

hexidecimal number,converted into a

sequence of bits.a

a. Bit sequence generated will always be a multiple of 4 bits in length i.e. leading zero bits of most significant nibble will be

generated.


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Example Compressed Mode schedule XML configuration:

Block Inputs: None

Block Outputs: PhyCH Chip Real: Real part of the chip output from the physi-cal DPCH channel.

PhyCH Chip Imag: Imaginary part of the chip output from the

physical DPCH channel. CCTrCH Frame: Current frame of data in the coded composite

transport channel. DCH0 TBS: The transport block set bits input to the coding for

the first transport channel in the coded composite. DCH1 TBS: The transport block set bits input to the coding for

the second transport channel in the coded composite.


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Parameter Dialog Box:


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5.3 Channel Coding

Prior to transmission information bits are coded to allow for error detection andcorrection at the receiver. The library provides a number of channel coding blockswhich can be configured with 3GPP standard values. Each coding mechanism (i.e.convolutional coding, turbo coding, CRC coding, interleaving etc.) is implemented

by an individual block. Alternatively the Transport Channel Coder allows all of thetransport channel coding functions to be performed in one block. The followingchannel coding blocks are included in the library:

Cyclic Redundancy Coding (CRC) - Encoder/Decoder (CRCGEN)

Convolutional Encoder (ConvEnc)

Convolutional Decoder (Viterbi Algorithm) (ConvDec)

Turbo Encoder (TurboEnc)

Turbo Decoder (TurboDec)

Rate Matcher (RateMtch)

Interleaver (IntLeave)

De-Interleaver (DeIntLev)

Transport Channel Coder (TrChCdr)

Transport Channel Multiplexer (TrChMux)

CRC

RM

CHCODEC


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5.3.1 Cyclic Redundancy Coding (CRC) - Encoder/Decoder

Block Name: CRCGen

Abbreviation: CRCGen

Synopsis: In encode mode this block reads in data bits segmenting them intotransport channel blocks. A CRC checksum is computed and appended to the block.In decode mode, the block removes the CRC and indicates if any errors occurred inthe block.

Block Inputs: Data Input: The serial input data. The input sample rate mustbe equal to the bit rate.

Block Outputs: Data Out: In encode mode this signal consists of input data(systematic) bits followed by CRC parity bits per block


Definition

Mode Encode/Decode DecodeSelects Encode or Decode

mode

Polynomial

GRCR8,GCRC12,GCRC16,GCC24

GCRC16Selects the polynomial to be

used for CRC checksumcalculation

Block Length (bits) 20

Block length over which theCRC is computed. In this

description the block lengthis denoted as

Offset Delay 0Delay offset in bits or

seconds

Offset in Bits Enable/disable DisableIndicates that offset delay is

specified in bits when

checked.


TRUE Output All 1 TRUE output voltage

FALSE Output All -1 FALSE output voltage

No leading output Enable/disable DisableSee section on leading

output.

CRC

0>

N

0

NM


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period. In this mode the sampling rate (of the output) istimes the input sampling rate. In decode mode this

signal consists of systematic bits which were read from theData Input signal per block period. No error correction is per-formed. The sampling rate is times the input sam-ple rate in decode mode.

Error: This output signal is only required in decode mode (it isset to FALSE in encode mode), and is used to indicate that anerror has been detected (i.e. a discrepancy exists between thedata bits and the parity bits). This signal is TRUE when an errorhas been detected, and FALSE when no error has been detectedin the current data block. The sampling rate is the sample as thatof the Data Out signal.

Discussion: The CRC block can operate in either Encode or Decode mode.

In encode mode the block reads in bits at a time and generates parity bitswhich are appended to the original block to create an output block size ofbits. This is shown in Figure , where are the input data bits, and are thecalculated parity bits.

To produce the parity bits the input bits are mapped to the coefficients of apolynomial where TRUE logic levels are represented by the value 1 and FALSElogic levels are represented by the value 0. The first bit is the coefficient of thehighest power term, the second bit the coefficient of the second highest power term,

and so on as shown below.

[5.3.1]

N M+( ) NM

N N M +( )

N MM N+( )

bi{ } Pj{ }

b1 b2 bN pMpM 1 p1

1 2 N 1+ N 2+ M N+block pos: N

Figure 5.3.1: Output block structure of CRC encoder.

M N

I D( ) biDN i

i 1=

N

b1DN 1

b2DN 2

bN 1 D bN+ + + += =


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The resulting polynomial is then multiplied by and divided by thegenerator polynomial specified by the polynomial parameter, using modulo-2division. The parity bits are the coefficients of the remainder polynomial, .

[5.3.2]

The number of parity bits is determined by the label of the polynomial which isbeing used. For example if is used then there are 16 parity bits. Eq.5.3.3 describes the relationship between the input polynomial, the generatorpolynomial and the remainder polynomial where is the quotient of themodulo-2 division operation. The polynomial in Eq. 5.3.4 describes the output ofthe block in encode mode.

[5.3.3]

[5.3.4]

The generator polynomials used in this block are specified in 3G TS 25.212, andare shown below.

[5.3.5]

[5.3.6]

[5.3.7]

[5.3.8]

In decode mode, the CRC block receives input bits and creates the apolynomial in a similar manner to encode mode but with coefficients. Thispolynomial is then divided by the specified CRC polynomial usingmodulo-2 division. If the remainder is zero, no CRC errors have occurred. Theerroroutput reflects the state of the CRC check. The output stream consists of the

systematic bits of the received block. Noerrorcorrection is performed by thisblock.

The block period is defined as the time for a samples to be read at the inputin encode mode, or samples to be read at the input in decode mode. Thedelay between input and output is equal to the block period irrespective of whatmode the block is operating in.

I D( ) DM

R D( )

R D( ) piDM i

i 1=

M

p1DM 1

p2D

M 2

pM 1 D pM+ + + += =

GCRC16 D( )

Q D( )

DMI D( )GCRCMD( )---------------------------- Q D( ) R D( )

GCRCMD( )----------------------------+=

Y D( ) DMI D( ) R D( )+=

GCRC24 D( ) D24 D23 D6 D5 D 1+ + + + +=

GCRC16 D( ) D16 D12 D5 1+ + +=

GCRC12 D( ) D12 D11 D3 D2 D 1+ + + + +=

GCRC8 D( ) D8 D7 D4 D3 D 1+ + + + +=

M N+( )M N+( )

GCRCM

N

Tb NM N+( )


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Equivalent circuits for encoding and decoding the data are shown below. In both ofthese the set of coefficients are derived from the CRC polynomials in Eq.5.3.5 to 5.3.8.

In encode mode the bits are input to the encoder circuit with switch 1 in the closed.After all the bits are fed in switch 1 is open and the parity bits appear sequentiallyat the output of the circuit.

Initial Values: The shift registers of both the encoder and decoder are initialised to

all zeros.

The implementation of the CRC encoder/decoder block can be represented by shiftregisters.

In decode mode the received bit vector is fed into the error circuit with switch 1closed and switch 2 open. Once all bits are fed into the circuit switch 1 isopened and switch 2 closed. If a any TRUE values appear at the output of the circuitthen an error has occured.

In encode mode N input bits are fed into the parity generator with the switch in theclosed position. After this the register contains the parity bits which can be shiftedout one at a time with the switch in the open position.

gi{ }

g1 g2 gL 1

switch 1

I D( ) Y D( )

Figure 5.3.2: CRC parity generator.

M N+( )

switch 2

g1 g2 gL 1

switch 1

CRC error checker

Y D( ) error

Figure 5.3.3: CRC syndrome generator.


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References:

3G TS 25.212: Multiplexing and channel coding (FDD).


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5.3.2 Convolutional Encoder

Block Name: ConvEnc

Abbreviation: ConvEnc

Synopsis: The convolutional encoder block performs segmentation, tail bitinsertion and convolutional encoding at rate 1/2 or rate 1/3.

Block Inputs: Data Input: Input stream ofsystematic data (data to be

encoded). The sampling rate of the input is denoted as and isinterpreted as one sample per bit.

Block Outputs: Data Output: Output stream of coded data. The sampling rateof the output is with one bit per sample.


Definition

Encoding Rate orDenoted . is the

number of functiongenerators.

Precoded Block Length (bits) 260Number of input bits grouped

together for encoding.Denoted as


True Output All 1 True output voltage

False Output All -1 False output voltage

Delay offset 0 See section on delay offset.

Delay in Samples enable/disable disabledSets delay offset

measurement units.

No Leading Output enable/disable disabledSee section on no leading

output

Release Version{v3.0.0, v3.1.0,v3.2.0, v3.3.0,

v3.4.0}v3.4.0

Defines which version of the3GPP standard the

convolutional encodershould comply with.

1 2 1 3 1 31 R R

1>Ms

0

s

c


96/267


Discussion: This block implements a constraint length , rate( )or rate ( ) convolutional coder. Blocks of (systematic) bitsare received and processed to generate output bits where .

The steps performed on each block are denoted in Figure 5.3.4:

eight tail bits are appended to the block;

the block is applied to one of the function generator circuits in Figure 5.3.5;

the outputs of the function generators are multiplexed to form the output of

the block.

Each encoder produces functions of the incoming bits and multiplexes them at

the output of the block. The following diagram shows the processing steps that ablock goes through for rate 1/2 coding, and how the encoded bits are positionedwithin the output block. is the output bit of the function generator.

As can be seen the bits of the output block alternate between the output bits of thefunction generators, starting from the lowest index. This is also the case for the

convolutional coder, where the output bits appear in the order. The input and output block sizes are therefore related

by .

Note that due to internal buffering the encoded data block will start to appear at theoutput of the coder input samples after the first bit of the input data is read.When one data block is being read in, the previous block is being coded andstreamed to the output.

Initial Values: The shift registers of the convolutional encoders are initialised to

all zeros.

K 9= 1 2R 2= 1 3 R 3= Ms

Mc Mc R Ms 8+( )=

R

R

yir ith rth

b1 b2 bMb3

b1 b2 bMb3 0 0 0 00 00 0

y10 y1

1 y20 y2

1 y30 y3

1 yM K 1+0 yM K 1+

1

tail bit insertion

convolutional encoding (1/2)

first input bit

first output bit

Figure 5.3.4: The steps performed by the convolutional encoders block.

1 3

y10 y1

1 y12 y2

0 y21 y2

2 , , , , , ,{ }Mc R Ms 8+( )=

Ms


97/267


Block Schematic:


References:

TS 25.212: Multiplexing and channel coding (FDD)

1/2 convolutional coder

1/3 convolutional coder

0

1

2

0

1

Figure 5.3.5: The structure of the convolutional coder function generators.

: modulo-2 addition

G0 = 561Oct

G1 = 753Oct

G0 = 557OctG1 = 663OctG2 = 711Oct


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5.3.3 Convolutional Decoder (Viterbi Algorithm)

Block Name: ConvDec

Abbreviation: ConvDec

Synopsis: This block implements a constraint length , rate ( ) orrate ( ) convolutional coder. Blocks of (systematic) bits are receivedand processed to generate output bits where .

This block performs decoding of rate or rate , constraint lengthconvolutionally encoded data using the Viterbi Algorithm (VA). Both hard and soft

decision modes are implemented. The block also removes the tail bitsinserted by the coder for correct trellis termination.

.


Definition

Encoding Rate orDenoted as is the

number of function

generators in the encoder.

Precoded Block Length (bits) 260Block length before coding

(i.e. output block size ofdecoder). Denoted as .

Decision Type. Hard/Soft HardDetermines whether the soft

or hard decision Viterbialgorithm is used.

Signalling Amplitude (v)

(soft decision mode only) 1

Magnitude of signalling

levels.

Quantisation Step (v)

(soft decision mode only)0.2

Voltage step betweenadjacent quantisation levels.

Quantisation Bits

(soft decision mode only)3

Number of bits used torepresent the soft decisions.

Denoted as

Input Threshold All 0 Input high/low threshold.

True Output All 1 True output voltage.

False Output All -1 False output voltage.

Delay Offset 0 See section on delay offset.

K 9= 1 2 R 2=1 3 R 3= Ms

Mc Mc R Ms K 1+( )=

1 2 1 3 K 9=

K 1

1 2 1 3 1 31 R R

0>Ms

0>

0>

18n

0


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Block Inputs: Data Input: Input stream of coded data. The sampling rate ofthe input is with one sample per bit.

Block Outputs: Data Output: Output stream of decoded data. The samplingrate of the output is with one sample for each bit.

Discussion: This block implements a constraint length rate 1/3convolutional decoder using the standard Viterbi Algorithm (VA). The path depthis the same as the precoded block length, .

The block reads in blocks of received samples, decodes them and then strips thetail bits. The output block size is given by .

The Viterbi algorithm is a computationally efficient method of performing maximallikelihood decoding specifically for convolutional codes.

The algorithm works by retracing the all possible sequences of states (paths) thatthe encoder could have progressed through when it generated the coded block. Ametric known as apath matrix is accumulated for each of these. When two pathsarrive at the same state then their path matrices are compared and one of them canbe disregarded. Once the paths have been traced through the whole block of data,the path matrices are compared and one path is selected is the most likely one whichactually occurred at the encoder.

In order to generate a path matrix for a particular path, a metric is required toevaluate each branch of the path. The path matrix is defined as the sum of all of the

branch metrics for that path. Decoding can be performed in either soft or harddecision mode.


measurement units.


output.


v3.4.0}v3.4.0

Defines which version of the3GPP standard the

convolutional decodershould comply with.


Definition

c

s

K 9=

Ms

McK 1 Ms Mc R( ) K 1+=


100/267


In hard decision mode the input to the block is a voltage, which is converted to a bitstream by applying a threshold. Let represent the bit of thesymbol (branch) of a possible path. Let similarly represent the inputbits to the viterbi decoder in hard decision mode, after thresholding. A metric forhow close is to is the hamming distance, defined as:

[5.3.9]

When this metric is used the path whose path matrix is smallest in value, is mostlikely to be the correct path.

In soft decision mode the input to the viterbi decoder ( ) is quantised todifferent levels where and . The metric for a

particular branch is defined as:

[5.3.10]

In soft decoding mode the path with the greatest value of path matrix is most likelyto be the correct path.

Initial Values: The decoder is initialised to the zero state before decoding (all paths

start from the zero state).

cjr 0 1,{ } rt th

jr 0 1,{ }

cjr yjr

j cjr yjrr

=

yjr LL 2

n= yjr 0 1 2 L 1, , ,( )

cjr

j yjr 2cjr 1( )r

=


101/267



References:

TS 25.212: Multiplexing and channel coding (FDD)


102/267


5.3.4 Turbo Encoder

Block Name: TurboEnc

Abbreviation: TurboEnc

Synopsis: The turbo encoder block performs segmentation, tail bit insertion andrate convolutional encoding.

Block Inputs: Data Input: Input stream of coded data. The sampling rate ofthe input is with one sample per bit.

Block Outputs: Data Output: Output stream of coded data. The sampling rateof the output is with one sample per bit.


Definition

Encoding Rate

Ratio of bits in / bits out forthe encoder.

Denoted as

Precoded Block Length (bits) 1296 Input block length






measurement units.


output.

Release Version

{v3.0.0, v3.1.0,

v3.2.0, v3.3.0,v3.4.0}

v3.4.0

Defines which version of the

3GPP standard the turbocoder should comply with.

R 3

1 3 1 31 R

0>

0

fs

fc


103/267


Discussion: This block implements turbo coding using a Parallel ConcatenatedConvolutional Coding (PCCC) scheme. The block reads in blocks of bits, andproduces output blocks of coded bits.The input and output block sizes arerelated by since 12 tail bits are appended to the output of theencoder to terminate the decoder correctly.

Since a block of bits is streamed to the output in the same time as bits areread at the input, the output sampling rate is .

The encoded data block only begins to appear at the output after the last bit of thecorresponding input block has been read. Therefore there is a latency of inputbits between input and output.

The encoding scheme consists of two recursive systematic convolutional encoders

(RSC1 and RSC2) and an interleaver. RSC1 encodes the systematic data, and RSC2encodes an interleaved version of the systematic data. After a block of bits havebeen read into the coder, both the systematic and interleaved data streams begin tobe encoded. For every bit which enters the encoder, three bits are output. The outputsequence is etc.

The interleaver generates a matrix whose size depends on the input block size .The input data block is read into the matrix row by row, and then both intra-row andinter-row permutation is performed. Intra-row permutation is performed on the

row according to a number sequence where the bit in position of the rowis moved to position . Inter-row permutation is performed (after intra-rowpermutation) according to the sequence where row is moved to position. For a precise description of how the interleaver selects the matrix size, and the

sequences and , refer to 3G TS 25.212.

After permutation the matrix is read out column by column. The output of theinterleaver consists of bits, where the extra bits arise because the inputblock does not fit exactly into the matrix. The bits which did not exist in the

original block are pruned bringing the number of bits back down to . Thecombined delay of the interleaving and the pruning operations is bits.

Once an entire block has passed through the encoder trellis termination must beperformed: the two RSCs must be forced to the all 0 state. For both of the RSCsthis is done by applying the feedback from the shift register to the RSC input:putting the input switches in the lower position. The first three tail bits are used toterminate RSC1 (RSC1 input switch in lower position) while RSC2 is disabled. Thelast three tail bits are used to terminate RSC2 (RSC2 input switch in lower position)

while RSC1 is disabled. For trellis termination the bits are then transmitted in thefollowing sequence:

MsMc

Mc RMs 12+=

Mc Msc Mf Ms( ) fs=

Ms

Ms

X 0( ) X 0( ) Y 0( ) X 1( ) X 1( ) Y 1( ), , , , ,

Ms

th

cj i( ) cj i( )ij( ) p j( )

cj i( ) j( )

Ms l+ ll

MsMs

Y t( ) X t 1+( ) Y t 1+( ) X t 2+( ) Y t 2+( ) X t( ) Y t( ) X t 1+( ) Y t 1+( ) X t 2+( ) Y, , , , , , , , , ,


104/267


105/267


5.3.5 Turbo Decoder

Block Name: TurboDec

Abbreviation: TurboDec

Synopsis: The Turbo decoder block performs decoding of rate PCCC turbo-codes using the sub-log MAP (Maximum A Posterior) algorithm.


Definition

Encoding Rate Encoder rate

Precoded Block Length 1296

Size of block in bits beforeencoding was performed.

Denoted .




Signalling Amplitude (v) 1 Magnitude of signallinglevels.

Noise Variance v2 0.001Estimate of the noise

variance.

Decoding Iterations 10Number of decodingiterations performed.






measurement units.


output.


v3.4.0}v3.4.0

Defines which version of the3GPP standard the turbo

decoder should comply with.

1 3

1 3 1 3

0>Ms

0>

0>

0>

0


106/267


Block Inputs: Data Input: Input stream of data to be decoded at one sampleper bit. Sampling frequency is denoted

Block Outputs: Data Output: Output stream of decoded data. Output samplingfrequency is denoted input sample rate /[R * ((M+8)/M)]where R is the rate parameter (2 or 3) and M is the input block

size (excluding tail bits).

Discussion: This block makes use of the sub-log MAP (Maximum A Posterior)algorithm to decode rate

Block Schematic:


fc

fs

1 3

MAPdecoder 1 MAP

decoder 2

interleaver

de-interleaver

interleaver

Figure 5.3.7: Turbo Decoder.


107/267


References:



108/267


5.3.6 Rate Matcher

Block Name: RateMatch

Abbreviation: RateMtch

Synopsis: Implements a rate matching algorithm that punctures or repeats bits toprovide an output bit stream at a different rate to the input bit stream.


Definition

Tx/RxRate Matching/

Rate Recovery

RateMatching

Selects whether the blockperforms rate matching (Tx)

or rate recovery (Rx).

Frame Before Matching (bits)

(uplink mode)

TTI Before Matching (bits)

(downlink mode)

402Number of bits in a frame/TTI

before rate matching/afterrate recovery.

Frame After Matching (bits)(uplink mode)

TTI After Matching (bits)

(downlink mode)

490Number of bits in a frame/TTI

after rate matching/beforerate recovery.

Link Direction Uplink/Downlink UplinkDetermines whether uplinkor downlink transmission/

reception is being performed.

Span (ms)

(Uplink mode only) 10,20,40,80 10

Determines the frame length

and therefore the number offrames per TTI.

Data Coding Type Conv./Turbo Conv.

Selects type of channelcoding or decoding which willbe or has been performed on

the data.

Information Type Hard/Soft HardSelects the type of datawhich is supplied by the

demodulator.




RM

0>

0>


109/267


Block Inputs: Input Data: Input data stream at rate R1 bits/s with R1*Spanbits per Transmission Time Interval (TTI).

Block Outputs: Output Data: Output data stream at a rate of R2 bits/s withR2*Span bits per Transmission Time Interval (TTI).

Discussion: The rate matcher may be placed before the first stage of interleaving orafter it depending on whether the transmission is uplink or downlink. The linkparameter therefore selects which algorithm is to be used depending on the stage at

which the rate matching is performed.

The algorithm applies puncturing and repetition to the input bit stream on a block-by-block basis to match the number of input bits per block to the specified numberof output bits per block. This may be either a rate increase or a rate decrease.

The rate matching is required because frequently the number of bits per TTI that areoutput from the channel coder/interleaver does not match that required to fill a radioframe. (The physical channel resource offers a fixed bit rate according to the

channel rate onto which the transport channels are mapped.) Furthermore, severaltransport channels with differing Quality of Service (QoS) requirements may sharea physical channel in which case the number of bits allocated to each transportchannel in the physical channel mapping must be selected according to the QoSrequired.

The algorithm used to perform rate matching is complex and depends on a numberof parameters. For example if turbo coding is performed then the rate matcher mustnot puncture systematic bits of data.

Please refer to the FDD channel coding specification document 25.212 Section4.2.7 Rate Matching for details of the rate matching algorithm.



measurement units.


output.


v3.4.0}v3.4.0

Defines which version of the3GPP standard the rate

matcher should comply with.


Definition

0


110/267


The Rate Matcher block has a latency of one TTI.

Block Schematic:


References:



111/267


5.3.7 Interleaver

Block Name: IntLeave

Abbreviation: IntLeave

Synopsis: 1st stage or 2nd stage permuting interleaver.


Definition

Link Direction Uplink/Downlink UplinkDetermines whether uplinkor downlink transmission is

being performed.

Position First/Second First

Indicates the position of theinterleaver in relation to the

transport channelmultiplexer.

Span (ms)

(First position only)

10, 20, 40, 80 20Determines the TTI andtherefore the number of

frames per TTI.

TTI Block Length (bits)

(in Uplink this is before radioframe equalisation)

804

Number of bits per TTI. For1st Interleaver this is the

number of bits per column.For second interleaver this is

the entire block size to beinterleaved. Denoted .

Information Type. Hard/Soft HardSelects the type of datawhich is supplied by the

demodulator.





Delay in Samples enable/disable disabled

Sets delay offset

measurement units.


output.

0>

M

0


112/267


Block Inputs: Data Input: Input data stream.

Block Outputs: Data Output: Output (interleaved) data stream.

Discussion: The interleaver block performs 1st and 2nd interleaving for both the

uplink and the downlink. The operation of each is highlighted below.

1st Interleaver

The 1st Interleaver is a block interleaver with inter-column permutations. Data isread input data into a rectangular matrix row by row (see Eq. 5.3.11) The columnsof the matrix are then re-arranged depending on the number of frames per TTI andthen read out column by column.

Each column represents one TTI worth of data. Therefore the number of columnsis set to the number of frames per TTI (1,2,4 or 8). The columns are re-arranged

according to one of the permutation patterns shown in Table 5.3.1.is the original position of the th permuted column. Note that the entire block sizeof the 1st Interleaver is and not just .

[5.3.11]

2nd Interleaver

The second interleaver operates on the output of the transport channel multiplexerand has a fixed span of 10 ms or 1 frame. The incoming data is read into a

rectangular array as shown by Eq. 5.3.11 but with the number of columns fixedto 30. The number of rows is chosen as the minimum integer such that .Since the size of the input block is not necessarily a multiple of 30, the matrix maycontain a number of bits ( ) which were not in the original block. If is the blocksize then .

TTI (ms)Numb

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