36 V, 18 MHz, Low Noise, Fast Settling Single Supply, RRO ... · The ADA4625-1/ADA4625-2 build on Analog Devices, Inc., high voltage, single-supply, rail-to-rail output (RRO), precision

36 V, 18 MHz, Low Noise, Fast Settling Single Supply, RRO, JFET Op Amp

Data Sheet ADA4625-1/ADA4625-2

Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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FEATURES Wide gain bandwidth product: 18 MHz typical High slew rate: 48 V/µs typical Low voltage noise density: 3.3 nV/√Hz typical at 1 kHz Low peak-to-peak noise: 0.15 µV p-p, 0.1 Hz to 10 Hz Low input bias current: ±15 pA typical at TA = 25°C Low offset voltage: ±80 µV maximum at TA = 25°C Offset voltage drift: ±1.2 µV/°C maximum at TA = −40°C to 85°C Fast settling: 0.01% in 700 ns typical Wide range of operating voltages

Dual-supply operation: ±2.5 V to ±18 V Single-supply operation: 5 V to 36 V

Input voltage range includes V− Rail-to-rail output High capacitive load drive capability Output short-circuit current: ±46 mA No phase reversal Unity-gain stable

APPLICATIONS PLL filter amplifiers Transimpedance amplifiers Photodiode sensor interfaces Low noise charge amplifiers

GENERAL DESCRIPTION The ADA4625-1/ADA4625-2 build on Analog Devices, Inc., high voltage, single-supply, rail-to-rail output (RRO), precision junction field effect transistor (JFET) input op amps, taking that product type to a level of speed and low noise that has not been made available to the market previously.

The ADA4625-1/ADA4625-2 provide optimal performance in high voltage, high gain, and low noise applications. The input common-mode voltage range includes the negative supply, and the output swings rail to rail. This enables the user to maximize dynamic input range in low voltage, single supply applications without the need for a separate negative voltage power supply for ground sense.

The combination of wide bandwidth, low noise, and low input bias current makes the ADA4625-1/ADA4625-2 especially suitable for phase-locked loop (PLL), active filter amplifiers and for high tuning voltage (VTUNE), voltage controlled oscillators (VCOs) and preamplifiers where low level signals require an amplifier that provides both high amplification and wide bandwidth.

PIN CONFIGURATION

NC 1

–IN 2

+IN 3

V– 4

NC8

V+7

OUT6

NC5

ADA4625-1

TOP VIEW(Not to Scale)

1589

3-00

1

NOTES1. NC = NO CONNECTION. DO NOT CONNECT TO THIS PIN.2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND, V+ OR V– PLANE, OR LEAVE IT FLOATING.

Figure 1.

The ADA4625-1/ADA4625-2 are unity-gain stable, and there is no phase reversal when input range exceeds either supply rail by 200 mV. The output is capable of driving loads up to 1000 pF and/or 600 Ω loads.

The ADA4625-1/ADA4625-2 are specified for operation over the extended industrial temperature range of −40°C to +125°C and operates from +5 V to +36 V (±2.5 V to ±18 V) with specifi-cations at +5 V and ±18 V. The devices are available in an 8-lead SOIC package with an exposed pad (EPAD).

1589

3-15

7

100

10

11 10 100 100k10k1k

VOLT

AG

E N

OIS

E D

ENSI

TY (n

V/√H

z)

FREQUENCY (Hz)

VSY = 5VVSY = ±18V

Figure 2. Voltage Noise Density vs. Frequency

Table 1. Related Precision JFET Operational Amplifiers Single Dual Quad Not applicable AD823A Not applicable AD8510 AD8512 AD8513 AD8610 AD8620 Not applicable ADA4610-1 ADA4610-2 ADA4610-4 ADA4622-1 ADA4622-2 ADA4622-4 ADA4627-1/ADA4637-1 Not applicable Not applicable

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ADA4625-1/ADA4625-2 Data Sheet

Rev. A | Page 2 of 35

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Pin Configuration ............................................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3

Electrical Characteristics—±18 V Operation ........................... 3 Electrical Characteristics—5 V Operation................................ 5

Absolute Maximum Ratings ............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 23

Input and Gain Stages ................................................................ 23

Output Stage ................................................................................ 23 No Phase Inversion .................................................................... 24 Supply Current ............................................................................ 24

Applications Information .............................................................. 25 Active Loop Filter for Phase-Locked Loops (PLLs) .............. 25 ADA4625-1 Advantages and Design Example ....................... 26 Transimpedance Amplifier ....................................................... 27 DAC Output Driver ................................................................... 31 Recommended Power Solution ................................................ 32 Input Overvoltage Protection ................................................... 32 Driving Capacitive Loads .......................................................... 32 Thermal Management ............................................................... 32 Typical Applications ................................................................... 33

Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35

REVISION HISTORY 6/2019—Rev. 0 to Rev. A Added ADA4625-2 ........................................................ Throughout Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 5 Added Figure 4 and Table 7; Renumbered Sequentially ............. 8 Changes to Table 6 ............................................................................ 8 Added Figure 16 .............................................................................. 10 Added Figure 25 and Figure 28..................................................... 12 Added Figure 17, Figure 38, and Figure 40 ................................. 14 Added Figure 61 and Figure 64..................................................... 18 Added Figure 65 to Figure 70 ........................................................ 19 Added Figure 73 and Figure 76..................................................... 20

Added Figure 77 and Figure 80 .................................................... 21 Added Figure 84 ............................................................................. 22 Added DAC Output Driver Section, Figure 105, Figure 106, and Figure 107 ........................................................................................ 31 Added Typical Applications Section, Figure 109, and Figure 110 ......................................................................................... 33 Added Figure 111 and Figure 112 ................................................ 34 Updated Outline Dimensions ....................................................... 35 Changes to Ordering Guide .......................................................... 35

10/2017—Revision 0: Initial Version





SPECIFICATIONS ELECTRICAL CHARACTERISTICS—±18 V OPERATION Supply voltage (VSY) = ±18 V, common-mode voltage (VCM) = output voltage (VOUT) = 0 V, TA = 25°C, unless otherwise noted.

Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS

Offset Voltage VOS ADA4625-1 ±15 ±80 µV ADA4625-2 ±100 µV −40°C < TA < +125°C ±250 µV

Offset Voltage Drift TCVOS −40°C < TA < +85°C ±0.2 ±1.2 µV/°C −40°C < TA < +125°C ±0.5 ±2.1 µV/°C

Input Bias Current IB ±15 ±75 pA ADA4625-1, −40°C < TA < +125°C ±5.5 nA ADA4625-2, −40°C < TA < +125°C ±7 nA

Input Offset Current IOS ±2 ±50 pA ADA4625-1, −40°C < TA < +125°C ±0.4 nA ADA4625-2, −40°C < TA < +125°C ±0.7 nA

Input Voltage Range IVR −18.2 +14.5 V Common-Mode Rejection Ratio CMRR VCM = −18.2 V to +14.5 V 97 115 dB

−40°C < TA < +125°C 94 dB VCM = −18.2 V to +12 V 115 130 dB −40°C < TA < +125°C 110 dB

Large Signal Voltage Gain AVO Load resistance (RL) = 2 kΩ, VOUT = −17.5 V to +17.5 V

140 150 dB

−40°C < TA < +125°C 135 dB RL = 600 Ω, VOUT = −15 V to +15 V 130 135 dB ADA4625-1, −40°C < TA < +125°C 115 dB ADA4625-2, −40°C < TA < +125°C 100 dB

Input Capacitance Differential Mode CDM ADA4625-1 8.6 pF

ADA4625-2 13.8 pF Common Mode CCM ADA4625-1 11.3 pF

ADA4625-2 13.3 pF Input Resistance RDM Differential mode 1012 Ω

RCM Common mode, VCM from −18 V to +12 V 1012 Ω

OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 2 kΩ 17.65 17.72 V

−40°C < TA < +125°C 17.5 V RL = 600 Ω 17.0 17.28 V −40°C < TA < +125°C 16.75 V

Output Voltage Low VOL RL = 2 kΩ −17.74 −17.70 V −40°C < TA < +125°C −17.5 V RL = 600 Ω −17.4 −17.0 V −40°C < TA < +125°C −16.85 V

Output Current IOUT Dropout voltage (VDROPOUT) < 1 V ±33 mA Short-Circuit Current ISC ±46 mA Closed-Loop Output Impedance ZOUT f = 1 MHz, closed-loop gain (AV) = +1 2 Ω

AV = +10 18 Ω AV = +100 29 Ω

POWER SUPPLY Power Supply Rejection Ratio PSRR VSY = ±5 V to ±18 V 105 120 dB

−40°C < TA < +125°C 102 dB Supply Current per Amplifier ISY VOUT = 0 V 4.0 4.5 mA

−40°C < TA < +125°C 5 mA





Parameter Symbol Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE

Slew Rate SR VOUT = ±10 V, RL = 2 kΩ, AV = −1 48 V/µs VOUT = ±10 V, RL = 2 kΩ, AV = −5 44 V/µs

Gain Bandwidth Product GBP AV = 100 18 MHz Unity-Gain Crossover UGC AV = 1 12.4 MHz −3 dB Bandwidth −3 dB AV = 1 16 MHz Phase Margin ΦΜ ADA4625-1 88 Degrees

ADA4625-2 75 Degrees Channel Separation CS VIN = 15 V p-p, f = 1 kHz, RL = 2 kΩ, AV = 100 108 dB

VIN = 15 V p-p, f = 10 kHz, RL = 2 kΩ, AV = 100 88 dB Settling Time tS

ADA4625-1 To 0.1%, input voltage (VIN) = 10 V step, RL = 2 kΩ, load capacitance (CL) = 15 pF, AV = −1

500 ns

To 0.01%, VIN = 10 V step, RL = 2 kΩ, CL = 15 pF, AV = −1

700 ns

ADA4625-2 To 0.1%, VIN = 10 V step, RL = 2 kΩ, CL = 15 pF, AV = −1

700 ns

To 0.01%, VIN = 10 V step, RL = 2 kΩ, CL = 15 pF, AV = −1

1200 ns

ELECTROMAGNETIC INTERFERENCE (EMI) REJECTION RATIO

EMIRR

f = 1000 MHz ADA4625-1/ADA4625-2 56 dB f = 2400 MHz ADA4625-1 93 dB

ADA4625-2 73 dB

NOISE PERFORMANCE Peak-to-Peak Noise eN p-p 0.1 Hz to 10 Hz 0.15 µV p-p Voltage Noise Density eN f = 10 Hz 5.5 nV/√Hz

f = 100 Hz 3.6 nV/√Hz f = 1 kHz 3.3 nV/√Hz

Current Noise Density iN f = 1 kHz 4.5 fA/√Hz Total Harmonic Distortion + Noise THD + N AV = 1, f = 10 Hz to 20 kHz, RL = 2 kΩ,

VIN = 6 VRMS at 1 kHz Bandwidth = 80 kHz 0.0003 %

−109 dB Bandwidth = 500 kHz 0.0007 %

−103 dB





ELECTRICAL CHARACTERISTICS—5 V OPERATION VSY = 5 V, VCM = 1.5 V, VOUT = VSY/2, TA = 25°C, unless otherwise noted.

Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS

Offset Voltage VOS ±0.1 ±0.6 mV −40°C < TA < +125°C ±1.0 mV

Offset Voltage Drift TCVOS ADA4625-1, −40°C < TA < +85°C ±0.4 ±2.6 µV/°C ADA4625-2, −40°C < TA < +85°C ±4.5 µV/°C ADA4625-1, −40°C < TA < +125°C ±0.7 ±3.6 µV/°C ADA4625-2, −40°C < TA < +125°C ±4.5 µV/°C

Input Bias Current IB ±15 ±50 pA ADA4625-1, −40°C < TA < +125°C ±3.5 nA ADA4625-2, −40°C < TA < +125°C ±4 nA

Input Offset Current IOS ±2 ±50 pA −40°C < TA < +125°C ±150 pA

Input Voltage Range IVR −0.2 +1.5 V

Common-Mode Rejection Ratio CMRR VCM = 0 V to 1.5 V 74 90 dB −40°C < TA < +125°C 70 dB

Large Signal Voltage Gain AVO RL = 2 kΩ to V−, VOUT = 0.35 V to 4.65 V 130 145 dB −40°C < TA < +125°C 120 dB RL = 600 Ω to V−, VOUT = 0.5 V to 4.5 V 120 130 dB −40°C < TA < +125°C 110 dB

Input Capacitance Differential Mode CDM ADA4625-1 12.1 pF

ADA4625-2 12.7 pF Common Mode CCM ADA4625-1 16.3 pF

ADA4625-2 18.4 pF Input Resistance RDM Differential mode 1012 Ω

RCM Common mode, VCM from 0 V to 1.5 V 1012 Ω

OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 2 kΩ to V− 4.75 4.82 V

−40°C < TA < +125°C 4.7 V RL = 600 Ω to V− 4.65 4.74 V −40°C < TA < +125°C 4.55 V

Output Voltage Low VOL RL = 2 kΩ to V+ 0.17 0.22 V −40°C < TA < +125°C 0.3 V RL = 600 Ω to V+ 0.25 0.3 V −40°C < TA < +125°C 0.45 V

Output Current IOUT VDROPOUT < 1 V ±33 mA Short-Circuit Current ISC ±46 mA Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = +1 2 Ω

AV = +10 18 Ω AV = +100 29 Ω

POWER SUPPLY Power Supply Rejection Ratio PSRR VSY = 4.5 V to 10 V 80 97 dB

−40°C < TA < +125°C 75 dB Supply Current per Amplifier ISY VOUT = 0 V 3.9 4.3 mA

−40°C < TA < +125°C 4.8 mA





Parameter Symbol Test Conditions/Comments Min Typ Max UnitDYNAMIC PERFORMANCE

Slew Rate SR VOUT = 0.5 V to 4.5 V, RL = 2 kΩ, AV = −1 32 V/μs VOUT = 0.5 V to 4.5 V, RL = 2 kΩ, AV = −5 27 V/μs

Gain Bandwidth Product GBP AV = 100 16 MHz Unity-Gain Crossover UGC AV = 1 11.2 MHz −3 dB Bandwidth −3 dB AV = 1 16 MHz Phase Margin ΦM ADA4625-1 86 Degrees

ADA4625-2 71 DegreesChannel Separation CS VIN = 15 V p-p, f = 1 kHz, RL = 2 kΩ, AV = 100 108 dB

VIN = 15 V p-p, f = 100 kHz, RL = 2 kΩ, AV = 100 88 dB Settling Time tS

ADA4625-1 To 0.1%, VIN = 4 V step, RL = 2 kΩ, CL = 15 pF, AV = −1 600 ns To 0.01%, VIN = 4 V step, RL = 2 kΩ, CL = 15 pF, AV = −1

950 ns

ADA4625-2 To 0.1%, VIN = 4 V step, RL = 2 kΩ, CL = 15 pF, AV = −1 1250 ns To 0.01%, VIN = 4 V step, RL = 2 kΩ, CL = 15 pF, AV = −1

1350 ns

EMI REJECTION RATIO EMIRR f = 1000 MHz ADA4625-1/ADA4625-2 56 dB f = 2400 MHz ADA4625-1 87 dB

ADA4625-2 79 dB

NOISE PERFORMANCE Peak-to-Peak Noise eN p-p 0.1 Hz to 10 Hz 0.15 μV p-p Voltage Noise Density eN f = 10 Hz 5.5 nV/√Hz

f = 100 Hz 3.6 nV/√Hz f = 1 kHz 3.3 nV/√Hz

Current Noise Density iN f = 1 kHz 4.5 fA/√Hz Total Harmonic Distortion + Noise THD + N AV = 1, f = 10 Hz to 20 kHz, RL = 2 kΩ,

VIN = 0.6 VRMS at 1 kHz Bandwidth = 80 kHz ADA4625-1 0.0003 %

−109 dB ADA4625-2 0.002 %

−93 dBBandwidth = 500 kHz ADA4625-1 0.0007 %

−103 dB ADA4625-2 0.004 %

−89 dB





ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage 40 V Input Voltage (V−) − 0.2 V to

(V+ ) + 0.2 V Differential Input Voltage (V−) − 0.2 V to

(V+) + 0.2 V Input Current1 ±20 mA Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +125°C Junction Temperature Range −65°C to +150°C Lead Temperature, Soldering (10 sec) 300°C Electrostatic Discharge (ESD)

Human Body Model (HBM)2

ADA4625-1 1.25 kVADA4625-2 1.5 kV

Field Induced Charge Device Model (FICDM)3

ADA4625-1 1.25 kVADA4625-2 1.25 kV

1 The input pins have clamp diodes connected to the power supply pins. Limit the input current to 20 mA or less whenever input signals exceed the power supply rail by 0.3 V.

2 ESDA/JEDEC JS-001-2011 applicable standard. 3 JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required.

Table 5. Thermal Resistance Package Type1, 2 θJA

3 θJC UnitRD-8-1 52.8 5.7 °C/W

1 Values were obtained per JEDEC standard JESD-51. 2 Although the exposed pad can be left floating, it must be connected to the

GND, or the V+ or V− plane for proper thermal management. 3 Board layout impacts thermal characteristics such as θJA. When proper thermal

management techniques are used, a better θJA can be achieved. Refer to the Thermal Management section for additional information.

ESD CAUTION





PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NC 1

–IN 2

+IN 3

V– 4

NC8

V+7

OUT6

NC5

ADA4625-1


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3-00

2

NOTES1. NC = NO CONNECTION. DO NOT CONNECT TO THIS PIN.2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND, V+ OR V– PLANE, OR LEAVE IT FLOATING.

Figure 3. ADA4625-1 Pin Configuration

Table 6. Pin Function Descriptions, ADA4625-1 Pin No. Mnemonic Description 1, 5, 8 NC No Connection. Do not connect to these pins. 2 −IN Inverting Input Pin. 3 +IN Noninverting Input Pin. 4 V− Negative Supply Voltage Pin. 6 OUT Output Pin. 7 V+ Positive Supply Voltage Pin.

EPAD Exposed Pad. Connect the exposed pad to GND, V+ or V− plane, or leave it floating.

OUT A 1

–IN A 2

+IN A 3

V– 4

V+8

OUT B7

–IN B6

+IN B5

ADA4625-2


NOTES1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND, V+ OR V– PLANE, OR LEAVE IT FLOATING. 15

893-

101

Figure 4. ADA4625-2 Pin Configuration

Table 7. Pin Function Descriptions, ADA4625-2 Pin No. Mnemonic Description 1 OUT A Output Pin for Channel A. 2 −IN A Inverting Input Pin for Channel A. 3 +IN A Noninverting Input Pin for Channel A. 4 V− Negative Supply Voltage Pin. 5 +IN B Noninverting Input Pin for Channel B. 6 −IN B Inverting Input Pin for Channel B. 7 OUT B Output Pin for Channel B. 8 V+ Positive Supply Voltage Pin.

EPAD Exposed Pad. Connect the exposed pad to GND, V+ or V− plane, or leave it floating.





TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VCM = 0 V, unless otherwise noted.

50

0–100 100

NU

MB

ER O

F A

MPL

IFIE

RS

VOS (µV)

10

20

30

40

–75 –50 –25 0 25 50 75

VSY = ±18VRL = ∞

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3

Figure 5. Input Offset Voltage (VOS) Distribution, Supply Voltage (VSY) = ±18 V

70

0–2.0 2.0

NU

MB

ER O

F A

MPL

IFIE

RS

TCVOS (µV/°C)

10

20

30

40

50

60

–1.5 –1.0 –0.5 0.0 0.5 1.0 1.5

VSY = ±18V

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Figure 6. Input Offset Voltage Drift (TCVOS) Distribution (−40°C to +125°C ), VSY = ±18 V

600

400

–600–18.2 16.8

V OS

(µV)

VCM (V)

–400

–200

0

200

–13.2 –8.2 –3.2 1.8 6.8 11.8

VSY = ±18V90 AMPLIFIERS

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5

Figure 7. VOS vs. Common-Mode Voltage (VCM), VSY = ±18 V

25

20

15

10

5

0–400 400

NU

MB

ER O

F A

MPL

IFIE

RS

VOS (µV)–300 –200 –100 0 100 200 300

VSY = 5VVCM = 1.5VRL = ∞

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Figure 8. VOS Distribution, VSY = 5 V

45

0–2.0 2.0

NU

MB

ER O

F A

MPL

IFIE

RS

5

10

15

20

25

30

35

40

–1.5 –1.0 –0.5 0.0 0.5 1.0 1.5TCVOS (µV/°C)

VSY = 5VVCM = 1.5V

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7

Figure 9. TCVOS Distribution (−40°C to +125°C ), VSY = 5 V

1000

–1000–0.2 3.4

–800

–600

–400

–200

0

200

400

600

800

V OS

(µV)

0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0VCM (V)

VSY = 5V90 AMPLIFIERS

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Figure 10. VOS vs. VCM, VSY = 5 V





120

100

80

60

40

20

0–60 10

NU

MB

ER O

F A

MPL

IFIE

RS

IB (pA)–50 –40 –30 –20 –10 0

VSY = ±18VRL = ∞

1589

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0Figure 11. Input Bias Current (IB) Distribution, VSY = ±18 V

90

0–40 40

NU

MB

ER O

F A

MPL

IFIE

RS

IOS (pA)

VSY = ±18VRL = ∞

10

20

30

40

50

60

70

80

–30 –20 –10 0 10 20 30

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1

Figure 12. Input Offset Current (IOS) Distribution, VSY = ±18 V

200

–1600

0

–40 125

I B (p

A)

TEMPERATURE (°C)

–1400

–1200

–1000

–800

–600

–400

–200

–25 –10 5 20 35 50 65 80 95 110

VSY = 5V, VCM = 1.5VVSY = ±18V

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2

Figure 13. ADA4625-1 IB vs. Temperature

120

100

80

60

40

20

0–60 10

NU

MB

ER O

F A

MPL

IFIE

RS

IB (pA)–50 –40 –30 –20 –10 0


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3

Figure 14. IB Distribution, VSY = 5 V

90

0–40 40

NU

MB

ER O

F A

MPL

IFIE

RS

IOS (pA)

10

20

30

40

50

60

70

80

–30 –20 –10 0 10 20 30


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4

Figure 15. IOS Distribution, VSY = 5 V

500

–4000

0

–40 125

I B (p

A)

TEMPERATURE (°C)

–3500

–3000

–2500

–2000

–1500

–1000

–500

–25 –10 5 20 35 50 65 80 95 110


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2

Figure 16. ADA4625-2 IB vs. Temperature





100

–100–18.2 17.8

–80

–60

–40

–20

0

20

40

60

80

I B (p

A)

VCM (V)–14.2 –10.2 –6.2 –2.2 1.8 5.8 9.8 13.8

VSY = ±18V

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5

Figure 17. IB vs. VCM, VSY = ±18 V

10n

1n

100p

10p

1p–18.2 17.8

AB

SOLU

TEVA

LUE

OF

I B(A

)

–14.2 –10.2 –6.2 –2.2 1.8 5.8 9.8 13.8VCM (V)

TA = 25°C

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6

TA = 125°C

TA = 85°C

Figure 18. Absolute Value of IB vs. VCM for Various Temperatures, VSY = ±18 V

100

10

1

0.10.001 100

(V+)

– V

OUT

(V)

IOUT SOURCE (mA)0.01 0.1 1 10

VSY = ±18V

+125°C+85°C+25°C–40°C

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Figure 19. Dropout Voltage ((V+) − VOUT) vs. Output Current (IOUT) Source for Various Temperatures, VSY = ±18 V

300

–300–0.2 3.8

–250

–200

–150

–100

–50

0

50

100

150

200

250

I B (p

A)

VSY = 5V

VCM (V)0.3 0.8 1.3 1.8 2.3 2.8 3.3

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8

Figure 20. IB vs. VCM, VSY = 5 V

–0.2 5.0

10n

1n

100p

10p

1p

AB

SOLU

TEVA

LUE

OF

I B(A

)

VCM (V)0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6

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9

TA = 25°C

TA = 125°C

TA = 85°C

Figure 21. Absolute Value of IB vs. VCM for Various Temperature, VSY = 5 V

10

1

0.10.001 0.01 0.1 101 100

(V+)

– V

OU

T (V

)

IOUT SOURCE (mA)

VSY = 5VVCM = 1.5V

TA = +125°CTA = +85°CTA = +25°CTA = –40°C

1589

3-02

0

Figure 22. ((V+) − VOUT) vs. IOUT Source for Various Temperatures, VSY = 5 V





100

10

1

0.10.001 100

V OUT

– (V

–)(V

)

IOUT SINK (mA)0.01 0.1 1 10

VSY = ±18V

TA = +125°CTA = +85°CTA = +25°CTA = –40°C

1589

3-02

1

Figure 23. Dropout Voltage (VOUT − (V−)) vs. IOUT Sink for Various Temperatures, VSY = ±18 V

120

–40100 1k 10k 100k 10M1M 100M

GA

IN (d

B)

FREQUENCY (Hz)

–20

0

20

40

60

80

100

270

225

180

135

90

45

0

–45

–90

PHA

SE (D

egre

es)

VSY = ±18VRL = 1kΩ

CL = 300pFCL = 100pFCL = 0pF

1589

3-02

2

Figure 24. ADA4625-1 Open-Loop Gain and Phase vs. Frequency, VSY = ±18 V

120

–40100 1k 10k 100k 10M1M 100M

GA

IN (d

B)

FREQUENCY (Hz)

–20

0

20

40

60

80

100

270

225

180

135

90

45

0

–45

–90

PHA

SE (D

egre

es)


VSY = ±18VRL = 1kΩ

1589

3-10

3

Figure 25. ADA4625-2 Open-Loop Gain and Phase vs. Frequency, VSY = ±18 V

10

1

0.10.001 0.01 0.1 101 100

V OU

T –

(V–)

(V)

IOUT SINK (mA)

VSY = 5VVCM = 1.5V

TA = +125°CTA = +85°CTA = +25°CTA = –40°C

1589

3-02

4

Figure 26. (VOUT − (V−)) vs. IOUT Sink for Various Temperatures, VSY = 5 V

120

–40100 1k 10k 100k 10M1M 100M

GA

IN (d

B)

FREQUENCY (Hz)

–20

0

20

40

60

80

100

PHA

SE (D

egre

es)

VSY = 5VRL = 1kΩ


1589

3-02

5

270

225

180

135

90

45

0

–45

–90

Figure 27. ADA4625-1 Open-Loop Gain and Phase vs. Frequency, VSY = 5 V

120

–40100 1k 10k 100k 10M1M 100M

GA

IN (d

B)

FREQUENCY (Hz)

–20

0

20

40

60

80

100

270

225

180

135

90

45

0

–45

–90

PHA

SE (D

egre

es)


VSY = 5VRL = 1kΩ

1589

3-10

4

Figure 28. ADA4625-2 Open-Loop Gain and Phase vs. Frequency, VSY = 5 V





10 100 1k 10k 100k 10M1M 100MFREQUENCY (Hz)

60

–20

GA

IN (d

B)

–10

10

0

20

30

40

50

VSY = ±18V

1589

3-02

3

AV = 100

AV = 10

AV = 1

Figure 29. Gain vs. Frequency for Various Closed-Loop Gains, VSY = ±18 V

1000

0.001

OU

TPU

TIM

PED

ANC

E(Ω

)

100 1k 10k 100k 10M1M 100MFREQUENCY (Hz)

0.01

0.1

1

10

100

VSY = ±18V15

893-

027

AV = 100 AV = 10 AV = 1

Figure 30. Output Impedance (ZOUT) vs. Frequency, VSY = ±18 V


VSY = ±18V100

–20

PSR

R (d

B)

0

20

40

60

80–PSRR+PSRR

1589

3-02

8

Figure 31. Power Supply Rejection Ration (PSRR) vs. Frequency, VSY = ±18 V


60

–20

GA

IN (d

B)

–10

10

0

20

30

40

50

VSY = 5V

1589

3-02

6

AV = 100

AV = 10

AV = 1

Figure 32. Gain vs. Frequency for Various Closed-Loop Gains, VSY = 5 V

1000

0.001

OU

TPU

T IM

PED

AN

CE

(Ω)

100 1k 10k 100k 10M1M 100MFREQUENCY (Hz)

0.01

0.1

1

10

100

VSY = 5V

1589

3-03

0

AV = 100 AV = 10 AV = 1

Figure 33. ZOUT vs. Frequency, VSY = 5 V


100

–20

PSR

R (d

B)

0

20

40

60

80

VSY = 5VVCM = 1.5V

–PSRR+PSRR

1589

3-03

1

Figure 34. PSRR vs. Frequency, VSY = 5 V





140

20100M 1G

EMIR

R (d

B)

FREQUENCY (Hz)

40

60

80

100

120

10M 10G

VSY = 5VVSY = ±18V

1589

3-02

9

Figure 35. ADA4625-1 EMI Rejection Ratio (EMIRR) vs. Frequency

45

40

35

30

25

20

15

10

5

01 10 100 1k

OVE

RSH

OO

T (%

)

LOAD CAPACITANCE (pF)

VSY = ±18VRL = 2kΩVIN = 100mV p-p

OS+OS– AV = +1

AV = –1

1589

3-03

4

Figure 36. ADA4625-1 Small Signal Overshoot (OS±) vs. Load Capacitance, VSY = ±18 V

45

40

35

30

25

20

15

10

5

01 10 100 1k

OVE

RSH

OO

T (%

)


VSY = ±18VRL = 2kΩVIN = 100mV p-p

OS+OS– AV = +1

AV = –1

1589

3-10

6

Figure 37. ADA4625-2 OS± vs. Load Capacitance, VSY = ±18 V

140

20100M 1G

EMIR

R (d

B)

FREQUENCY (Hz)

40

60

80

100

120

10M 10G

VSY = 5VVSY = ±18V

1589

3-10

5

Figure 38. ADA4625-2 EMIRR vs. Frequency

40

35

30

25

20

15

10

5

01 10 100 1k

OVE

RSH

OO

T (%

)


VSY = 5VVCM = 1.5VRL = 2kΩVIN = 100mV p-p

OS+OS–

AV = +1

AV = –1

1589

3-03

7

Figure 39. ADA4625-1 OS± vs. Load Capacitance, VSY = 5 V

01 10 100 1k

OVE

RSH

OO

T (%

)


45

40

35

30

25

20

15

10

5

VSY = 5VRL = 2kΩVIN = 100mV p-p

OS+OS– AV = +1

AV = –1

1589

3-10

7

Figure 40. ADA4625-2 OS± vs. Load Capacitance, VSY = 5 V





140

60–40 125

CM

RR

(dB

)

TEMPERATURE (°C)

70

80

90

100

110

120

130

–25 –10 5 20 35 50 65 80 95 110

VSY = ±18V, VCM = –18.2V TO +14.5VVSY = ±18V, VCM = –18.2V TO +12.0VVSY = 5V, VCM = 0V TO 1.5V

1589

3-03

6

Figure 41. CMRR vs. Temperature

20

15

10

5

0

–5

–10

–15

–200 0.5 2.01.0 2.51.5 3.0 3.5

VOLT

AG

E (V

)

TIME (µs)

VSY = ±18VRL = 2kΩCL = 100pF

1589

3-03

5

Figure 42. Large Signal Transient Response, AV = +1, VSY = ±18 V

20

15

10

5

0

–5

–10

–15

–200 0.5 2.01.0 2.51.5 3.0 3.5

VOLT

AG

E (V

)

TIME (µs)

VSY = ±18VRL = 2kΩCL = 100pF

1589

3-03

9

Figure 43. Large Signal Transient Response, AV = −1, VSY = ±18 V


120

0

CM

RR

(dB

)

10

20

30

40

50

60

70

80

90

100

110VSY = 5VVSY = ±18V

1589

3-03

3

Figure 44. CMRR vs. Frequency

4

3

2

1

0

–1

–20 0.5 2.01.0 2.51.5 3.0 3.5

OU

TPU

T VO

LTA

GE

(V)

TIME (µs)

VSY = 5VRL = 2kΩCL = 100pF

1589

3-03

8

Figure 45. Large Signal Transient Response, AV = +1, VSY = 5 V

5

4

3

2

1

0

–10 0.5 2.01.0 2.51.5 3.0 3.5

OU

TPU

T VO

LTA

GE

(V)

TIME (µs)

VSY = 5VVCM = 1.5VRL = 2kΩCL = 100pF

1589

3-04

2

Figure 46. Large Signal Transient Response, AV = −1, VSY = 5 V





0.10

0.05

0

–0.05

–0.100 0.5 2.01.0 2.51.5 3.0 3.5

VOLT

AG

E (V

)

TIME (µs)

VSY = ±18VRL = 2kΩCL = 100pFVIN = 0.1V p-p

1589

3-04

0

Figure 47. Small Signal Transient Response, AV = 1, VSY = ±18 V

0.10

0.05

0

–0.05

–0.100 0.5 2.01.0 2.51.5 3.0 3.5

VOLT

AG

E (V

)

TIME (µs)

VSY = ±18VRL = 2kΩCL = 100pFVIN = 0.1V p-p

1589

3-04

1

Figure 48. Small Signal Transient Response, AV = −1, VSY = ±18 V

10

0

–10

–20

5

–5

–15

–25

–30

20

10

0

–10

15

5

–5

–15

–20

INPU

T VO

LTA

GE

(V)

OU

TPU

T VO

LTA

GE

(V)

TIME (200ns/DIV)

VSY = ±18VVIN = 5.4V p-p

VINVOUT

1589

3-04

5

Figure 49. Negative Overload Recovery, AV = −10, VSY = ±18 V

1.60

1.55

1.50

1.45

1.400 0.5 2.01.0 2.51.5 3.0 3.5

VOLT

AG

E (V

)

TIME (µs)

VSY = 5VVCM = 1.5VRL = 2kΩCL = 100pFVIN = 0.1V p-p

1589

3-04

3

Figure 50. Small Signal Transient Response, AV = 1, VSY = 5 V

1.60

1.55

1.50

1.45

1.400 0.5 2.01.0 2.51.5 3.0 3.5

VOLT

AG

E (V

)

TIME (µs)

VSY = 5VVCM = 1.5VRL = 2kΩCL = 100pFVIN = 0.1V p-p

1589

3-04

4

Figure 51. Small Signal Transient Response, AV = −1, VSY = 5 V

1.0

0.5

–0.5

–1.5

0

–1.0

–2.0

–3.0

–2.5

2.5

2.0

1.0

0

–1.0

0.5

1.5

–0.5

–1.5

INPU

T VO

LTA

GE

(V)

OU

TPU

T VO

LTA

GE

(V)

TIME (200ns/DIV)

(V+) = 3.5V, (V–) = –1.5VVCM = 0VVIN = 0.75V p-p

VINVOUT

1589

3-04

8

Figure 52. Negative Overload Recovery, AV = −10, VSY = 5 V





5

0

–10

–20

–5

–15

–25

–35

–30

35

30

20

10

0

15

25

5

–5

INPU

T VO

LTA

GE

(V)

OU

TPU

T VO

LTA

GE

(V)

TIME (200ns/DIV)

VSY = ±18VVIN = 5.4V p-p

VINVOUT

1589

3-04

6

Figure 53. Positive Overload Recovery, AV = −10, VSY = ±18 V

10

0

–10

5

–5

–15

–30

–25

–20

INPU

T VO

LTA

GE

(V)

TIME (400ns/DIV)

VSY = ±18VRL = 2kΩCL = 100pFDUT AV = –1

ERROR BANDPOST GAIN = 20

1589

3-04

7

+100mV

0V

–100mV

INPUT

OUTPUT

Figure 54. ADA4625-1 Negative Settling Time to 0.1%, VSY = ±18 V

10

0

–10

5

–5

–15

–30

–25

–20

INPU

T VO

LTA

GE

(V)

TIME (400ns/DIV)



1589

3-05

1

+10mV0V–10mV

INPUT

OUTPUT


0.5

–0.5

–1.5

0

–1.0

–2.0

–3.5

–3.0

–2.5

14

12

8

4

0

6

10

2

–2

INPU

T VO

LTA

GE

(V)

OU

TPU

T VO

LTA

GE

(V)

TIME (200ns/DIV)

(V+) = 3.5V, (V–) = –1.5VVCM = 0VVIN = 0.75V p-p

VINVOUT

1589

3-04

9

Figure 56. Positive Overload Recovery, AV = −10, VSY = 5 V

5

1

–3

3

–1

–5

–11

–9

–7 0

INPU

T VO

LTA

GE

(V)

TIME (400ns/DIV)

VSY = 5VVCM = 1.5VRL = 2kΩCL = 100pFDUT AV = –1

1589

3-05

0

+40mV

–40mV


INPUT

OUTPUT

Figure 57. ADA4625-1 Negative Settling Time to 0.1%, VSY = 5 V

4

0

–4

2

–2

–6

–12

–10

–8 0

INPU

T VO

LTA

GE

(V)

TIME (400ns/DIV)


1589

3-05

4

+4mV

–4mV


INPUT

OUTPUT

Figure 58. AD4625-1 Negative Settling Time to 0.01%, VSY = 5 V





10

0

–10

5

–5

–15

–30

–25

–20

INP

UT

VO

LT

AG

E (

V)

TIME (400ns/DIV)


158

93-0

52


+100mV

0V

–100mV

INPUT

OUTPUT

Figure 59. ADA4625-1 Positive Settling Time to 0.1%, VSY = ±18 V

10

0

–10

5

–5

–15

–30

–25

–20

INP

UT

VO

LT

AG

E (

V)

TIME (400ns/DIV)


158

93

-05

3


+10mV

0V–10mV

INPUT

OUTPUT


10

0

–10

5

–5

–15

–30

–25

–20

INP

UT

VO

LT

AG

E (

V)

TIME (400ns/DIV)

VSY = ±18VVCM = 0VRL = 2kΩCL = 100pFDUT AV = –1


+100mV

0V

–100mV

INPUT

OUTPUT

158

93-

108


5

1

–3

3

–1

–5

–11

–9

–7 0

INP

UT

VO

LT

AG

E (

V)

TIME (400ns/DIV)


1589

3-0

55

+40mV

–40mV


INPUT

OUTPUT

Figure 62. ADA4625-1 Positive Settling Time to 0.1%, VSY = 5 V

4

0

–4

2

–2

–6

–12

–10

–8 0

INP

UT

VO

LT

AG

E (

V)

TIME (400ns/DIV)


158

93-0

56

+4mV

–4mV


INPUT

OUTPUT


4

0

–4

2

–2

–6

–12

–10

–8 0

INP

UT

VO

LT

AG

E (

V)

TIME (400ns/DIV)


+40mV

–40mV


INPUT

OUTPUT

1589

3-1

09

Figure 64. ADA4625-2 Negative Settling Time to 0.1%, VSY = 5 V





10

0

–10

5

–5

–15

–30

–25

–20

INPU

T VO

LTA

GE

(V)

TIME (400ns/DIV)



+10mV0V–10mV

INPUT

OUTPUT

1589

3-11

0


10

0

–10

5

–5

–15

–30

–25

–20

INPU

T VO

LTA

GE

(V)

TIME (400ns/DIV)



+100mV

0V

–100mV

INPUT

OUTPUT

1589

3-11

1


10

0

–10

5

–5

–15

–30

–25

–20

INPU

T VO

LTA

GE

(V)

TIME (400ns/DIV)



+10mV

0V–10mV

INPUT

OUTPUT

1589

3-11

2


4

0

–4

2

–2

–6

–12

–10

–8 0

INPU

T VO

LTA

GE

(V)

TIME (400ns/DIV)


+10mV

–10mV


INPUT

OUTPUT

1589

3-11

3

Figure 68. AD4625-2 Negative Settling Time to 0.01%, VSY = 5 V

4

0

–4

2

–2

–6

–12

–10

–8 0

INPU

T VO

LTA

GE

(V)

TIME (400ns/DIV)


+40mV

–40mV


INPUT

OUTPUT

1589

3-11

4


4

0

–4

2

–2

–6

–12

–10

–8 0

INPU

T VO

LTA

GE

(V)

TIME (400ns/DIV)


+10mV

–10mV


INPUT

OUTPUT

1589

3-11

5






10

1

0.1

0.01

0.001

0.00010.001 0.01 0.1 1 10

THD

+ N

(%)

AMPLITUDE (V rms)

BW = 80kHz, AV = +1BW = 80kHz, AV = –1BW = 500kHz, AV = +1BW = 500kHz, AV = –1

VSY = ±18VRL = 2kΩFREQUENCY = 1kHz

1589

3-05

8

Figure 71. ADA4625-1 Total Harmonic Distortion + Noise (THD + N) vs. Amplitude, VSY = ±18 V (BW Means Bandwidth)

0.1

0.01

0.001

0.000120 200 2k 20k

THD

+ N

(%)

FREQUENCY (Hz)

VSY = ±18VRL = 2kΩVIN = 6V rms

1589

3-05

9


Figure 72. ADA4625-1 THD + N vs. Frequency, VSY = ±18 V

10

1

0.1

0.01

0.001

0.00010.001 0.01 0.1 1 10

THD

+ N

(%)

AMPLITUDE (V rms)


VSY = ±18VRL = 2kΩFREQUENCY = 1kHz

1589

3-11

6

Figure 73. ADA4625-2 THD + N vs. Amplitude, VSY = ±18 V

10

1

0.1

0.01

0.001

0.00010.001 0.01 0.1 1

THD

+ N

(%)

AMPLITUDE (V rms)

VSY = 5VRL = 2kΩFREQUENCY = 1kHz

1589

3-06

1


Figure 74. ADA4625-1 THD + N vs. Amplitude, VSY = 5 V

0.1

0.01

0.001

0.000120 200 2k 20k

THD

+ N

(%)

FREQUENCY (Hz)

VSY = 5VRL = 2kΩVIN = 0.6V rms

1589

3-06

2


Figure 75. ADA4625-1 THD + N vs. Frequency, VSY = 5 V

10

1

0.1

0.01

0.001

0.00010.001 0.01 0.1 1

THD

+ N

(%)

AMPLITUDE (V rms)

VSY = 5VRL = 2kΩFREQUENCY = 1kHz


1589

3-11

8

Figure 76. ADA4625-2 THD + N vs. Amplitude, VSY = 5 V





0.1

0.01

0.001

0.000120 200 2k 20k

TH

D +

N (

%)

FREQUENCY (Hz)

VSY = ±18VRL = 2kΩVIN = 6V rms


15

893

-11

7

Figure 77. ADA4625-2 THD + N vs. Frequency, VSY = ±18 V

50n

V/D

IV

TIME (1s/DIV)

VSY = 5VVSY = ±18V

158

93-

06

0

Figure 78. 0.1 Hz to 10 Hz Noise

400

300

200

100

0

–100

–200

–300

–4004 168 2420 2812 32 36

VO

S (

µV

)

VSY (V)

5 AMPLIFIERSTA = 25°C

1589

3-0

65

VCM = VSY/2

Figure 79. VOS vs. VSY

0.1

0.01

0.001

0.000120 200 2k 20k

TH

D +

N (

%)

FREQUENCY (Hz)

VSY = 5VRL = 2kΩVIN = 0.6V rms


15

893

-11

9

Figure 80. ADA4625-2 THD + N vs. Frequency, VSY = 5 V

100

10

11 10 100 100k10k1k

VO

LT

AG

E N

OIS

E D

EN

SIT

Y (

nV

/√H

z)

FREQUENCY (Hz)

VSY = 5VVSY = ±18V

15

89

3-0

57

Figure 81. Voltage Noise Density vs. Frequency

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.0

1.5

0.5

00 4 168 2420 2812 32 36

I SY

(m

A)

VSY (V)

1589

3-0

63

TA = –40°C

TA = +125°C

TA = +85°C

TA = +25°C

VCM = VSY/2

Figure 82. Supply Current (ISY) vs. VSY for Various Temperatures





140

60–40 125

PSR

R (d

B)

TEMPERATURE (°C)

70

80

90

100

110

120

130

–25 –10 5 20 35 50 65 80 95 110

VSY = ±5V TO ±18VVSY = +4.5V TO +10V

1589

3-03

2

Figure 83. PSRR vs. Temperature

0

–140

–120

–100

–80

–60

–40

–20

10k 100k 1M 100M10M

CH

AN

NEL

SEP

AR

ATI

ON

(dB

)

FREQUENCY (Hz)

VSY = ±18VVSY = ±2.5V

AV = 10VIN = 1V p-pRL = 2kΩ

1589

3-12

0

Figure 84. Channel Separation vs. Frequency

25

–25–40 125

TEMPERATURE (°C)

–20

–15

–10

–5

0

5

10

15

20

V OS

(µV)

–25 –10 5 20 35 50 65 80 95 110


1589

3-00

9

Figure 85. VOS vs. Temperature

40

35

30

25

20

15

10

5

010k 100k 1M 10M

OU

TPU

T VO

LTA

GE

(V p

-p)

FREQUENCY (Hz)

VSY = ±18VVSY = ±2.5V

MAXIMUMOUTPUTVOLTAGEWITHOUT SID

1589

3-06

4

Figure 86. Maximum Peak-to-Peak Output Voltage Without Slew Rate Induced Distortion (SID) vs. Frequency





THEORY OF OPERATION Figure 87 shows the simplified circuit diagram for the ADA4625-1/ADA4625-2. The JFET input stage architecture offers the advantages of low input bias current, high bandwidth, high gain, low noise, and no phase reversal when the applied input signal exceeds the common-mode voltage range. The output stage is rail to rail with high drive characteristics and low dropout voltage for both sinking and sourcing currents.

INPUT AND GAIN STAGES To achieve high input impedance, low noise, low offset, and low offset drift, the ADA4625-1/AD4625-2A uses large input N channel JFETs (M1 and M2). These JFETs operate with the S source at about 1.2 V above the G gate. In the worst case, the source is only 0.9 V above the gate. By design, the normal operation of the input tail current (ITAIL) extends down to 0.6 V above V−, which gives the ADA4625-1/ADA4625-2 an input common-mode range down to 0.2 V below V− with margin. Resistive loads keep the noise low. The BUFF1 buffer drives the top of the input load resistors (R1 and R2), keeping the voltage drop across M1 and M2 nearly constant, making a virtual cascode. The differences

of the input voltages of +IN and –IN steer ITAIL through M1 and M2 to R1 and R2, generating a differential voltage. The first voltage to current gain block (GM1) translates that differential voltage into differential currents (I1 and I2) that drive the current mirror (Q1 and Q2), which generates a differential voltage between the reference node and gain node. JFET inputs of the second voltage to current gain block (GM2) maximizes the gain node impedance, giving the ADA4625-1/ADA4625-2 a high gain.

OUTPUT STAGE The GM2 gain block generates two pairs of differential currents. One pair drives the bottom current mirror (Q3 and Q4) and the NPN output transistor (Q7), and the second pair drives the top current mirror (Q5 and Q6) and the output PNP transistor (Q8). The common emitter output transistors (Q7 and Q8) source and sink current rail to rail. GM2 also senses the base voltages of Q7 and Q8 and adjusts the I4 and I6 currents; with no output load, Q7 and Q8 collector currents are 0.6 mA. In addition, GM2 clamps the base voltages of Q7 and Q8 so neither completely turns off.

+IN

+IN

V–

V+

INPUTTAIL CURRENT

–IN

OUTTCVOSTRIM

JFETINPUT PAIR

5 VLEVEL SHIFT

DG GD

S

G GD

S

D

S

SM4 M3

M1 M2

Q10

I1 I2

I5 I6

I3I4

BIAS

ITC1

ITAIL

ITC2

Q9

Q1

CCOMP2

CCOMP1

OUTPUTPNP

OUTPUTNPN

Q2

–IN

GM1

R2R1

DIFFERENTIALVOLTAGE

INPUT LOADRESISTORS

AND VOS TRIM

DIFFERENTIALCURRENTS

GAIN NODE

REF NODE

V/I GAIN

BUFF1

Q3 Q4

Q7

Q8

Q5 Q6

GM2V/I GAIN ANDOUTPUTBIAS

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Figure 87. Simplified Circuit Diagram





NO PHASE INVERSION Rail-to-rail output (RRO) amplifiers without rail-to-rail input (RRI) are prone to phase inversion because the output can drive the input outside of the normal common-mode range, causing the output to go in the wrong direction and latch up. To prevent phase inversion, the input must control the input at all times. Even though the RRO of the ADA4625-1/ADA4625-2 input stage (M1, M2, R1, and R2) operates correctly down to 0.2 V below V−, it does not operate correctly within 2.5 V of V+. The ADA4625-1/ADA4625-2 guarantees no phase inversion by implementing an input pair (M3 and M4) to extend the common-mode range to 0.2 V above V+, with reduced performance. M3 and M4 are not active in the normal common-mode range. Figure 88 shows that the input voltage exceeds both supplies by 200 mV with no phase inversion at the output.

–25

–20

–15

–10

–5

0

5

10

15

20

25

INPU

T VO

LTA

GE

AN

DO

UTP

UT

VOLT

AG

E(V

)

TIME (200µs/DIV)

VIN

VOUT

VSY = ±18VVIN = 36.4V p-pAV = 1

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7

Figure 88. No Phase Reversal if the Input Range Exceeds the Power Supply by 200 mV

SUPPLY CURRENT The supply current (ISY) is the quiescent current drawn by the op amp with no load. Figure 89 and Figure 90 show that the quiescent current varies with the common-mode input voltage. The shape of ISY vs. VCM at higher VCM shows saturation of BUFF1 and the ITAIL turn off.

2.0

2.5

3.0

3.5

4.0

4.5

5.0

–18.2 –12.2 –6.2 –0.2 5.8 11.8 17.8

I SY

(mA

)VCM (V)

TA = +85°C

TA = +25°C

TA = +125°C

TA = –40°C

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8

Figure 89. ISY vs. VCM, VSY = ±18 V

2.0

2.5

3.0

3.5

4.0

4.5

5.0

–0.2 0.7 1.6 2.5 3.4 4.3 5.2

I SY

(mA

)

VCM (V)

TA = +85°C

TA = +25°C

TA = +125°C

TA = –40°C

1589

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9

Figure 90. ISY vs. VCM, VSY = 5 V





APPLICATIONS INFORMATION ACTIVE LOOP FILTER FOR PHASE-LOCKED LOOPS (PLLS) PLL Basic

A PLL is a feedback system that combines a phase detector (PD), a loop filter, and a voltage controlled oscillator (VCO) that is so connected that the oscillator maintains a constant frequency (or phase angle) relative to the reference signal. The functional block diagram of a basic PLL is shown in Figure 91.

PHASEDETECTOR

CHARGEPUMP

N DIVIDER

LOOPFILTER VCOfREF fOUT

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Figure 91. Basic PLL

The phase detector detects the phase difference between the input reference signal and the feedback signal. The resulting error signal is proportional to the relative phase of the input and the feedback signals. The charge pump converts the PD error signal into current pulses. A loop filter circuit is typically required to integrate and smooth the source and sink current pulses from the charge pump into a voltage, which in turn drives the VCO. The VCO outputs a range of frequencies depending on the voltage level at its tuning port. By making the frequency N divider programmable, the VCO frequency can be tuned in either integer steps or fractional amounts characterizing the PLL as either an integer-N PLL or a fractional-N PLL. Because a PLL is a negative feedback loop, the output of the VCO adjusts as necessary until the frequency error signal is zero and the PLL is in lock. The output frequency is given by fOUT = N × fREF.

Figure 92 shows the block diagram of the basic PLL model in the Laplace transform format, where fREF is the frequency of the input signal, and fOUT is the frequency of the VCO output signal. Because the phase difference is the integral of the frequency difference, there is a 1/s term in the PLL loop.

PHASEDETECTOR

+

–PD

CHARGEPUMP

LOOPFILTER

N DIVIDER

VCO

fREF fOUTKd Z(s) KV

1N

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2

1s

Figure 92. Basic PLL Model

Loop Filter

The loop filter, which smooths out the error signal, is a critical part of the system. For applications that require low phase noise and a wide tuning range, design the VCO with a low gain and a large input voltage range to satisfy these requirements. When the required VCO tuning voltage is higher than the maximum voltage the charge pump can supply, implement an active loop filter comprising of an op amp with gain to accommodate the higher tuning voltages. Figure 93 and Figure 94 illustrate the typical active loop filters in inverting and noninverting topologies, respectively, with prefiltering.

CHARGEPUMP

OUTPUT VCOINPUT

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Figure 93. Typical Active Loop Filter—Inverting Topology

CHARGEPUMP

OUTPUT

VCOINPUT

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Figure 94. Typical Active Loop Filter—Noninverting Topology

The inverting topology has the advantage of biasing the charge pump output at a fixed voltage, typically one-half the charge pump voltage (VP/2), which is optimal for spur performance. When using the inverting topology, ensure that the PLL IC allows the phase detector polarity to be inverted for the correct polarity voltage at the output of the op amp for driving the VCO.





ADA4625-1 ADVANTAGES AND DESIGN EXAMPLE The op amp choice for an active filter affects the key performance parameters of the PLLs: frequency range, phase noise, spurious frequencies, and lock time. The output of the filter directly affects the generated frequency and phase. Low noise is essential because any voltage noise applied to the tuning port of the VCO is amplified by the VCO gain and translated into phase noise. Low input bias current is also recommended because the op amp bias current must be sourced from the PLL phase detector/ charge pump, and any mismatch or leakage at the output of the phase detector between the up and down currents causes ripples and reference spurs.

With 18 MHz gain bandwidth product (GBP), low input bias currents (±15 pA), low voltage noise density (3.3 nV/√Hz), ultralow current noise density, and low 1/f corner frequency, the ADA4625-1 is an ideal op amp for using in a PLL active loop filter. The ADA4625-1 does not require a negative voltage supply because of its ground sensing input. The rail-to-rail output stage is beneficial in terms of increasing the flexibility in biasing the op amp so that the output range of the PLL is mapped efficiently onto the input range of the VCO. In addition, the wide 5 V to 36 V operating supply range makes the ADA4625-1 a versatile choice for the design of a wide variety of active loop filters.

Figure 96 shows the ADA4625-1 as the loop filter for the ADF4159, a 13 GHz fractional-N synthesizer. The phase detector polarity of the ADF4159 is programmed to negative because the ADA4625-1 is used in an inverting active loop filter

configuration. The VCO is set up to feedback the VCO/2 output to the ADF4159. The loop filter has a 900 kHz loop bandwidth (LBW) and a phase margin of 58° with 2.5 mA charge pump current. Lowering the bandwidth further improves phase noise at the expense of increased PLL lock time.

Figure 95 shows the PLL loop filter transfer function. Capacitor C1 and Resistor R1 change the phase detector current pulses into a continuous time voltage waveform. At frequencies lower than the R2C2 zero, the amplifier and R1C2 form an integrator. Between the R2C2 zero and the R2C3 pole, the gain is constant at the value set by R2/R1. Above the R2C3 pole, the amplifier is an integrator until R1C3 becomes a feedforward noninverting zero path around the amplifier. Resistor R3 and Capacitor C4 add an additional pole in the loop filter signal path. Setting the R3C4 pole below the R2C3 pole reduces the effect of the R1C3 feedforward zero.

GA

IN (d

B)

LOG FREQUENCY

0dB

R2C2 ZERO

R2/R1AMP GAIN

R3C4 POLE

R2C3 POLE

R1C1 POLE

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Figure 95. PLL Loop Filter Transfer Function

ADF4159FRACTIONAL-NSYNTHESIZER

11.4GHz TO 12.8GHzVCO

RFINx CP

3.3V 1.8V

AVDD

5V

VCC

DVDD

3.3V

VP

AGND

GNDRFOUT

11.4GHz TO 12.8GHz

ADA4625-1

1µF

47kΩ

47kΩ

15V3.3nF

33pF

1kΩ

100pF

52pFVTUNERFOUT/2

5.7GHz TO 6.4GHz

3.3V

6dB PAD6GHz

12GHz OUTPUT

REFIN100MHzDGND SDGNDCPGND

C1220pF

C3

C2

C4100pF

R1100Ω

R2

R3365Ω

U4

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Figure 96. Block Diagram of ADA4625-1 Active Loop Filter for ADF4159

http://www.analog.com/ADF4159?doc=ADA4625-1-4625-2.pdf








PLLs in which the loop gain passes through 0 dB above the R2C2 zero and below the R2C3 pole and R3C4 pole are stable. At low charge pump currents, the loop gain passes through zero above R2C2 zero. At high charge pump currents, the loop gain passes through zero below the R2C3 pole and R3C4 pole (see Figure 97).

1589

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7

GA

IN (d

B)

0

LOG FREQUENCY

0dB FULL LOOP GAINLOW CURRENT

0dB FULL LOOP GAINHIGH CURRENT

LOOP FILTER GAINLOOP WITHOUT FILTER, HIGH CURRENTLOOP WITHOUT FILTER, LOW CURRENTLOOP FILTERFULL LOOP, HIGH CURRENTFULL LOOP, LOW CURRENT

Figure 97. Gain vs. Frequency of PLL and Loop Filter

Figure 98 shows the measured phase noise vs. frequency offset from 12 GHz carrier for different charge pump currents (ICP). Generally, most operations have a charge pump current of 2.5 mA and below. Refer to the UG-383 User Guide for details on running these tests and setting up the software required.

–180

–160

–140

–120

–100

–80

–60

1k 10k 100k 1M 10M 100M

PHA

SE N

OIS

E (d

Bc/

Hz)

FREQUENCY OFFSET FROM 12GHz CARRIER (Hz)

ICP = 4.7mA

ICP = 2.5mA

ICP = 0.31mA

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8

Figure 98. Phase Noise vs. Frequency Offset from 12 GHz Carrier for Different Charge Pump Currents (ICP)

The Analog Devices simulation tool, ADIsimPLL, allows the design and simulation of PLL loop filter topologies and has a library of Analog Devices op amps built in. The simulation tool accurately predicts PLL closed-loop phase noise and is able to model the effect of op amp noise along with the noise of the other PLL loop components. For more information about the ADIsimPLL design tools, refer to www.analog.com/ADIsimPLL.

TRANSIMPEDANCE AMPLIFIER The ADA4625-1 is an excellent choice for low noise transimpe-dance amplifier (TIA) applications. While its low voltage and current noise maximize signal-to-noise ratio (SNR), its low voltage offset and input bias current minimize the dc error at the amplifier output. Having a true ground sense capability, the ADA4625-1 is ideal for single-supply operation. In addition, its rail-to-rail output swing allows the detection and amplification of a wide range of input current signals. Figure 99 shows the ADA4625-1 as a current to voltage (I-V) converter with an electrical model of a photodiode.

–

+

VOUT

VB

CD

CM

CMRSH = 1011ΩCDID

CF

RF

1589

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1ADA4625-1

Figure 99. Equivalent TIA Circuit

Photodiodes can operate in either photovoltaic mode (zero bias) or photoconductive mode (with an applied reverse-bias across the diode). Mode selection depends on the speed and dark current requirements of the application and the choice of photodiode. In photovoltaic mode, the dark current is at a minimum and is preferred for low frequency and/or low light level applications (that is, PN photodiodes). Photoconductive mode is better for applications that required faster and linear responses (that is, PIN photodiodes); however, the tradeoffs include increases in dark and noise currents.

The following transfer function describes the transimpedance gain of Figure 99:

FF

FDOUT RsC

RIV

+=

1(1)

where: VOUT is the desired output dc voltage of the op amp. ID is the output current of the photodiode. RF and CF are the feedback resistor and capacitor. The parallel combination of RF and CF sets the signal bandwidth. s is the s plane.

Set RF such that the maximum attainable output voltage corresponds to the maximum diode output current. Because signal levels increase directly with RF, while the noise due to RF increases with the square root of the resistor value, employing the full output swing maximizes the SNR.

http://www.analog.com/UG-383?doc=ADA4625-1-4625-2.pdf

http://www.analog.com/ADIsimPLL?doc=ADA4625-1-4625-2.pdf







It is important to distinguish between the signal gain and the noise gain (NG) because the noise gain characteristics determine the net circuit stability. The noise gain has the same transfer function as the noninverting signal gain, which follows:

FF

FINSHF

SH

F

CsRCCRRs

RR

NG+

++×

+=

1))(//(1

1 (2)

where: RSH is the diode shunt resistance. CIN is the total input capacitance consisting of the sum of the diode shunt capacitance (CD), the input capacitance of the amplifier (CDM + CCM), and the external stray capacitance. CIN and RF produce a zero in the noise gain transfer function and the zero frequency (fZ) is as follows:

))(//(21

FINSHFZ CCRR

f+π

= (3)

Because the photodiode shunt resistance RSH >> RF, the circuit behavior is not impacted by the effect of the junction resistance, and fZ simplifies to

)(2π1

FINFZ CCR

f+

= (4)

Figure 100 shows the TIA noise gain superimposed upon the open loop gain of the amplifier. For the system to be stable, the noise gain curve must intersect with the open loop response with a net slope of less than 20 dB/decade. In Figure 100, the dotted line shows an uncompensated noise gain (CF = 0 pF) intersecting with the open loop gain at the frequency (fX) with a slope of 20 dB/decade, indicating an unstable condition.

fZ fp fx fN

fGBP

FREQUENCY

GA

IN

UNCOMPENSATED(CF = 0pF)

CF

CIN

OPEN LOOP GAIN

NOISE GAIN

SIGNAL BANDWIDTH

COMPENSATED

1 +

1589

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2

R1R21 +

Figure 100. Generalized TIA Noise Gain and Transfer Function

The instability caused by CIN can be compensated by adding CF to introduce a pole at a frequency equal to or lower than fX. The pole frequency is as follows:

FFP CR

f2π

1= (5)

Setting the pole at the fX frequency maximizes the signal bandwidth with a 45° phase margin but is marginal for stability, as indicated by the dashed line. Because fX is the geometric mean of fZ and the gain bandwidth product frequency (fGBP) of the amplifier, calculate fX by

GBPZX ff f= (6)

Substituting Equation 4 and Equation 5 into Equation 6, the CF value that produces fX is

GBPF

GBPINFF fR

fCRC

π

π++=

4

811(7)

If 8π × RF × CIN × fGBP >> 1, Equation 7 simplifies to

GBPF

INF fR

CC

π=

2(8)

Adding CF also sets the signal bandwidth at fP. Substitute Equation 8 into Equation 5 and rearrange the equation for the signal bandwidth in terms of fGBP, RF, and CIN:

INF

GBPP CR

ff

π=

2(9)

Notice the attainable signal bandwidth is a function of the time constant RFCIN and the fGBP of the amplifier. To maximize the signal bandwidth, choose an op amp with high bandwidth and low input capacitance, and operate the photodiode in reverse bias to reduce its junction capacitance.

Because the input current noise of the FET input op amp is negligible, and the shot noise of the photodiode is negligible due to the filtering effect of the shunt capacitance, the dominant sources of output noise in the wideband photodiode TIA circuit are the input voltage noise of the amplifier eN and the thermal noise generated by RF.

At low frequencies, the circuit noise gain is 1 + RF/RSH. At frequencies equal to or greater than fZ, the noise gain begins to increase and plateau when the gain is 1 + CIN/CF (see Figure 100). In addition, the noise bandwidth frequency, fN (where the compensated noise gain intersecting the open loop gain), can be estimated by

GBPFIN

FN f

CCC

f)( +

= (10)





Design Example

As a design example, Figure 101 shows the ADA4625-1 configured as a TIA amplifier in a photodiode preamp application. Assuming the photodiode has a CD of 5 pF and an ID of 200 µA, and the desired full-scale VOUT is 10 V, and using Equation 1, RF is 50 kΩ.

0.1µF

+15V

49.9kΩ

VOUT

1kΩ

2.2pF

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ADA4625-1

Figure 101. Single-Supply TIA Circuit Using the ADA4625-1

The ADA4625-1 input capacitance (CCM + CDM) is 19.9 pF; therefore, the total input capacitance (CIN) is 24.9 pF. By substituting CIN = 24.9 pF, RF = 50 kΩ, and fGBP = 18 MHz into Equation 7 and Equation 9, the resulting feedback capacitor value (CF) and the −3 dB signal bandwidth (fP) are 2.2 pF and 1.45 MHz, respectively.

Figure 102 and Figure 103 show the compensations of the TIA circuit. The system has a bandwidth of 1.45 MHz when it is maximized for a signal bandwidth with CF = 2.2 pF. Increasing CF to 3.9 pF reduces the bandwidth to 0.82 MHz; however, it greatly reduces the overshoot (see Figure 104). In practice, an optimum CF value is determined experimentally by varying it slightly to optimize the output pulse response.

1

10

100

1k

10k

100k

1M

–20

0

20

40

60

80

100

1k 10k 100k 1M 10M 100M 1G 10G

I-V G

AIN

(Ω)

GA

IN (d

B)

FREQUENCY (Hz)

OPEN-LOOPGAIN

NOISE GAIN

I-V GAIN

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Figure 102. Compensating the TIA, CF = 2.2pF

1

10

100

1k

10k

100k

1M

–20

0

20

40

60

80

100

1k 10k 100k 1M 10M 100M 1G 10G

I-V G

AIN

(Ω)

GA

IN (d

B)

FREQUENCY (Hz)

OPEN-LOOPGAIN

NOISE GAIN

I-V GAIN

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5

Figure 103. Compensating the TIA, CF = 3.9 pF

–50

0

50

100

150

OU

TPU

TVO

LTAG

E(%

)

TIME(1µS/DIV)

CF = 3.9pF

CF = 2.2pF

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Figure 104. Pulse Response vs. CF





Table 8 shows the noise sources and estimated total output noise for the photodiode amplifier with CF = 2.2 pF and CF =3.9 pF, respectively.

Use the Analog Devices Analog Photodiode Wizard to design a transimpedance amplifier circuit to interface with a photodiode.

Table 8. RMS Noise Contributions of the Photodiode Preamplifier

Noise Contributor Expression RMS Noise (µV)1

CF = 2.2 pF CF = 3.9 pF RF

π

PF fkTR2

4

where: k is Boltzmann’s constant (1.38 × 10−23 J/K). T is the temperature in Kelvin (K).

43.2 32.5

Current Noise, Vni, AMP pFN fRi

2π 0.34 0.25

Voltage Noise, Vnv, AMP

GBPF

INN f

CC

e2

1π

+

61.6 47.7

Total Noise 222,, FRAMPnvAMPnv VVV ++ 75.2 57.7

1 RMS noise with RF = 49.9 kΩ, CIN = CCM + CDM = 19.9 pF, CD = 5 pF, iN = 4.5 fA/√Hz, and eN =3.3 nV/√Hz.

http://www.analog.com/photodiode?doc=ADA4625-1-4625-2.pdf





DAC OUTPUT DRIVER

AD5791B

VR

EF

PF

VR

EF

PS

VR

EF

NF

RFB

INV

VR

EF

NS

1/2AD8676B

1/2AD8676B

AG

ND

DG

ND

VS

S

VOUT

IOV

CC

VC

C

VD

D7

8

11

14

13

12

6

2

1

2034510

15 18 16 19

CLR

LDAC

SDO

SYNC

SCLK

SDIN

RESET

+

+

+

+15V+3.3V

–15V

+

ADA4625-1

1/2AD8676B

1/2AD8676B

+ –

+ –

+

–

A1

C1

B1

B2

PRECISION5V DC

SOURCE

SPI INTERFACEAND DIGITAL

CONTROL

–10V TO +10VOUTPUTVOLTAGE

0.1µF

10µF

10µF 10µF

0.1µF 0.1µF

10µF

1kΩ

R1

1.5kΩ

R3

2kΩR5

R21kΩ

C1

+15V

−15V

+15V

−15V

+15V −15V

+

–

+

–

A2

1kΩR4

9

17

158

93-

121

Figure 105. 20-Bit Accurate, ±10 V Voltage Source (Simplified Schematic: All Connections and Decoupling Not Shown)

ADA4625-1 can be used as an output buffer for 20-bit accurate, ±10 V voltage source with the AD5791 and the LTC6655. The low voltage noise, low drift output drive capability of the ADA4625-1, as well as dynamic parameters such as fast settling time and slew rate make the device an ideal DAC output buffer. It is recommended to provide supplies of ±15 V to obtain the full potential of the ADA4625-1 in this application due to the input VCM range of the device.

2.0

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

0 200000 400000 600000 800000 1000000 1200000

INL

(L

SB

)

DAC CODES

LTC6655 REFERENCEADA4625-1 OUTPUT BUFFERON-BOARD SUPPLIES FROM ADP7118 AND ADP71823458A DMM, NPLC = 10STEP SIZE = 1024TA = 25°C

15

893

-12

2

Figure 106. AD5791 with LTC6655 and ADA4625-1 as Output Buffer INL Performance

Figure 106 and Figure 107 show the INL response with the EVAL-AD5791SDZ and the step response of the ADA4625-1 in comparison to the AD8675, respectively.

VO

LT

AG

E (

200m

V/D

IV)

TIME (500ns/DIV)

ADA4625-1AD8675

TA = 25°CEVAL-AD5791SDZ1V STEP FROM DACOUTPUT READ AT VO_BUF

15

893

-12

3

Figure 107. Step Response with ADA4625-1 and AD8675 Output Buffers


http://www.analog.com/LTC6655?doc=ADA4625-1-4625-2.pdf


http://www.analog.com/LTC6655?doc=ADA4625-1-4625-2.pdf

http://www.analog.com/EVAL-AD5791?doc=ADA4625-1-4625-2.pdf







RECOMMENDED POWER SOLUTION Analog Devices has a wide range of power management products to meet the requirements of most high performance signal chains.

For a dual-supply application, the ADA4625-1 typically needs a ±15 V supply. Low dropout (LDO) linear regulators such as the ADP7118 or the ADP7142 for the positive supply and the ADP7182 for the negative supply help improve the PSRR at high frequency and generate a low noise power rail. In addition, if a negative supply is not available, the ADP5070 can generate the negative supply from a positive supply. Figure 108 shows an example of this power solution configuration for the ADA4625-1.

ADP5070ADP7118

ADP7182+12V

+16V+15V

–15V–16V

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Figure 108. Power Solution Configuration for the ADA4625-1

Table 9. Recommended Power Management Devices Product Description ADP5070 DC-to-dc switching regulator with independent

positive and negative outputs ADP7118 20 V, 200 mA, low noise, CMOS LDO linear regulator ADP7142 40 V, 200 mA, low noise, CMOS LDO linear regulator ADP7182 −28 V, −200 mA, low noise, linear regulator

It is recommended to use a low ESR, 0.1 μF bypass capacitor close to each power supply pins of the ADA4625-1 and ground to reduce errors coupling in from the power supplies. For noisy power supplies, place an additional 10 μF capacitor in parallel with the 0.1 μF for better performance.

INPUT OVERVOLTAGE PROTECTION The ADA4625-1 has internal protective circuitry that allows voltages as high as 0.2 V beyond the supplies to be applied at the input of either terminal without causing damage. For higher input voltages, a series resistor is necessary to limit the input current. Determine the resistor value by

(VIN − VS)/RS ≤ 20 mA

where: VIN is the input voltage. VS is the voltage of either V+ or V−. RS is the series resistor.

With a very low bias current of <5.5 nA up to 125°C, higher resistor values can be used in series with the inputs. A 500 Ω resistor protects the inputs from voltages as high as 10 V beyond the supplies and adds less than 2.75 µV to the offset. However, note that the added series resistor (RS) may increase the overall noise and lower the bandwidth due to the addition of a pole introduced by RS and the input capacitor of the amplifier.

DRIVING CAPACITIVE LOADS The inherent output resistance of the op amp combined with a capacitive load forms an additional pole in the transfer function of the amplifier. Adding capacitance to the output of any op amp

results in additional phase lag. This lag reduces stability and leads to overshoot or oscillation, which is a common situation when an amplifier is used to drive the input of switched capacitor analog-to-digital converters (ADCs).

The ADA4625-1 has a high phase margin and low output impedance and is capable of directly driving a capacitive load up to 1 nF with no external compensation at unity-gain without oscillation.

For other considerations and various circuit solutions, see the Ask the Applications Engineer-25, Op Amps Driving Capacitive Loads Analog Dialogue article.

THERMAL MANAGEMENT The ADA4625-1 can operate with up to a 36 V supply voltage with a typical 4 mA quiescent current. Heavy loads increase power dissipation and raise the chip junction temperature.

The maximum safe power dissipation for the ADA4625-1 is limited by the associated rise in junction temperature (TJ) on the die. Two conditions affect TJ: power dissipation (PD) of the device and ambient temperature (TA) surrounding the package. This relationship is shown in Equation 11.

TJ = PD × θJA + TA (11)

where θJA is the thermal resistance between the die and the ambient environment. The total power dissipation in the amplifier is the sum of the power dissipated in the output stage plus the quiescent power. Power dissipation for the sourcing current is shown in Equation 12, where VSY is the total supply voltage (V+) – (V−).

PD = VSY × ISY + ((V+) − VOUT)IOUT (12)

Replace ((V+) − VOUT) in Equation 12 with ((V−) − VOUT) when sinking current.

For symmetrical supplies with a ground referenced load, use the following equation to calculate the average power for the amplifier processing sine signal.

( )

×

−

×+×+×

=

L

2PEAK

L

PEAK

R2V

RV)(V

π2

SYSY

SINEAVG,

IV

P

(13)

where VPEAK is the peak value of a sine wave output voltage.

The specified thermal resistance θJA of the ADA4625-1/ADA4625-2 is 52.8°C/W. A good PCB layout and an external heat sink can improve thermal performance by reducing junction to ambient temperature.

The ADA4625-1/ADA4625-2 features an exposed pad that floats internally to provide the maximum flexibility and ease of use. Solder the exposed pad to the PCB board GND, or the V+ or V− plane for best thermal transfer. Where thermal heating is not an issue, the exposed pad can be left floating.

Incorporate the use of thermal vias or heat pipes into the design of the mounting pad for the exposed pad to lower the overall θJA.

http://www.analog.com/ADP7118?doc=ADA4625-1-4625-2.pdf








http://www.analog.com/ask-app-engineer-25?doc=ADA4625-1-4625-2.pdf

http://www.analog.com/ask-app-engineer-25?doc=ADA4625-1-4625-2.pdf





TYPICAL APPLICATIONS

R8100MΩ

R71MΩ

1/2ADA4625-2

2

3

8

4

1

+18V

–18V

R33.9kΩ

C11

R11100MΩ

R2200Ω

HYDRO-PHONE

CT

1/2ADA4625-2

6

57

C20.47µF

R6100kΩ

R41MΩ

R51MΩ

OUTPUT

DC OUTPUT ≤ 750µV FOR TA < 125°C.OUTPUT VOLTAGE NOISE = 128nV/√Hz AT 1kHz (GAIN = 20).C1 ≈ CT ≈ 100pF TO 5000pF; R4 × C2 > R8 × CT.

1OPTIONAL

1589

3-12

4

Figure 109. Low Noise Hydrophone Amplifier with DC Servo

1589

3-12

5

1/2ADA4625-2

2

3

8

4

1

+18V

–18V

1/2ADA4625-2

6

57

C22µF

R32kΩ

R420MΩ

R520MΩ

R4 × C2 = R5 × C3 > R1 (1 + R2/R3) C1.OUTPUT = 0.8mV/pC = 80mV/g.DC OUTPUT ≤ 1mV FOR TA < 25°C.OUTPUT NOISE = 6.6nV/√Hz AT 1kHz.

ACELEROMETERB & K MODEL 4381OR EQUIVALENT

C32µF

R1100MΩ

R218kΩ

C11250pF

OUTPUT

Figure 110. Accelerometer Amplifier with DC Servo





1589

3-1

26

3.9MΩ

1/2ADA4625-2

2

3

1

10pF

100pF

4.7kΩ

1.5kΩ

470kΩ

500kΩ

100kΩ

3 1

2

PREAMPOUT

1/2ADA4625-2

6

5

7

10pF

470kΩ

PREAMPLOW

390pF560kΩ

0.022µF

DC SUPPLY

1MΩ

AC SUPPLY

0.47pF

T

R

Figure 111. Guitar Preamplifier

158

93

-12

7

TYPICAL OFFSET ≈ 30µV.1% TOLERANCESVIN = 10V p-p, VOUT = –110dB AT f > 300Hz

VOUT = –6dB AT f = 16HzTHE LOW INPUT BIAS CURRENTS ALLOW THE USE OF HIGH RESISTOR VALUES.

1/2ADA4625-2

2

3

8

4

1

+18V

–18V

1/2ADA4625-2

6

5

7

R2237kΩ

R3249kΩ R4

154kΩR6

249kΩ

R1237kΩ

C133nF

C310nF

C2100nF

C4330nF

VIN

R5154kΩ

VOUT

Figure 112. 10 Hz Fourth-Order Chebyshev Low-Pass Filter (0.01 dB Ripple)





OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-012-AA 06-0

2-2

011

-B

1.270.40

1.751.35

2.29

2.29

0.356

0.457

4.003.903.80

6.206.005.80

5.004.904.80

0.10 MAX0.05 NOM

3.81 REF

0.250.17

8°0°

0.500.25

45°

COPLANARITY0.10

1.04 REF

8

1 4

5

1.27 BSC

SEATINGPLANE

FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

BOTTOM VIEW

TOP VIEW

0.510.31

1.651.25

Figure 113. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] Narrow Body

(RD-8-1) Dimensions shown in millimeters

ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADA4625-1ARDZ −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1 ADA4625-1ARDZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1 ADA4625-1ARDZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1 ADA4625-2ARDZ −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1 ADA4625-2ARDZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1 ADA4625-2ARDZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-1 EVAL-ADA4625-1ARDZ Evaluation Board EVAL-ADA4625-2ARDZ Evaluation Board

1 Z = RoHS Compliant Part.

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