1

S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques

Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100

Q.1(a) Attempt any SIX of the following : [12]Q.1(a) (i) Derive AND gate and OR gate using NAND gates only. [2](A) OR Gate using NAND gates

AND Gate Using NAND gates Q.1(a) (ii) Define Duality theorem and give example. [2](A) Theorem: Starting with a boolean relation, another boolean relation can be

derived by (i) Changing each OR sign to an AND sign (ii) Changing each AND sign to an OR sign (iii) Complementing any 0 or 1 appearing in the expression Example: A.0 = 0

The dual relation is A = 1 = 1 Q.1(a) (iii) List any four Boolean laws. [2](A)

OR Laws

AND Laws

Associative Law

Commutative Law

Distributive Law

A + 0 = A A . 1 = A (A . B) C = A . (B . C) A.B = B.A A.B + A.C = A(B + C) A + 1 = 1 A . 0 = 0 (A + B) + C =

A + (B + C) A + B = B + A (A + B) (A + C)

= A + BC A + A = A A . A = A A + A = 1 A . A = 0

A B A B

Y = A B = A B

A

B

A

B

Y = A B = A + B

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Q.1(a) (iv) Define any two specifications of ADC. [2](A) Analog input voltage This is the maximum allowable input voltage range. Input impedance Its value ranges from 1 K to 1 M depending upon the type of A/D

converter. Input capacitance is in the range of tens of pF. Linearity It is conventionally equal to the deviation of the performance of the

converter from a best straight line. Accuracy The accuracy of the A/D converter depends upon the accuracy of maximum

deviation of the digital output from the ideal linear line. Monotoxicity In response to a continuously increasing input signal the output of an

A/D converter should not at any point decrease or skip one or more codes. This is called the monotoxicity of A/D converter.

Resolution It is define as the maximum number of digital output codes. This is same

as that of a DAC Resolution = 2n

Resolution is defined as the ratio of change in the value of the input analog voltage VA; required to change the digital output by 1 LSB.

Resolution

FSn

v2 1

Conversion Time It is the total time required to convert the analog input signal into a

corresponding digital output. Quantization Error This approximation process is called as quantization and the error due to

the quantization process is called as quantization error. Q.1(a) (v) Draw the symbol and truth lable of AND and OR gate. [2](A)

A B X A B X 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 1

OR

A

B X

A

B X

AND Vidyala

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Q.1(a) (vi) Define with respect to digital ICs(1) Propagation delay (2) Noise immunity

[2]

(A) (1) Propagation delay (or speed of operation) The delay times are measured between the 50 % voltage levels of input

and output waveforms. There are two delay times tPHL when output goes from High to Low tPLH when output goes from Low to High Propagation delay is average of above two delay times. (2) Noise immunity (or Noise margin)

The input & output voltage levels defined above are shown in figure.

Stray electric and magnetic fields may induce unwanted voltages, known as noise, on the connecting wires between logic circuits. This may cause the voltage at the input to a logic circuit to drop below V1H or rise above V1L and may produce undesired operation.

The circuit’s ability to tolerate noise signals is referred to as the noise

immunity, a quantitative measure of which is called noise margin. There are two types of noise margins.

(a) High level noise margin (NMH) NMH = V0H V1H

(b) Low level noise margin (NML) NML = V1L V0L

0V0L

V0H

V1H

V1L

1 state noise margin

0 state noise margin

Voltages

V0H V1H

V1L V0L

Input

Output

50 %

50 %

tPHL tPLH

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Q.1(a) (vii) Which are the universal gates? Why they called it? [2](A) NAND and NOR gates are called as Universal gates. With the help of NAND

and NOR gates only all basic logical operations can be constructed, hence they are called as universal gates.

Q.1(a) (viii) Define any two specifications of DAC. [2](A) (i) Resolution Resolution is defined as the ratio of change in analog output voltage

resulting from a change of 1 LSB at the digital input VFSis defined as the full scale analog output voltage i.e. the analog

output voltage when all the digital input with all digits 1. (ii) Accuracy Accuracy indicates how close the analog output voltage is to its

theoretical value. It indicates the deviation of actual output from the theoretical value. Accuracy depends on the accuracy of the resistors used in the ladder, and the precision of the reference voltage used. Accuracy is always specified in terms of percentage of the full scale output that means maximum output voltage.

(iii) Linearity The relation between the digital input and analog output should be

linear. However practically it is not so due to the error in the values of

resistors used for the resistive networks. (iv) Temperature sensitivity The analog output voltage of D to A converter should not change

due to changes in temperature. But practically the output is a function of temperature. It is so

because the resistance values and OPAMP parameters change with changes in temperature.

(v) Settling time The time required to settle the analog output within the final value,

after the change in digital input is called as settling time. The settling time should be as short as possible. (vi) Long term drift Long term drift are mainly due to resistor and semiconductor aging

and can affect all the characteristics. Characteristics mainly affected are linearity, speed etc.

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(vii) Supply rejection Supply rejection indicates the ability of DAC to maintain scale,

linearity and other important characteristics when the supply voltage is varied.

Supply rejection is usually specified as percentage of full scale change at or near full scale voltage at 25e.

(viii) Speed It is defined as the time needed to perform a conversion from

digital to analog. It is also defined as the number of conversions that can be performed per second.

Q.1(b) Attempt any TWO of the following : [8]Q.1(b) (i) Draw symbol and write truth table of 2 : 1 MUX. Also draw

the block diagram of 8 : 1 mux. [4]

(A) Q.1(b) (ii) Convert the following:

(1) (11001)2 = ( ? )10 (2) (10101)2 = ( ? )8 (3) (37)8 = ( ? )2 (4) (5AC) = ( ? )2

[4]

(A) (1) (11001)2 = ( ? )10

(11001)2 = (25)10

(2) (10101)2 = ( ? )8 The student may convert it to decimal first and then to octal or

directly by forming groups of 3 bits starting from LSB.

2 : 1 MUX

DoutD0

D1

S0

S0 Dout

0 D0

1 D1

8 : 1 MUX

Dout

D0

D7

S0

S1 S2

1 1 0 0 11 × 20 = 1 0 × 21 = 00 × 22 = 01 × 23 = 81 × 24 =16

25Vidyala

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Method 1 (10101)2 = (21)10 = (25)(8)

OR Method 2

2

010 1012 5

= (25)8

(3) (37)8 = ( ? )2

The student may write 3 bit equivalent binary for every octal digit to get the answer or convert the number to decimal first and then to binary.

Method 1 (37)8 = (011 111)2 = (11111)2 Method 2

(4) (5AC) = ( ? )2

The student may convert the hexadecimal number to decimal first and then the obtained decimal to binary or form 4 bit binary groups equivalent of the hexadecimal digits to get the answer in binary directly.

Method 1 Method 2

8 21 5 2

3 7

0 1 1 1 1 1

(3 7)8 = (3 1)10 = (11111)2

7 × 80 = 73 × 81 = 24

31

2 31 12 15 12 7 12 3 1

1

1

2 1452 0 2 726 0 2 363 1 2 181 1 2 90 0 2 45 1 2 22 0 2 11 1 2 5 1 2 2 0

1

5 A C

0101 1010 1100 = (10110101100)2

(5 A C)16 = (1452)10 = (10110101100)2

12 × 160 = 1210 × 161 = 1605 × 162 = 1280

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Q.1(b) (iii) Draw truth table of 3 inputs EX-OR gate. Draw its symbol. Also give its output expression.

[4]

(A) Q.2 Attempt any FOUR of the following : [16]Q.2(a) Draw logical symbol, truth table and logical expression for NAND

and NOR gate. [4]

(A) NAND Gate y = A B … logical expression

A B Y0 0 1 0 1 1 1 0 1 1 1 0

NOR Gate

y = A B … logical expression

A B Y0 0 1 0 1 0 1 0 0 1 1 0

Symbol

Symbol

Output Expression: Q =ABC

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Q.2(b) Perform the following binary operations.(i) 111.01 × 110 (ii) 11001 101

[4]

(A) (i) 111.01 × 110

111.01110

0000011101

11101101011.10

´

´´´

Answer = 101011.1

(ii) 11001 101

101101 11001

10100101101

000

Answer = 101 Q.2(c) For the given K-map in Figure, write minimized SOP expression and

for the same draw NAND-NAND logic circuit. CD CD CD CD

AB 0 1 0 0AB 1 1 1 0AB 1 1 1 0AB 0 0 1 0

[4]

(A)

CD CD CD CD AB 0 1 0 0 AB 1 1 1 0 AB 1 1 1 0 AB 0 0 1 0

BD

ACD

CB

ACD

CD CD CD CD AB 0 1 0 0 AB 1 1 1 0 AB 1 1 1 0 AB 0 0 1 0

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Q.2(d) Simplify the following equation using kmap and realize it using logic

gates. Y=m(0, 1, 2, 3, 8, 10) + d(5, 7).

[4]

(A) Y = (0, 1, 2, 3, 8, 10) + d(5, 7) Y = BD AD

Y BC ACD ACD BD

A B C D

A B C D

B.D

y

AB AB AB AB

CD 0 1 4 0 12 0 8 1

CD 1 1 5 X 13 0 9 0

CD 3 1 7 X 15 0 11 0

CD 2 1 6 0 14 0 10 1

C B A D

A B

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Q.2(e) Draw 16:1 MUX using 4:1 MUX [4](A)

Q.2(f) Perform the following substraction using 2's complement method.

(1) (01000)2 (01001)2 (2) (01100)2 (00011)2 [4]

(A)

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Q.2(g) Design a full adder using half adder. [4](A) Full Adder is a combinational circuit that performs the addition of three

bits (two significant bits and previous carry). It consists of three inputs and two outputs, two inputs are the bits to be added, the third input represents the carry form the previous position

A B Carry Input SUM CARRY OUT 0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

A circuit which obeys this truth table is called a full adder. We can design a full adder by linking together two half adder circuits: Vidy

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Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will half adder will be used to add A and B to produce a partial Sum. The second half adder logic can be used to add CIN to the Sum produced by the first half adder to get the final S output. If any of the half adder logic produces a carry, there will be an output carry. Thus, COUT will be an OR function of the half-adder Carry outputs.

Q.3 Attempt any FOUR of the following : [16]Q.3(a) Convert the expression Y = AB + AC BC into the standard SOP

form. [4]

(A) Y = AB C C AC B B BC A A = ABC ABC ABC ABC ABC ABC = ABC ABC ABC ABC ABC ABC

But A + A = A (ABC + ABC) = ABC and ABC ABC = ABC Y = ABC ABC ABC ABC Standard SOP form

Q.3(b) Draw logic diagram of 1:4 demultiplexers. Write truth table of it. [4](A) Din is connected to Y0 when S1S0 = 00, it is connected to Y1 when S1 S0 = 01

and so on. The other outputs will remain zero.

The enable input needs to be high in order to enable the demux. If E= 0 then all the outputs will be low irrespective of everything.

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Implementation : The 1 : 4 Demux is implemented as shown in figure.

Q.3(c) Reduce the given logic expression using Boolean laws and draw

NAND logic circuit. Y A A B A B

[4]

(A) Y A A B A B A B (A A)

A B A A 1

E Enable

Din

(Input)

Y0 is connected to Din

Y1 is connected to D

Y2 is connected to Din

Y3 is connected to Din

Inputs OutputsE Din S1 S0 Y0 Y1 Y2 Y3

1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 0 0 0 1 1 1 1 0 0 0 1

A B A B

A

B

A

B

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Q.3(d) For the given K-Map in figure, write the POS expression and drawNOR-NOR logic circuit for same.

[4]

(A)

POS Expression y (A C D) (A B D) (A C)

Q.3(e) Minimize the following equation using kmap.

(i) Y = m(0, 1, 2, 4, 5, 6) (ii) Y = m(0, 2, 4, 5).

[4]

(A) (i) Y = m(0, 1, 2, 4, 5, 6)

Y = m (0, 1, 2, 4, 5, 6)

A B C D A B C D

A C D A B D

A C

(A + C + D) (A B C) A C

00 01 11 10

CD CD CD CD

00 AB 0 1 1 1

01 AB 0 0 0 1

11 AB 1 1 0 0

10 AB 1 1 0 0

ABCD

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Y = B C (ii) Y = m (0, 2, 4, 5)

Y = m (0, 2, 4, 5)

Y = (A + C) A B Q.3(f) Explain working of PIPO with neat logic diagram and timing diagram. [4](A)

Working In Parallel out Shift register, the data bits are entered simultaneously into their respective stages on parallel lines. The output data bits are also available on parallel lines. Immediately following the simultaneous entry of all data bits, the bits appear in the parallel outputs.

B C B C BC B C

A 1 1 0 1

A 1 1 0 1

BC A

BC .

B C B C BC B C

A 0 1 1 0

A 0 0 1 1

BCA

A B

(A + C)

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Truth Table

Inputs Outputs ABCD QA QB QC QD 1111 1 1 1 1

Timing diagram Input D C B A = 1111

Q.3(g) Obtain an 1 : 8 demultiplexer using 1 : 4 demultiplexer. [4](A)

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Q.3(h) Explain the functions of 'preset' and 'clear' inputs in flip-flops. [4](A) The normal data inputs to a flip flop (D, S and R, or J and K) are referred to

as synchronous inputs because they have effect on the outputs (Q and not Q) only in step, or in sync, with the clock signal transitions. These extra inputs are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock signal. Typically, they are called preset and clear:

When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock. So, what happens if both preset and clear inputs are activated? we get an invalid state on the output.

Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active low.

If they’re active-low, there will be an inverting bubble at that input lead on the block symbol, just like the negative edge-trigger clock inputs.

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Sometimes the designations “PRE” and “CLR” will be shown with inversion bars above them, to further denote the negative logic of these inputs:

Inputs OUTPUT Operation performed

CLK PR CLR1 1 1 Qn+1 Normal JKFF X 0 1 1 FF is set X 1 0 0 FF is reset

Q.4 Attempt any FOUR of the following : [16]Q.4(a) Classify the memories and explain ROM. [4](A) [Correct classification of memories in other form may also be considered]

Read only Memory (ROM) ROM is used to store information permanently. The data stored in ROM can be read or recalled for use in digital devices. ROM is nonvolatile memory i.e. the information once stored remains intact.

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Q.4(b) State any four specifications of A to D converter. [4](A) Analog input voltage: This is the maximum allowable input voltage range,

010 V, ± 5 V,± 10 V, and so on.

Input Impedance: Its value ranges from 1 k to 1 M depending upon the type of A/D converter. Input capacitance is in the range of tens of pF.

Stability : The temperature dependence. Even if analog input is kept constant, the digital output may change with temperature. This is called stability. It is expressed as % error per degree rise in temperature.

Resolution : Is define as the maximum number of digital output code. This is same as that of a DAC.

Resolution = 2” Resolution is defined as the ratio of change in the value of the input

analog voltage VA, required to change the digital output by 1 LSB.

Resolution = FSnV

2 1

Conversion Time It is the total time required to convert the analog input signal into a

corresponding digital output.

As we know the conversion time depends on the conversion technique used for an ADC. The conversion time is also dependent on the propagation delays introduced by the circuit components.

Conversion time should ideally be zero and practically be as small as possible.

Quantization Error As shown in the figure the digital output is not always the accurate

representation of the analog input. For example any input voltage between 1/8 to 2/8 of full scale will be converted to a digital word of “001”.

This approximation process is called as quantization and the error due to the quantization process is called as quantization error.

The maximum value of quantization error is 1 LBS2

.

The quantization error should be as small as possible. It can be reduce by increasing the number of bits. The increase in number of bits will also improve the resolution.

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Q.4(c) Construct D-flip flop using R-S flip flop and explain it’s working

along with truth table. [4]

(A)

Working : The SR flip flop can be converted into D flip flop by simply the addition of an inverter. This flip flop has only one input that is D input. The output Q will go to the same state that is present on the D input when negative edge of clock occurs. The output Qn+1 at the end of the clock pulse equal the input Dn. hence we can say that the input data appears at the output at the end of the clock pulse. Thus the transfer of data from input to the output delayed and hence the name delay (D) flip flop.

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Truth Table for a Dtype Flipflop Input Dn Output Qn+1

0 0 1 1

Q.4(d) Describe working of RS ff using NAND gates only. [4](A) The clocked SR flip flop is an edge triggered SR flip flop. It can be of two types.

(i) Positive edge triggered (ii) Negative edge triggered.

Positive edge triggered SR Flip Flop:

Basic SR Latch

Clocked SR Flipflop (Positive edge triggered) The positive edge triggered S-R flip Flop. It is also called as clocked SR FF. This circuit will operate as an SR flip flop only for the positive clock edge but there is no change in output id clock=0 or even for the negative going clock edge.

Operation : Case I: S = X, R = X, clock = 0 Since clock = 0, the outputs of NAND gates 3 and 4 will be forced to be

1 irrespective of the values of S and R. that means R'= S'= 1 these are the inputs of the latch.

Hence the outputs of basic SR F/F i.e. Q and Q will not change in the output of the clocked SR flip flop

Case II: S = X, R = X, clock = 1 (high level) As this flip flop does respond not respond to levels applied at the clock

input, the outputs Q and Q will not change. So Qn+1 = Qn and n 1 nQ Q

Case III: S = R = 0 : No Change If S = R = 0 then outputs of NAND gates 3 and 4 are force to become 1. Hence R' and S' both will be equal to 1. Since S' and R' are the inputs of

the basic S-R flip flop using NAND gates, there will be no change in the state of outputs.

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Case IV: S = 0 R = 1, clock ↑ Now S = 0, R = 1 and a positive edge is applied to the clock input. Since S = 0, output of NAND-3 i.e. R =1. And as R = 1 and clock =1 the

output of NAND-4 i.e. S = 0. Hence n 1Q = 0 and n 1Q = 1. This is the reset condition.

Case V: S = 1 R = 0, clock = ↑ Now S = 1, R = 0 and a positive going edge is applied to the clock input. Output of NAND 3 i.e. R' = 0 and output of NAND 4 i.e. S' = 1 Hence output of SR flip flop is Qn+1 = 1 and n 1Q = 0 This is the reset condition. Case VI: S = 1 R = 1, clock = ↑ As S = 1, R = 1 and clock = 1, the outputs of NAND gates 3 and 4 both

are 0. i.e. S'= R' = 0. Hence the "Race" condition will occur in the basic SR flip-flop. The symbol of positive edge triggered SR flip flop is as shown in figure

and the truth table.

Inputs OutputsRemark

CLK S R Qn + 1 n 1Q

0 X X Qn n 1Q No change (NC)

1 X X Qn nQ No change (NC)

X X Qn nQ No change (NC)

0 0 Qn nQ No change (NC) 0 1 0 1 Reset 1 0 1 0 Set 1 1 Race Race Avoid

= Negative edge of clock, = Positive edge of clock

Note that for clock input to be at negative or positive levels as the edge

triggered flip flop does not respond. Similarly it does not respond to negative edge of the clock.

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The flip flop will respond only to the positive edge of clock. With positive edge of the clock, the SR flip flop behaves in the following way: S = R = 0 No change in output S = 0, R = 1 Qn+1 = 0, n 1Q 1 Reset condition

S = 1, R = 0 Qn+1 = 1, n 1Q 0 Set condition S = R = 1 Race condition. Negative Edge Triggered S-R Flip Flop: The internal circuit (with NAND gates) of the negative edge triggered

S-R flip flop is exactly same as that for the positive edge triggered one.

The differentiator circuit is slightly modified in order to enable the flip flop for the negative (falling) edges of the clock input.

The circuit symbol of the negative edge triggered S-R flip flop and its truth table.

QS

R Q

CLK

(C590) Fig. : Circuit symbol of negative edge triggered SR FF

= Positive edge of clock = Negative edge

of clock Vidyala

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Q.4(e) Draw and explain D flip-flop using SR flip-flop. Also draw truth table.

[4]

(A)

Due to Inverter S and R will always be the complements of each other hence S=R=0 or S=R=1 conditions never appear.

D S R Qn+1 Qn+1 0 0 1 0 1 1 1 0 1 0

Q.4(f) Draw neat circuit diagram of clocked JK flip-flop using NAND

gates. Give its truth table and explain race around condition. [4]

(A)

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Race around condition: When JK flip flop when the value of J and K =1 and at the same time value of clock is 1, so according to the truth table of J=k=1 the value of output should be toggled so the value keep on changing till the change in the clock pulse which is not acceptable . Elimination of Race around Condition: Race around condition can be avoided using Master Slave Flip flop & by using Edge Triggered Flip Flop.

Q.5 Attempt any FOUR of the following : [16]Q.5(a) Draw the logic diagram of D type flip flop using NAND gates.

Write its truth table. [4]

(A)

Truth table Input (Dn) Output Q

0 1 1 0

Q.5(b) Draw Master- slave J-K flip-flop and explain its working. [4](A)

Master Slave JK FF

D (Input)

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Truth Table :

Case I: Clock = x, J=K=0 For clock=1 the master is active, slave in active. As J=K=0.Therefore Output of master i.e. Q1 and will not change. Hence the S and R inputs to the slave will remain unchanged.

As soon as clock = 0, the slave becomes active and master is inactive. But since the S and R inputs have not change the slave outputs will also remain unchanged. Therefore the output will not change if J=K=0

Case II: clock = , J = K = 0 This condition has been already discussed in case I. Case III: Clock= , J = 0 and K = 1

Clock = 1: Master active, slave inactive. Output of the master become Q1 = 0 and 1Q = 1.That means S=0 and R = 1

Clock = 0 slave active master inactive Outputs of the slave become Q = 0 and 1Q =1 Again if clock=1: master active, slave inactive. Even with the change output Q=0 and 1Q = 1 fed back to master, its

outputs will Q1 = 0 and 1Q = 1 that means S = 0 and R = 1. Hence with clock = 0 and slave becoming active, the outputs of slave will

remain Q = 0 and Q 1 . Thus we get a stable output from the Master Slave.

Case IV: CLK= , J=1, K=0

Clock =1 master active, slave inactive Outputs of master become Q1 = 1 and 1Q = 0 i.e. S=1,

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R = 0 Clock = 0: master inactive slave active. Outputs of slave become Q = 1 and 1Q = 0. Again if clock=1 then it can be shown that the outputs of the slave are

stabilized to Q = 1 and 1Q 0 .

Case V : CLK : = , J = 1, K = 1 Clock =1: master will be active, slave inactive. Outputs of master will toggle so S and R also will be inverted. Clock=0:

master inactive, slave active Outputs of the slave will toggle. These changed outputs are returned back to the master inputs. But since clock = 0, the master is still inactive. So it does not respond to

these changed outputs. This avoids the multiple toggling which leads to the race around condition. Thus the master slave flip flop will avoid the race around condition.

Q.5(c) Define ‘Modulus of counter’. Determine number of flip flops to be

used in MOD-21 counter. [4]

(A) Modulus of a counter is the no. of different states through which the counter progress during its operation. It indicates the no. of states in the counter, pulses to be counted are applied to counter. The circuit comes back to its starting state after counting N pluses in the case of modulus N counter.

In general, m number of flip-flops are required to construct MOD-n counter, where n <=2m

MOD n Counter = 2m where m is no. of flip flops and n is the no. of counters.

MOD 21 = 2m Hence m = 5 (5 flip flops are required for MOD 21)

MOD n counter Number of flipflops(m)21 5

Q.5(d) Compare combinational logic circuit and sequential logic circuit. (any

4 points) [4]

(A) Combinational logic Sequential logic

(i) The combinational logic circuit consists of logic gate only.

Sequential logic circuit consists of combinational logic circuit along with memory for storage of information.

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(ii) It operation depend upon present input and does not required history of inputs.

It operation depend upon present input as well as last state of input and output which are stored in memory.

(iii) Easy to design due to lack of memory.

Difficult to design due to presence of memory.

(iv) Faster in speed as all inputs are primary inputs are applies simultaneously.

Slower in speed because of secondary Inputs.

(v) Examples Encoders, decoders, multiplexer, demultiplexer etc.

Examples counters, shift registers flip-flop etc.

Q.5(e) Describe block diagram of digital comparator and write truth table

of 2 bit comparator. [4]

(A) Digital comparator is a combinational circuit which compares two numbers, A and B; and evaluates their relative magnitudes.

The outcome of the comparison is given by three binary variables which indicate whether.

A = B or A > B or A < B. Depending on the result of comparison one of these outputs will go high.

Inputs OutputsA1 A0 B1 B0 A > B A = B A < B 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0

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0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 0 1 0 1 0

Q.5(f) List different types of flip-flop. Draw the diagram of master

Slave JK flip-flop. [4]

(A) Types of Flip-Flops RS flip-flop JK flip-flop D flip-flop T flip-flop

Circuit Diagram Fig: Master Slave JK

Q.5(g) Draw the diagram of serial in parallel out (SIPO) shift register.Also draw timing diagram.

[4]

(A) A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. It is different in that it makes all the internal stages available as outputs. Therefore, a serial-in/parallel-out shift register converts data from serial format to parallel format. If four data bits are shifted in by four clock pulses via a single wire at data-in, below, the data becomes available simultaneously on the four outputs QA to QD after the fourth clock pulse.

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Figure: Serial in parallel

Q.5(h) State different applications of flip flops. [4](A) Applications of flip flop Bounce elimination of key Memory Registers Counters Delay element Q.5(i) Draw and explain SISO with truth table and timing diagram. [4](A) Serial in Serial out Shift Register (SISO), type of shift register accepts

data serially, one bit at a time at the single input line, and shifted to next flip flop serially. The output is also obtained on a single output line in a same serial fashion. A shift right register can be constructed with either J-K or D flip flops as shown in below.

Figure: Timing Diagram

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Shift-right register using J-K flip-flops

As shown in figure J-K flip flop based shift register requires connection of both J and K inputs. Input data are connected to the J and K inputs of the left most (lowest order) flip flop of flip flop chain. And all flip flops are connected in serially. For a JK flip flop output is followed whatever the input of J and the both the input are complimentary. Let take an example to input a 0, one should apply a 0 at the J input, i.e., J = 0 and K = 1 and vice versa. With the application of a clock pulse the data will be shifted by one bit to the right. In this way the first data will store at Flip flop A then in next clock pulse the date of A flip flop is shifted to filp flop B in that way. Finally the serial output will appear from flip flop D. For example, consider that all the stages are reset and a logical input 1011 is applied at the serial input line connected to stage A. the table given below shows how the data is shifted from one flip flop to other and finally get the output from D flip flop. After fourth clock pulse we will get first input after next three clock pulse the complete input (1011) which we feed at flip flop A will out from flip flop D. Now in bellow see the waveform of 4 bit serial shift register.

After fourth clock pulse we will get first input after next three clock pulse the complete input (1011) which we feed at flip flop A will out from flip flop D. Now in bellow see the waveform of 4 bit serial shift register.

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Q.6 Attempt any TWO of the following : [16]Q.6(a) (i) Draw the circuit diagram of successive approximation type A to

D converter and describe its working. (ii) A D to A converter has a full scale analog output of 12V with

4 bit binary inputs. Find the voltage corresponding to eachanalog step.

[8]

(A) (i) Block Diagram

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Working The comparator serves the function of the scale, the output of which is

used for setting/ resetting the bits at the output of the programmer. This output is converted into equivalent analog voltage from which offset is subtracted and then applied to the inverting input terminal of the comparator. The outputs of the programmer will change only when the clock pulse is present.

To start the conversion, the programmer sets the MSB to 1 and all other

bits to 0. This is converted into analog voltage by the DAC and the comparator compares it with the analog input voltage. If the analog input voltage Va >= Vi, the output voltage of the comparator is HIGH, which sets the next bit also. On the other hand if Va <= Vi. Then the output of the comparator is LOW which resets the MSB and sets the next bit. Thus a 1 is tried in each bit of DAC until the binary equivalent of analog input voltage is obtained.

(ii) Formula

Vo = n

Full scale analog output2 -1

= 412

2 1 = 12

15 = 0.8

Inputs OutputD C B A VO in Volts0 0 0 0 0 0 0 0 1 0.8 0 0 1 0 1.6 0 0 1 1 2.4 0 1 0 0 3.2 0 1 0 1 4 0 1 1 0 4.8 0 1 1 1 5.6 1 0 0 0 6.4 1 0 0 1 7.2 1 0 1 0 8 1 0 1 1 8.8 1 1 0 0 9.6 1 1 0 1 10.4 1 1 1 0 11.2 1 1 1 1 12

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Q.6(b) (i) List four applications of flip flops. (ii) Compare synchronous and asynchronous counter on any two points. (iii) Convert JK- flip flop in to T-flip flop. Write its truth table

and explain.

[8]

(A) (i) Applications of flip flops (1) Elimination of keyboard debounce. (2) As a memory elements. (3) In various types of registers. (4) In counters/timers. (5) As a delay elements

(ii) Asynchronous Counter Synchronous Counter

1) In an Asynchronous Counter the output of one Flip Flop acts as the clock Input of the next Flip Flop.

In a Synchronous Counter all the Flip Flop’s are Connected to a common clock signal.

2) Speed is Low. Speed is High. 3) Only J K or T Flip Flop can be used

to construct Asynchronous Counter.

Synchronous Counter can be designed using JK, RS, T and D FlipFlop.

4) Problem of Glitch arises Problem of Lockout 5) Only serial count either up or

down is possible. Random and serial counting is possible.

6) Settling time is more Settling time is less 7) Also called as serial counter Also called as Parallel Counter 8)

(iii) Truth Table for Conversion :

Inputs Outputs

T Present state of Q Next state of Q J K

0 0 0 0 X 1 0 1 1 X 1 1 0 X 1 0 1 1 X 0

Excitation table of T FF Excitation table of JK FF

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K map and simplification :

For J output For K output

(a) K map for J output (b) K map for K outputs Logic Diagram : Q.6(c) (i) Convert the following SOP equation into standard SOP

equation. Y =AB AB AB C

[8]

(A) Y = AB AB ABC Y = AB(C C) AB(C C) ABC Y = ABC ABC ABC ABC ABC Q.6(c) (ii) List any four applications of multiplexer and implement the

following logic expression using 16:1 MUX. Y = m(0, 3, 5, 6, 7, 10, 13).

[8]

(A) Applications: 1) Digital computer 2) Microprocessor 3) Data converters 4) Digital systems

Qn

T 0 1

0 0 X

1 1 X

J = T

Qn

T 0 1

0 X 0

1 X 1

K = T

T (input)

Outputs

CLK

Conversion logic

GivenJK F/F

J

K

Q

Q

T Flipflop

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Expression using 16:1 MUX Y = m(0, 3, 5, 6, 7, 10, 13)

Q.6(d) Draw block diagram and truth table of 1:4 demultiplexer. [8](A) 1-to-4 Demultiplexer has a single input (D), two selection lines (S1 and S0)

and four outputs (Y0 to Y3). The input data goes to any one of the four outputs at a given time for a particular combination of select lines. The block diagram of 1:4 DEMUX is shown below.

0

1

23456789

y

+VCC

10

11

1213

14 15

S3 S2 S1 S0

16 : 1 MUX

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The truth table of this type of demultiplexer is given below. From the truth table it is clear that, when S1=0 and S0= 0, the data input is connected to output Y0 and when S1= 0 and s0=1, then the data input is connected to output Y1.

Similarly, other outputs are connected to the input for other two combinations of select lines.

Q.6(e) (i) With suitable diagram describe successive approximation ADC. [4]

(A) Successive approximation register

The comparator serves the function of the scale, the output of which is used for setting /resetting the bits at the output of the programmer. This output is converted into equivalent analog voltage from which offset is subtracted and then applied to the inverting input terminal of the

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comparator. The outputs of the programmer will change only when the clock pulse is present. To start the conversion, the programmer sets the MSB to 1 and all other bits to O. This is converted into analog voltage by the DAC and the comparator compares it with the analog input voltage. If the analog input voltage Va>= Vi, the output voltage of the comparator is HIGH, which sets the next bit also. On the other hand if Va<=Vi, Then the output of the comparator is LOW which resets the MSB and sets the next bit. Thus a 1 is tried in each bit of DAC until the binary equivalent of analog input voltage is obtained.

Q.6(e) (ii) List any four specifications of ADC. [4](A) Analog input voltage Input impedance Linearity Accuracy: Monotoxicity Resolution Conversion Time Quantization Error OR

Analog input voltage: This is the maximum allowable input voltage range Input impedance: Its value ranges from 1 kΩ to 1 MΩ depending upon the type of A/D converter. Input capacitance is in the range of tens of pF. Linearity: is conventionally equal to the deviation of the performance of the converter from a best straight line. Accuracy: the accuracy of the A/D converter depends upon the accuracy of maximum deviation of the digital output from the ideal linear line. Monotoxicity: In response to a continuously increasing input signal the output of an A/D converter should not at any point decrease or skip one or more codes. This is called the monotoxicity of A/D converter. Resolution is define as the maximum number of digital output codes. This is same as that of a DAC Resolution= 2n Resolution is defined as the ratio of change in the value of the input analog voltage VA, required to change the digital output by 1 LSB.

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Conversion Time: It is the total time required to convert the analog input signal into a corresponding digital output. Quantization Error: This approximation process is called as quantization and the error due to the quantization process is called as quantization error.

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