3 AVR Interrupts

Atmega16 Interrupts

AVR Lecture 3

Interrupts

Atmega16 has 3 external interrupts and 17 internal interrupts

These interrupts and the separate reset vector each have a separate program vector in the program memory space

All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors

The complete list of vectors is shown in a table on next slide

More Details on Page 11 and Page 42 of Datasheet

Interrupt

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled

The I-bit is automatically set when a Return from Interrupt instruction is executed

The interrupts have priority in accordance with their interrupt vector position

The lower the interrupt vector address, the higher the priority

What does it mean? Like 8051 you cannot set the interrupt priority in

Atmega16 the only solution is nested interrupt (interrupt with in an interrupt)


Nested Interrupts

The user software can write logic one to the I-bit to enable nested interrupts

All enabled interrupts can then interrupt the current interrupt routine


External Interrupts

External Interrupt The External Interrupts are triggered by the INT0, INT1,

and INT2 pins

Internal Through External Interrupt If enabled, the interrupts will trigger even if the INT0..2

pins are configured as outputs This provides a way of software interrupt

INT0 and INT1 The external interrupts can be triggered by a falling or

rising edge or a low level

INT2 It is only edge triggered

More Details on Page 64 of Datasheet

Registers Associated with InterruptsFollowing are the registers which contains different bits that

control the interrupts Status Register (SREG)

Bit-I (7) of SREG is Global Interrupt Enable bit This bit must be set for the interrupts to be enabled


General Interrupt Control Register – GICR

Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) the external pin interrupt

1 is enabled The corresponding interrupt of External Interrupt

Request 1 is executed from the INT1 interrupt Vector

Registers Associated with Interrupts


Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) the external pin interrupt 0 is

enabled The corresponding interrupt of External Interrupt Request 0 is

executed from the INT0 interrupt Vector

Bit 5 – INT2: External Interrupt Request 2 Enable When the INT2 bit is set (one) the external pin interrupt 2 is

enabled The corresponding interrupt of External Interrupt Request 2 is

executed from the INT2 interrupt Vector

External Interrupts Resgisters

MCU Control Register (MCUCR)Last four bits of this register controls the mode of external interrupt 0

and 1

Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 (Interrupt 1 Sense control)



Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 (Interrupt 0 sense control)


MCU Control and Status Register – MCUCSR Bit-6 of this register controls the mode of interrupt 2

If ISC2 is written to zero, a falling edge on INT2 activates the interrupt

If ISC2 is written to one, a rising edge on INT2 activates the interrupt


For Interrupt 0 Set the SREG bit-I Set the INT0 pin of GICR Select its mode by setting bits ICS01 and ICS00

of MCUCR accordingly For Interrupt 1

Set the SREG bit-I Set the INT1 pin of GICR Select its mode by setting bits ICS11 and ICS10

of MCUCR accordingly


For Interrupt 0 Set the SREG bit-I Set the INT2 pin of GICR Select its mode by setting bit ISC2 of MCUCSR

accordingly


General Interrupt Flag Register – GIFR

Bit 7 – INTF1: External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an

interrupt request, INTF1 becomes set (one) The flag is cleared when the interrupt routine is executed If the I-bit in SREG and the INT1 bit in GICR are set (one), the

MCU will jump to the corresponding Interrupt Vector Alternatively, the flag can be cleared by writing a logical one to

it This flag is always cleared when INT1 is configured as a level

interrupt

External Interrupts Flags Register




it This flag is always cleared when INT0 is configured as a level

interrupt





it


Example#include <avr/io.h>

#include <avr/interrupt.h>

unsigned char z=0;

void main()

{

DDRB=0xFF; //Configures port B as output

DDRD|=0b00001000; //configure bit4 of port D as intput

SREG=SREG|0b10000000; //Enabling Global Interrupt

GICR=0b10000000; //Enabling Interrupt 1

MCUCR=(1<<ISC10|0<<ISC11); //selecting mode of interrupt 1

while(1)

{

PORTB=z; //continuously outputs z

}

}

ISR(INT1_vect)

{

z++;

}

Vector Names for WinAVR(AVR GCC)External interrupt 0 INT0_vect

External interrupt 1 INT1_vect

External interrupt 2 INT2_vect

ADC Conversion Complete ADC_vect

Analog Comparator ANA_COMP_vect

Serial Transfer Complete SPI_STC_vect

Store Program Memory Ready SPM_RDY_vect

Timer/Counter0 Compare Match TIMER0_COMP_vect

Timer/Counter0 Overflow TIMER0_OVF_vect

Timer/Counter Capture Event TIMER1_CAPT_vect

Timer/Counter1 Compare Match A TIMER1_COMPA_vect

Timer/Counter1 Compare MatchB TIMER1_COMPB_vect

Timer/Counter1 Overflow TIMER1_OVF_vect

Complete table available at : http://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html

http://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html

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3 AVR Interrupts