2746 IEEE JOURNAL OF SOLID-STATE CIRCUITS, …cc.ee.ntu.edu.tw/~jrilee/publications/77G_RADAR_J.pdf · 2746 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010 AFully-Integrated77-GHzFMCWRadarTransceiver

2746 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010

A Fully-Integrated 77-GHz FMCW Radar Transceiverin 65-nm CMOS Technology

Jri Lee, Member, IEEE, Yi-An Li, Meng-Hsiung Hung, and Shih-Jou Huang

Abstract—A fully-integrated FMCW radar system for automo-tive applications operating at 77 GHz has been proposed. Utilizinga fractional- synthesizer as the FMCW generator, the trans-mitter linearly modulates the carrier frequency across a rangeof 700 MHz. The receiver together with an external basebandprocessor detects the distance and relative speed by conductingan FFT-based algorithm. Millimeter-wave PA and LNA areincorporated on chip, providing sufficient gain, bandwidth, andsensitivity. Fabricated in 65-nm CMOS technology, this prototypeprovides a maximum detectable distance of 106 meters for amid-size car while consuming 243 mW from a 1.2-V supply.

Index Terms—77 GHz, fast Fourier transform (FFT), frac-tional- synthesizer, frequency modulated continuous-wave(FMCW) radar, low-noise amplifier (LNA), power amplifier (PA).

I. INTRODUCTION

T HE emerging automotive radar systems have been devel-oped over the past years to create a more secure and more

comfortable driving environment. Up to now, quite a few stan-dards have been established for different applications (Fig. 1).For example, short-range ( m) radars are adopted to pro-vide parking assistance or to prevent side-crash, which utilizespulse-based modulation with a wide bandwidth of 7 GHz. Be-cause of the short distance, it must provide a wide azimuthangle and a fine resolution ( cm) [1]. Used in theStop-and-Go system,1 the mid-range radars usually operate at24-GHz band to cover a distance of 10–40 m with an angle of30 –60 [2], [3]. The 77-GHz band, on the other hand, has beendedicated to long-range radars, e.g., the adaptive cruise control(ACC) system, which basically detects the distance and the rela-tive speed of the vehicles in front so as to perform a real-time re-sponse by means of the braking system or other protective mech-anism. It must cover a range up to 100–150 meters [4]. At thespeed of 110 km/h, saving one second response time is equiva-lent to extending over 30 meters for braking. With proper oper-ation, such an anti-collision system can reduce a great amountof casualties in traffic accident.

The 77-GHz radar presents significant advantages overmicrowave (e.g., 24-GHz) radars. The more compact size

Manuscript received April 06, 2010; revised June 29, 2010; accepted August12, 2010. Date of publication October 28, 2010; date of current version De-cember 03, 2010. This paper was approved by Guest Editor Ranjit Gharpurey.

The authors are with the Electrical Engineering Department, National TaiwanUniversity, Taipei, Taiwan (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JSSC.2010.2075250

1A cruise control system that could maintain a safe driving distance from thevehicle ahead while in heavy traffic.

(especially in antenna design) makes it suitable for furtherintegration. The associated narrow-beamwidth requirementfits in with long-distance applications. For example, high-gainnarrow-beamwidth antennas such as horn or dish can be used.Also, as compared with the laser radar, which is subject todisturbance by rain or mist, millimeter wave reveals betterenvironmental resistance. However, even with modern tech-nology, 77-GHz radar systems are still very expensive and canonly be applied to luxury cars. It is because in conventionalapproaches, engineers need to collect individual mm-wavecircuits and put them together as a module, rather than real-izing a fully-integrated circuit in one chip. It inevitably suffersfrom high cost and low yield. Today, the trend to popularizethis high-end technique puts more pressure on cost reduction.Research on 77-GHz automotive radars has been extensivelyconducted over the past years. For example, [5] and [6] pro-vide single-chip transceivers and transceiver arrays in SiGeBiCMOS technology, respectively, and 77-GHz transceivers arealso demonstrated in CMOS [7], [8]. Even so, highly-integrated77-GHz radar transceivers have never been realized in CMOSbefore. Unlike compound technologies, CMOS manifests itselfin its low cost, high yield, and potential of highly integration,and it is of course desirable to implement long range radartransceivers in CMOS. In this paper, we propose a solutionthat integrates the whole transceiver in single chip, whichalong with antennas and baseband processor forms a completesystem. It substantially reduces the cost and increases thereliability. Note that [9] only accomplishes the transmit part

. Whole-systemassembly requires much more effort than building up blocks.

Before looking at design details, we need to evaluate the chal-lenges of realizing such a high-frequency system. It is well-known that the returned power loss of a radar system is givenby

(1)

where denote the transmitted and received power,the gain of antennas, the radar cross section, the wave-

length, and the distance [10]. At 77 GHz, the reflected wavewould be attenuated by approximately 150 dB at a distance of100 meters. Here, the radar cross section is defined as

(2)

where denotes the incident power density measured at thetarget, and the scattered power density seen at a distance

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LEE et al.: A FULLY-INTEGRATED 77-GHz FMCW RADAR TRANSCEIVER IN 65-nm CMOS TECHNOLOGY 2747

Fig. 1. Classification of automotive radar systems.

away from the target. For a mid-size automotive,m [11]. In the receive side, the lowest detectable power level

can be expressed as [10]

(3)

where denotes the overall receiver noise figure andthe fast Fourier transform (FFT) resolution band-

width. Here we assume the intermediate frequency (IF) of theFMCW radar is calculated by doing FFT. In radar systems, adetectable signal needs to present a signal-to-noise ratio (SNR)higher than 16 dB [10]. Considering 1-kHz FFT bandwidth,and approximately 28-dB total noise figure ( , obtainedfrom simulation), we can calculate the minimum detectablepower level as around dBm. Compared with standard2.4-GHz transceivers (e.g., Bluetooth [12], which have RFinput sensitivity of dBm), the receiver here must deal witheven weaker signals. Meanwhile, to reach a longer distance, itis desirable to suppress as much as possible, which inturn requires a high-gain low-noise amplifier (LNA).

To estimate the minimum required output power in thetransmit side , we have

(4)

where represents the receiver (Rx) sensitivity, theantenna gain. Suppose each antenna contributes 20-dBi gain, weobtain that the power amplifier (PA) in the transmitter (Tx) mustdeliver at least 10 dBm of power for a 100-m ranging distance. Inother words, high output power PA and high-gain antennas areessential. The 20-dBi antenna gain can be achieved by some spe-cific structures. So far, horn and dish antennas still prove to bethe most suitable structures because they concentrate radiationenergy efficiently. As will be discussed in Section VI, planar an-tennas such as patch arrays may achieve similar performance aswell. The interconnection between chip and antenna is anotherissue, since the signal at 77 GHz can get attenuated significantlyby travelling through only a small piece of wire. In our proto-type, the lengths of the bonding wires are minimized to about250–300 m.

In advanced CMOS technologies, the millimeter-wave (mm-wave) PA and LNA designs become applicable. However, the

Fig. 2. Performance analysis of CMOS mm-wave circuits: (a) � of PAs, (b)power gain and (c) noise figure of LNAs.

design margins are still quite small. To be more specific, wecan analyze the performance of state-of-the-art PAs and LNAs,and predict their output saturation power ( , for PAs) andpower gain (for LNAs) at 77 GHz by regression. As illustratedin Fig. 2(a) and (b), they are approximately 7.5 dBm and 11 dB.For the radar to function properly, we need a PA with of atleast 10 dBm and an LNA with -dB gain and -dB NF.Thus, it is necessary to adopt modern mm-wave circuit designsso as to achieve the required performance. Block optimizationand integration technique are equally important. Similarly, thenoise figure of LNAs must be kept below 10 dB as the intersec-tion point is about 7.5 dB [Fig. 2(c)]. Note that the down-conver-sion mixer and IF amplifier contribute significant noise figure aswell.

In architecture level, conventional structures tend to use aninteger- phase-locked loop (PLL) with a programmable di-rect digital frequency synthesizer (DDFS) as the reference input[27]. The frequency modulation is accomplished by changingthe input reference . This approach, however, suffers fromsevere power and area penalties, primarily because the DDFSmay need high-resolution digital-to-analog converters (DACs)and large read-only memory (ROM) tables to achieve fine fre-quency tuning. The linearity of modulated frequency is deter-mined by that of the DDFS, which may undergo inaccuracyof frequency chirping. In our design, we remove the DDFSentirely and incorporate a fractional- PLL instead. The fre-quency modulation is therefore achieved by changing the di-vide modulus. We integrate the FMCW generator and the radiofrequency (RF) front-end in one chip, and have it co-designedwith the interconnection to antennas. Together with signal pro-cessor realized in a field programmable gate array (FPGA), theFMCW radar system is capable of detecting multiple objectsand exhibiting their positions and speeds in real time.

This paper is organized as follows. Section II briefly describesthe FMCW radar theory. Section III presents the transceiverarchitecture, revealing system level considerations. Section IV


Fig. 3. FMCW radar operation for (a) general case, (b) longest distance, (c) highest speed.

Fig. 4. (a) FMCW radar system architecture, (b) triangular frequency modula-tion, (c) loop bandwidth selection.

discusses building block designs, and a complete testing result issummarized in Section V. Consideration for future work is dis-cussed in Section VI. Finally, Section VII concludes this work.

II. FMCW RADAR

An FMCW radar transmits a continuous wave, which is trian-gularly modulated in frequency, and receives the wave reflectedfrom objects. As can be illustrated in Fig. 3(a), for a movingtarget, the received frequency would be shifted (i.e., Dopplershift), resulting in two different offset frequencies andfor the falling and rising ramps. Denoting the modulation rangeand period as and , respectively, we can derive the distance

and the relative velocity as

(5)

(6)

where represents the center frequency and the speed of light.In this design, we have MHz, and msec,leading to a ranging resolution of approximately21.4 cm. Here, we assume and are obtained by countingtheir cycles, which must be integers in each period. Sincethe detectable offset frequencies need to be counted at least oncein each ramp, we conclude that the minimum (and ) isequal to . By the same token, the lowest difference be-tween the two offset frequencies is equal tokHz. It translates to a speed resolution of , whichis equal to 4.7 km/h. For automotive application, these resolu-tions are sufficient in most cases.

It is also interesting to look into the maximum ranging limitsof such an FMCW radar. For a stationary object standing veryfar away from the detector, the two sawtooth waveforms becomeapart from each other. This extreme case is shown in Fig. 3(b),where . Such a condition corresponds to a dis-tance of km, given that the very unstable

and (only appear for a very short period of time) canbe obtained. Similarly, the maximum detectable speed can becalculated as illustrated in Fig. 3(c). Here, one of the offset fre-quencies drops to zero under this circumstance. The maximumdetectable speed is therefore given by , which isa function of distance . For m, the highest detectablespeed is about 2182 km/h. Since we are looking at distance andspeed 2–3 orders less than the extreme cases, the FMCW oper-ation here is quite robust.

III. TRANSCEIVER ARCHITECTURE

The transceiver architecture is illustrated in Fig. 4(a). It con-tains an RF front-end (PA, LNA, and mixer), two high-gain an-tennas, an FMCW generator (basically a fractional- synthe-sizer), and an FPGA-based signal processor. By tuning the di-vide modulus, the full-rate VCO delivers FMCW carrier signalaround 77 GHz directly to the PA, the mixer, and the first di-vider. One important advantage of this structure is that it re-quires no frequency doublers or triplers, simplifying the circuitdesign by eliminating lots of mm-wave blocks. The referenceclock is set to about 700 MHz, created by an external


PLL with a crystal oscillator (50 MHz) for simple implementa-tion. If necessary, this low-speed PLL can be further integratedinto the transceiver. A 16-bit - modulator produces a 3-bitmodulation signal for the – divider, which follows the2nd divider. Note that the power consumption of this architec-ture is at least 2 orders less than that of the DDFS version. Thefull-rate clock is amplified by the PA and coupled to the antennadirectly.

In the receiver path, another antenna captures the reflectedsignal. After the LNA and mixer, we obtain the IF signal andhave it digitized by means of an external analog-to-digital con-verter (ADC) before sending it to the digital signal processor(DSP). The ADC provides 12-bit output with sampling rate of3 MSample/s. Again, if necessary, it can be easily included inthe main chip. Since the IF is quite low, the ADC power con-sumption can be kept less than 1 mW [28]. An FFT algorithm isimplemented in the FPGA to calculate the distance and speed,which can track up to 5 objects simultaneously. In order toachieve the best frequency resolution, the FFT sampling timeshould be as large as to fully utilize the information forIF frequency estimation at each and interval. However,since the number of FFT points are usually a power of 2, theFFT sampling time here may be slightly smaller thanif the sample rate is pre-selected. In this design, we choose a2048-point FFT with 3-MSample/s sampling rate, leading to anFFT sampling time as

(7)

Equation (7) corresponds to 1.46-kHz frequency resolution.It is also important to look at the modulation mechanism. As

shown in Fig. 4(b), the ramp is composed of 8192 steps withstepping rate of about 10.9 MHz . Note thatthe stepping is accomplished by using the output, whichfacilitates the synchronization between DSP (in FPGA) and themodulation logics (on chip). The - resolution is thus givenby

(8)

In other words, each step corresponds to 2 LSBs. The loop band-width of the frequency synthesizer is of great concern as well. Inorder to achieve a linear triangular profile with steep turn-aroundpoints, the bandwidth must be much greater than the modulationfrequency, which is 0.67 kHz, and less than the stepping rate,which is 10.9 MHz [Fig. 4(c)]. In this design, the loop band-width is set to be 1 MHz as an optimal value.

Other issues may affect the transceiver performance and needto be considered carefully. For example, to extract andcorrectly, the logics on the board and the chip must be synchro-nized by the same reset and clock signals. Adaptability is impor-tant as well. Parameters such as and had better be madeprogrammable to meet different standards.

Fig. 5. (a) VCO and its tuning range, (b) 1st frequency divider stage.

Fig. 6. 38.5-GHz frequency divider.

IV. BUILDING BLOCKS

In this section, we introduce circuit details of building blocksand their design considerations.

A. VCO and Frequency Dividers

Fig. 5(a) depicts the 77-GHz VCO design. It is implementedas a standard tank structure with thick-oxide (5.6-nm) varac-tors to suppress the leakage. Simulation suggests a tuning rangeof about 1 GHz. To drive a large loading of 66 fF for the divider,the PA, and the mixer at 77 GHz, we employ a pseudo-differen-tial tuned amplifier pair - as a buffer. It is also possibleto incorporate a cascode structure to further isolate the VCO.However, in such a low-supply design, the buffer’s output swingwould be somewhat degraded, if another deck of devices wereadded. The parasitic capacitance introduced at internal nodeswould cause significant loss as well.

The first divider stage is realized as a direct injection-lockedtopology [Fig. 5(b)], where the injection signal is ac-coupled tothe gate of the switch . The bias voltage affects the lockrange significantly. Higher produces a larger lock range bydegrading the tank , which in turn decreases the output swing.As can be clearly shown in Fig. 5(b), with input swing of 800mV , the divider fails for V, where the equivalent


Fig. 7. (a) Prescaler design, (b) �� cell, (c) CML-to-CMOS converter.

tank loss exceeds . Here, we choose V toarrive at a lock range of 4 GHz with sufficient design margin.Note that injection-locked dividers present much less kickbackthan their static counterparts.

The second divider is implemented as a static topology withcurrent-mode logic (CML) structure, class-AB biasing, and in-ductive peaking (Fig. 6) [29]. Simulation shows that for inputswing of 260 mV ( dBm, single-endedly), the lock rangeis approximately equal to 26 GHz. The peaking inductors onlygive a mild bandwidth boost and contribute negligible influenceon the static divider’s behavior. The – prescaler is illus-trated in Fig. 7(a), which follows the design in [30]. Fourcells are placed in cascade. This structure provides a simple yetrobust operation. With the 4th control bit set to 1, the divisionrange is given by – .Different types of latches2 are employed to minimize its powerconsumption while achieving high speed. Here, we map the3-bit - output to the control bits so as to tune thedivide modulus from 24 to 31 (the average divide ratio is about27.5). For completeness, we plot the cell in Fig. 7(b).Once again, class-AB biasing technique [29] is applied to thefirst cell to help driving large loading at higher speed (19.25GHz). A differential CML-to-CMOS converter is required be-tween the 2nd and the 3rd cells, which is illustrated in Fig. 7(c).Note that we take advantage of the available differential clocksto relax the heavy loading. That is, both of the pseudo-differen-tial inputs and in the 3rd cell are used to drive two latchesfor each. In 65-nm CMOS technology, the converter presents a

-dB bandwidth of 10.5 GHz while consuming only 2.2 mWof power.

B. LNA and PA

The LNA is realized as three identical gain stages [Fig. 8(a)].Here, each stage contains a cascode structure, and conjugatematching networks are placed between stages. The on-chip

2CML and true-single-phase clock (TSPC).

Fig. 8. (a) Low-noise amplifier, (b) improvement of double-shield ground.

transmission line design is not trivial at such a high frequency.For example, copper’s skin depth is equal to 0.25 m at 77GHz, whereas the thickness of M1 in 65-nm CMOS is only0.18 m. To prevent significant leakage to the substrate, weput two layers of metal as the ground plane. Here, M1 andM2 are shunt through vias to form a thicker ground planewith no penetrating slot [31]. As demonstrated in Fig. 8(b),the LNA gain and noise figure are improved by at least 2 to4 dB by using this double-layered ground. Also, andare laid out with shared junction [32] to minimize the parasiticcapacitance of the internal node. The layout for and isillustrated in Fig. 8(a) as well. Note that if source degenerationwere used, the gain would be degraded by 2–3 dB. Since thereceiver’s noise figure is primarily determined by the mixer andIF amplifier, it is good to keep the LNA in high gain region.

The PA design is depicted in Fig. 9(a). It is a 5-stage structurein cascade with conjugate matching in between. Each stage ismade of a single-stage class-A amplifier. Here, to improve sta-bility, it is desirable to add local bypass, e.g., a capacitor, to thesupply. However, this bypass capacitor can never be large (usu-ally 1–2 pF) since it has to accommodate limited space betweenstages. As a result, the bypass impedance raises up to a higher


Fig. 9. (a) Power amplifier, (b) impedance �� and � of bypass network as afunction of frequency with parasitics considered.

value at low frequencies, possibly introducing more noise cou-pling or even oscillation.

To reduce the impedance and quality factor at low frequen-cies, we can introduce an additional - branch [33]. Theoverall impedance seen looking into the - - networkis now given by

(9)

In our design, pF, pF, and ,arriving at a zero at 1.6 GHz and two poles at dc and 8.2 GHz,respectively. Similarly, the equivalent of this bypass networkis defined as

(10)

which must be low enough for any frequency. However, (9) and(10) are over simplified as they contain no parasitics. Fig. 9(b)reveals the simulated results with parasitic inductance and resis-tance taken into account. Note that we can not use - solely,otherwise the PA’s gain will be degraded significantly (owing to

). Simulation suggests that this PA presents a gain higher than13 dB. The degeneration transmission lines are used here to im-prove stability and wideband matching.

C. Mixer, IF Amplifier, and - Modulator

The mixer design is shown in Fig. 10(a). In order to conformto the 1.2-V supply and ensure abrupt switching on and

, we separate the gain and switching stages [34], i.e., a tunedamplifier couples its output to the common-source node of theswitching pair - . A single-balanced structure is used toreduce the LO port loading. Since IF is less than LO frequencyby approximately 5 orders of magnitude, the LO feedthroughcan easily be eliminated. Note that if a double-balanced mixerwere used, the LO port would present capacitive loading twiceas large to the VCO and its buffer. Most RF current flows into

Fig. 10. (a) Mixer, (b) IF amplifier, (c) 16-bit �-� modulator.

Fig. 11. (a) Die photograph, (b) testing setup.

the switching pair - rather than the tail current , sincethe latter presents an output impedance much greater than theimpedance seen upwards. Parasitic capacitance associated withnode is absorbed as part of the matching network. The mixergain is estimated to be 5 dB.

The down-converted IF signal needs to be enlarged to at least5 mV before it can be processed by the ADC. The IF amplifieris composed of 3 differential pairs and an offset compensationunit loaded to the first stage, which could neutralize any possibleoffset up to 300 mV [Fig. 10(b)]. Although the offset cancella-tion in this prototype is designed for manual tuning,3 it could beeasily modified as an automatic calibration scheme [35], [36].The IF amplifier is capable of providing 16-dB gain.

The 16-bit - modulator is illustrated in Fig. 10(c).Adopting standard MASH 1-1-1 structure [37], this modulatoris inherently stable. All the blocks are operated in pure digitalmode. The 3-bit output (averagely equal to ) is pro-duced by the -times carry overflow of the first accumulatorin every cycles. Note that the carries of the second and thethird accumulators do not affect the output average value dueto the differentiators . Integrated with modulationcontrol logics, the adders, delay cells, and other digital blocksare synthesized by Design Compiler and are placed-and-routed

3In real measurement, the observed offset is very small and we do not needto tune it out manually.


Fig. 12. Spectra of 77-GHz synthesizer: (a) integer-� , (b) fractional-� op-eration. (c) Phase noise plots under integer-� operation, (d) spread spectrumunder frequency modulation.

by Astro [38]. Guard rings made of n-well and p diffusionlayer are placed around the - modulator to isolate thecreated digital noise.

V. EXPERIMENTAL RESULTS

The transceiver chip has been fabricated in 65-nm CMOStechnology. Fig. 11(a) shows the die photo, which measures0.95 1.1 mm . The circuit (FPGA not included) consumes atotal power of 243 mW, of which 73 mW dissipates in the fre-quency synthesizer, 115 mW in PA, 30 mW in LNA, and 25mW in the mixer and buffers. The testing setup is also shownin Fig. 11(b). An external PLL (CDCE62002) [39] provides the700 MHz reference clock, and an ADC (ADS7882) [39] digi-tizes the IF signal. Both of them can be further merged into thetransceiver in future design. A low-cost FPGA evaluation board(Altera DE0 Board) [40] has been used for FFT calculation. Theradar transceiver as well as individual building blocks are testedon a probe station. A fully-assembled module has also been im-plemented, whose link budget is degraded by about 12 dB dueto bonding wire loss and mismatch loss especially at transmitteroutput. We here summarize the measurement results obtainedfrom probing as follows.

Fig. 12(a) and (b) reveal the output spectra of the 77-GHzsynthesizer under integer- and fractional- operation, sug-gesting phase noise of and dBc/Hz at 1-MHzoffset, respectively. The reference spurs are dBc and thefractional spurs dBc. Note that these spikes have little in-fluence on the radar performance, because the fractional spursvary all the time due to the modulated carrier frequency. In otherwords, after averaging no stationary spur can be created to causefalse alarm. Phase noise plots are also depicted in Fig. 12(c).Here, the phase noise of the full-rate clock is not directly avail-able due to our limited equipment [29]. We instead plot thephase noise of the divided-by-4 output along with that of the700-MHz reference. The 19-GHz output reveals phase noise of

dBc/Hz at 1-MHz offset, demonstrating that the first two

Fig. 13. FMCW modulation profile and accuracy.

Fig. 14. LNA measurement: (a) S-parameters, (b) noise figure.

Fig. 15. PA measurement: (a) S-parameters, (b) large signal performance.


Fig. 16. (a) IF spectrum while detecting an object 102-m away, (b) link budget.

TABLE IPERFORMANCE SUMMARY

divider stages contribute negligible noise. It also follows the ref-erence profile tightly until 100 kHz offset. The integrated jitterfrom 100 Hz to 1 GHz is equal to 293 fs. The output spec-trum under modulation is shown in Fig. 12(d), which presents aspreading range of 700 MHz.

By using a standalone synthesizer, we can even record the tri-angular frequency profile as shown in Fig. 13. The root-mean-square (rms) frequency error including the turn-around pointsis less than 300 kHz, which is superior to that of conventionalDDFS-based transceivers by at least 1 order [27]. Note thatthe standalone synthesizer provides slightly lower modulationrange , which is approximately 500 MHz.

To verify the performance of each block, we have also testedthe LNA and PA individually. Here, both small- and large-signalmeasurements are conducted. The LNA achieves 17.5-dB gain,7.4-dB NF, -dBm , and -dBm at 77 GHz.Fig. 14 depicts the LNA S-parameter and NF around the band

of interest. The PA reveals a peak gain of 13.7 dB, with a -dBbandwidth of 21.5 GHz, of 6.7 dBm, of 10.5 dBmand maximum PAE of 8.4% (Fig. 15).

Fig. 16(a) shows the IF spectrum while detecting an objectabout 0.4 0.6 m at 102 meters away. We can see an IF line of

dBm at about 635 kHz. Note that the undesired spur causedby stepping does not appear, since we choose a low IF and ahigh modulating resolution. It serves as another advantage ascompared with other FMCW designs [27]. The link budget is il-lustrated in Fig. 16(b). For a mid-size car, the longest detectabledistance is about 110 meters, which matches our measurementclosely. Furthermore, the noise floor at the IF is about dBm,which implies that the total NF of the receiver is about 30 dB.

We have also verified the accuracy of this radar system, andshown in Fig. 17(a) and (b) are the results for distance andspeed. A picture of this out-door measurement is also shownin Fig. 17(c). A mid-size car with cross-section area of 30 m


Fig. 17. Accuracy for (a) distance, (b) velocity measurements, (c) picture ofmeasurement setup.

Fig. 18. (a) 8� 8 patch array antenna, (b) its gain and bandwidth, (c) radiationpattern E- and H-planes.

serves as a target, and accurate speed meters as well as long-range measuring tapes are used. The maximum detectable is106 meters. Note that the rms error is less than the resolution inboth cases here, demonstrating the accuracy of this work. Table Isummarizes the overall performance, and compares this workwith some other FMCW radar transceivers and front-ends pre-viously published. Other 77-GHz circuits such as [42] and [43]can also be found in the literature.

VI. FUTURE WORK

The antenna is of great importance in a radar system and isworthy of further modification. As discussed in Section I, inorder to reach a long distance, we need high-gain antennas suchas horn or dish to concentrate the radiation energy. In such cases,signal at 77 GHz must be transformed from coplanar wave-guide to rectangular waveguide mode, and vice versa. All of the

Fig. 19. Photos of the 77-GHz radar system with integrated transceiver (chip)and on-board antennas.

mm-wave components (antennas, adaptors, etc) are very costlybecause they require delicate manufacture techniques and pre-cise mechanical placement.

A low-cost solution may be found if we use a patch antennaarray. It is well known that a large antenna array could get ahigh gain by focusing the radiation energy. As demonstratedin Fig. 18, we design an 8 8 patch array on a commer-cially-available PC board, RO4003C [41], which occupies anarea of approximately 2.3 2.5 cm on a board with .Tree-structure corporate feeding paths guarantee that the overallradiation is constructive. Using 8 8 elements, we can achieve

-dBi gain and -GHz bandwidth [Fig. 18(b)], quiteclose to the requirement of automotive FMCW radar systems.The radiation patterns for E- and H-planes are also shown inFig. 18(c), revealing beamwidth of 10 and 9 , respectively. Aradar module incorporates 8 8 patch antenna arrays has beendemonstrated in Fig. 19, which achieves a ranging distance ofat least 40 meters in preliminary test. It is absolutely possibleto extend this distance to over 100 meters by modifying the RFfront-ends as well as the DSP baseband.

VII. CONCLUSION

A fully-integrated 77-GHz FMCW radar transceiver has beenproposed in this paper. Utilizing fractional- synthesizer as anFMCW engine, we substantially reduce the complexity of thecircuit and board designs. Significant power and area can besaved by this architecture, leading to a low-cost solution. Mil-limeter-wave front-end realized in CMOS technology has beendemonstrated as well. With baseband processors and high-gainantennas included, this work provides a complete realization ex-ample, which reveals promising potential for future automotiveapplications.

ACKNOWLEDGMENT

The authors thank the TSMC University Shuttle Program forchip fabrication.


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Jri Lee (S’03–M’04) received the B.Sc. degree inelectrical engineering from National Taiwan Univer-sity (NTU), Taipei, Taiwan, in 1995, and the M.S. andPh.D. degrees in electrical engineering from the Uni-versity of California, Los Angeles (UCLA), both in2003.

After two years of military service (1995–1997),he was with Academia Sinica, Taipei, Taiwan from1997 to 1998, and subsequently Intel Corporationfrom 2000 to 2002. He joined National TaiwanUniversity (NTU) since 2004, where he is currently

an Associate Professor of electrical engineering. His current research interestsinclude high-speed wireless and wireline transceivers, phase-locked loops, anddata converters.

Prof. Lee received the Beatrice Winner Award for Editorial Excellence at the2007 ISSCC, the Takuo Sugano Award for Outstanding Far-East Paper at the2008 ISSCC, the best technical paper award from Y. Z. Hsu memorial foun-dation in 2008, the T. Y. Wu memorial award from national science council(NSC), Taiwan in 2008, the Young Scientist Research Award from AcademiaSinica in 2009, and the Outstanding Young Electrical Engineer award in 2009.He has also received NTU outstanding teaching award in 2007, 2008, and 2009.He has served as a Guest Editor of the IEEE Journal of Solid-State Circuits in2008 and a tutorial Lecturer at the 2009 ISSCC. He is now serving in the Tech-nical Program Committees of the International Solid-State Circuits Conference(ISSCC), Symposium on VLSI Circuits, and Asian Solid-State Circuits Confer-ence (A-SSCC).


Yi-An Li was born in Taichung, Taiwan, in 1986. Hereceived the B.S. and M.S. degrees in electrical en-gineering from National Taiwan University, Taipei,Taiwan, in 2008 and 2010, respectively.

His research interests include phase-locked loopsand frequency synthesizers.

Meng-Hsiung Hung was born in Tainan, Taiwan,in 1986. He received the B.S. degree in electricalengineering from National Tsing-Hua University,Hsinchu, Taiwan, in 2008, and the M.S. degreein electrical engineering from National TaiwanUniversity, Taipei, Taiwan, in 2010.

His research interests focus on millimeter-wavefront-end circuits including antenna.

Shih-Jou Huang was born in Tainan, Taiwan, in1986. He received the B.S. degree in electricalengineering from National Tsing-Hua University,Hsinchu, Taiwan, in 2008. He is currently workingtoward the Ph.D. degree at National Taiwan Univer-sity.

His research interests focus on millimeter-wavewireless transceivers.

Documents

2746 IEEE JOURNAL OF SOLID-STATE CIRCUITS, …cc.ee.ntu.edu.tw/~jrilee/publications/77G_RADAR_J.pdf · 2746 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010 AFully-Integrated77-GHzFMCWRadarTransceiver