Embed Size (px)
Citation preview
#2653 Introduction of New Materialsinto CMOS Devices
ESC Symp on Purity Silicon(E6)
8:30 – 9:00 am, October, 10, 2012
@Rm 320, Level 3,Hawaiian Convention Center, Honolulu, Hawaii
Hiroshi Iwai
Frontier Research Center, Tokyo Institute of Technology
Lee De Forest
Electronic Circuits started by the invention of vacuum tube (Triode) in 1906
Cathode(heated) Grid
Anode(Positive bias)
Thermal electrons from cathodecontrolled by grid bias
Same mechanism as that of transistor
J.E.LILIENFELD
J. E. LILIENFELD
DEVICES FOR CONTROLLED ELECTRIC CURRENTFiled March 28, 1928
3
ElectronSemiconductor
Gate Electrode
Gate InsulatorNegative bias
Positive bias
Capacitor structure with notch
No current
Current flows
Electricfield
4
Source Channel Drain
0V
N+-Si P-Si
N-Si
0V
1V
Negative
Source Channel DrainN-Si1V
N+-Si P-Si
Surface Potential (Negative direction)
Gate Oxd
ChannelSource Drain
Gate electrode
S D
G
0 bias for gate Positive bias for gate
Surface
Electron flow
5
However, no one could realize MOSFET operation for more than 30 years.
Because of very bad interface property between the semiconductor and gate insulatorEven Shockley!
6
Very bad interface property between the semiconductor and gate insulator
Even Shockley!
eGe
GeO Electric Shielding
CarrierScattering
Interfacial Charges
Drain Current was several orders of magnitude smaller than expected
7
1960: First MOSFET by D. Kahng and M. Atalla
Top View
Al
SiO2
Si
Si/SiO2 Interface is exceptionally good
8
1900 1950 1960 1970 2000
VacuumTube
Transistor IC LSI ULSI
10 cm cm mm 10 m 100 nm
In 100 years, the size reduced by one million times.There have been many devices from stone age.We have never experienced such a tremendous reduction of devices in human history.
10-1m 10-2m 10-3m 10-5m 10-7m
Downsizing of the components has been the driving force for circuit evolution
9
Downsizing1. Reduce Capacitance
Reduce switching time of MOSFETsIncrease clock frequency
Increase circuit operation speed2. Increase number of Transistors
Parallel processingIncrease circuit operation speed
Thus, downsizing of Si devices is the most important and critical issue.10
Downsizing contribute to the performance increase in double ways
Gate oxide
Gate metal
Source Drain
1V 0V0V
Substrate 0V DepletionRegion (DL)
1V
0V 0V
tox and Vdd have to be decreased for betterchannel potential control IOFF Suppression
0V < Vdep＜1V
0V
0V < Vdep＜1VChannel
0V
0V
0V0V
0.5V
Large IOFF
Region governed By drain bias
Region governed by gate bias
DL touch with SRegion (DL)
Large IOFF
No toxthinning
Vdd
Vdd
11
How far we can go with downscaling?
Question:
Tunnelingdistance
3 nm
What would be the limit of downsizing!
Source DrainChannel
14
Vg
Id
Vth (Threshold Voltage)
Vg=0V
SubthreshouldLeakage Current
Subtheshold leakage current of MOSFET
Subthreshold CurrentIs OK at Single Tr. level
But not OKFor Billions of Trs.
ONOFF
Ion
Ioff
Subthresholdregion
15
Vg (V)1
0.3 V
0.5 V 1.0 V
Ion
Ioff
Id (A/m)
10-7
10-5
10-11
10-9
Vd
Vth
0.15 V
0 0.5
Subthreshold leakage current will limit the downsizing
16
Subthreshold Leakage (A/m)
Ope
ratio
n Fr
eque
ncy
(a.u
.)
e)
100
10
1
Source: 2007 ITRS Winter Public Conf.
The limit is deferent depending on application
How far can we go for production?
10m 8m 6m 4m 3m 2m 1.2m 0.8m 0.5m
0.35m 0.25m 180nm 130nm 90nm 65nm 45nm 32nm
1970年
(28nm) 22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm?
Past 0.7 times per 3 years
Now
In 40 years: 18 generations,Size 1/300, Area 1/100,000
Future
・At least 4,5 generations to 8 ~ 5 nm
The down scaling of MOSFETs is still possible for at least another 10 years!
2. Thinning of high-k gate oxide thicknessbeyond 0.5 nm
3. Metal(Silicide) S/D
1. Wire channel
4 important technological items for down scaling.New structures
New materials
4. III-V/Ge channel, for the moment, however, very difficult to replace Si
Gate Oxide
ChannelSource Drain
Gate electrode
19
MOSFET
Channel
1960 1970 1980 1990 2000 2010 2020 2030
Si
III‐V/Ge
Gate OxideSiO2 SiON HfO2 LaSixOy
Gate ElectrodeAl Poly Si MetalWSi2/
Poly SiNiSi/Poly Si
Source DrainP/B‐dope Si As/B‐dope Si Silicide
High-k beyond 0.5 nm
K. Kim, pp.1, IEDM2010 (Samsung) 1.21.1
1
0.9
0.8
0.7
0.6
0.5
EO
T [n
m]
202020152010Year
12
10
8
6
4
2
0
Body Thickness [nm
]
Multi-Gate
Planar
ITRS2011
Fin width
EOT Scaling Trends
Wire/fin mitigates EOT thinning trend (Trend 1 Trend 2)Because of better SCE control.
However, ION severely degrade with wire/fin width reduction
Therefore, EOT trend will become accelerated again(Trend 2 Trend 3) Thus, high-k becomes important again.21
Si-sub.
Metal
SiO2-IL
High-kSmall interfacial state density at high-k/Si
Oxygen diffusion control for prevention of EOT increase and oxygen vacancy formation in high-k
Thinning or removal of SiO2-IL for small EOT
Flat metal/high-k interface for better mobility
O
Workfunction engineering for Vth control
Interface dipole control for Vth tuning
Suppression of oxygen vacancy formation
Control of interface reaction and Si diffusion to high-k
Oxygen concentration control for prevention of EOT increase and oxygen vacancy formation in high-k
Suppression of metal diffusion
Endurance for high temperature process
Remove contaminationintroduced by CVD
Reliability: PBTI, NBTI, TDDB
Suppression of gate leakage current
Suppression of FLP
22
Issues in high‐k/metal gate stack
0 10 20 30 40 50Dielectric Constant
4
2
0
-2
-4
-6
SiO2
Ban
d D
isco
ntin
uity
[eV]
Si
XPS measurement by Prof. T. Hattori, INFOS 2003
Conduction band offset vs. Dielectric Constant
Band offset
Oxide
Leakage Current by Tunneling
23
R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)
Gas or liquidat 1000 K
H
Radio activeHe
Li Be B C N O F Ne① Na Mg Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① ① K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ① ① ① ① Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe ③ ① ① ① ① ① ① ① Cs Ba Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn Fr Ra Rf Ha Sg Ns Hs Mt
La Ce Pr Nd PmSmEu Gd Tb Dy Ho Er Tm Yｂ Lu Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
Candidates
Na Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ①
Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
②
③
Unstable at Si interfaceSi + MO X M + SiO 2①
Si + MO X MSi X + SiO 2
Si + MO X M + MSi XOY
Choice of High-k elements for oxide
HfO2 based dielectrics are selected as the first generation materials, because of their merit in1) band-offset, 2) dielectric constant3) thermal stability
La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer
24
SiO2-ILHfSix (k~4)
VO
IO
IOVO
VO
IOIO
VOHfO2
Si substrate SiO2-IL(k~4)
LaSix
VO
IOVO
IO
VO
IOLa2O3silicate
La-rich Si-rich
Si substrate
High PO2Low PO2 High PO2Low PO2
SiO2 IL formation
Si substrate
silicate formation
Si substrate
HfO2 case La2O3 case
Direct contact can be achieved with La2O3 by forming silicate at interfaceControl of oxygen partial pressusre is the key for processing.
Our approach
K. Kakushima, et al., VLSI2010, p.69
Direct high‐k/Si by silicate reaction
26
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
Si sub.
Hf SilicateSiO2
500 oC
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
Si sub.
Hf SilicateSiO2
500 oC
SiOx-IL growth at HfO2/Si Interface
HfO2 + Si + O2 → HfO2 + Si + 2O*→HfO2+SiO2
Phase separator
SiOx-IL is formed after annealingOxygen control is required for optimizing the reaction
Oxygen supplied from W gate electrode
XPS Si1s spectrum
D.J.Lichtenwalner, Tans. ECS 11, 319
TEM image 500 oC 30min
H. Shimizu, JJAP, 44, pp. 6131
27
La-Silicate Reaction at La2O3/Si
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
as depo.
300 oC
La-silicate
Si sub.
500 oC
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
as depo.
300 oC
La-silicate
Si sub.
500 oC
La2O3 + Si + nO2→ La2SiO5, La2Si2O7,
La9.33Si6O26, La10(SiO4)6O3, etc.
La2O3 can achieve direct contact of high-k/Si
XPS Si1s spectraTEM image
Direct contact high-k/Si is possible
28Year
Pow
er p
er M
OSF
ET (P
)
EOT Limit0.7~0.8 nm
EOT=0.5nm
TodayEOT=1.0nm
Now
45nm node
One order of Magnitude
Si
HfO2
Metal
SiO2/SiON
Si
High‐k
Metal
Direct ContactOf high-k and Si
Si
Metal
SiO2/SiON
0.5～0.7nm
Introduction of High-kStill SiO2 or SiONIs used at Si interface
For the past 45 yearsSiO2 and SiON
For gate insulator
EOT can be reduced further beyond 0.5 nm by using direct contact to SiBy choosing appropriate materials and processes.
29
Substrate
Moving Mask
SourceElectron Beam
Flux
Deposited thin film
Robot
EB Evaporation Flash Lamp Anneal
ALD
RTA
Sputter
EB Evaporation
Flash Lamp Anneal
ALDRTAEntrance
Entrance
Sputter
High-k/metal gate stackfilm deposition cluster tool
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
0 0.5 1 1.5 2 2.5 3
EOT ( nm )
Cur
rent
den
sity
( A
/cm
2 )Al2O3HfAlO(N)HfO2HfSiO(N)HfTaOLa2O3Nd2O3Pr2O3PrSiOPrTiOSiON/SiNSm2O3SrTiO3Ta2O5TiO2ZrO2(N)ZrSiOZrAlO(N)
Gate Leakage vs EOT, (Vg=|1|V)
La2O3
HfO2
30
31
0.0E+00
5.0E-04
1.0E-03
1.5E-03
2.0E-03
2.5E-03
3.0E-03
3.5E-03
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2VI d
(V)
W/L = 50m /2.5m
Vd (V) Vd (V) Vd (V)
EOT=0.37nm
Vth=-0.04VVth=-0.05VVth=-0.06V
EOT=0.37nm EOT=0.40nm EOT=0.48nm
W/L = 50m /2.5m W/L = 50m /2.5m
0.48 0.37nm Increase of Id at 30%
La2O3 at 300oC process make sub-0.4 nm EOT MOSFET
32
2
1.5
1
0.5
0
Cap
acita
nce
[F/
cm2 ]
-1 -0.5 0 0.5 1Gate Voltage [V]
10kHz 100kHz 1MHz
20 x 20m2 1.5
1
0.5
0
Cap
acita
nce
[F/
cm2 ]
-1.5 -1 -0.5 0 0.5Gate Voltage [V]
20 x 20m2
10kHz 100kHz 1MHz
2
1.5
1
0.5
0
Cap
acita
nce
[F/
cm2 ]
-1.5 -1 -0.5 0 0.5Gate Voltage [V]
20 x 20m2
10kHz 100kHz 1MHz
FGA500oC 30min FGA700oC 30min FGA800oC 30min
A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800oC)
However, high-temperature anneal is necessary for the good interfacial property
33
① silicate-reaction-formedfresh interface
metal
Si sub.
metal
Si sub.
La2O3 La-silicateSi Si
Fresh interface with silicate reaction
J. S. Jur, et al., Appl. Phys. Lett., Vol. 87, No. 10, (2007) p. 102908
② stress relaxation at interface by glass type structure of La silicate.
La atomLa-O-Si bonding
Si sub.
SiO4tetrahedron network
FGA800oC is necessary to reduce the interfacial stress
S. D. Kosowsky, et al., Appl. Phys. Lett., Vol. 70, No. 23, (1997) pp. 3119
Physical mechanisms for small Dit
34
No interfacial layer can be confirmed with Si/TiN/W
La2O3Si/TiN/W
300
250
200
150
100
50
0
Elec
tron
Mob
ility
[cm
2 /Vse
c]
10.90.80.70.60.5EOT [nm]
at 1MV/cmT = 300K
Open : Hf-based oxides
Gate leakage is two orders of magnitude lower than that of ITRS.
Electron mobility is comparable to record mobility with Hf-based oxides.
10-2
10-1
100
101
102
103
104
J g a
t Vg
= 1V
[A/c
m2 ]
0.80.750.70.650.60.550.5EOT [nm]
A = 10 x 10m2
ITRS requirements
MIPS Stacks
This work (MIPS Stacks)
T. Ando, et al., (IBM) IEDM 2009, p.423
T. Kawanago, et al., (Tokyo Tech.) T-ED, vol. 59, no. 2, p. 269, 2012
35
Benchmark of La‐silicate dielectrics
EOT Mobility Vth SS DIBLGate stack Ref.
0.5nmMetal(A)/Cap/HfO2 110cm2/Vs
(at 0.8MV/cm)IMEC
IEDM20090.3V
(Lg=1um)
0.52nmTiN/Cap/HfO2 110cm2/Vs
(at 1x1013cm-2)IBM
VLSI2011~0.4V
(Lg=24nm) 90mV/dec 147mV/V
0.59nmMetal/HfO2 130cm2/Vs
(at 1MV/cm)0.45V
(Lg=1um) 75mV/decSematechVLSI2009
0.65nmMetal/Hf-basedSamsungVLSI2011
0.3~0.4V(Lg=~30nm) 90mV/dec 100mV/V
0.95nmMetal/Hf-basedIntel
IEDM2009~0.3V
(Lg=30nm) 100mV/dec ~200mV/V
0.62nmW/La-silicateTokyo Tech.T-ED2012
-0.08V(Lg=10um) ~70mV/dec
155cm2/Vs (at 1MV/cm)
0.55nmTiN/Cap/HfO2 140cm2/Vs
(at 1MV/cm)IBM
VLSI2009
36
Si benchmark (nMOSFET)
0
20
40
60
80
100
120
140
160
180
0 0.5 1 1.5 2
EOT = 0.53nm
L/W = 20/20m
T = 300K
Nsub = 3×1016cm-3
Eeff [MV/cm]El
ectr
on M
obili
ty [c
m2 /V
sec]
Recent results by my group.
substrate
①La gas feed ②Ar purge ③H2O feed ④Ar purge
La
ligand HO
substrate substrate substrate
1 cycle
La
C 3H7
3
L a
C 3H7
3
L a
C 3H7
3
CLaN
NH
C3H7
C3H7
La(iPrCp)3 La(FAMD)3
Precursor (ligand)
ALD is indispensable from the manufacturing viewpoint- precise control of film thickness and good uniformity
K. Ozawa, et al., (Tokyo Tech. and AIST) Ext. Abstr. the 16th Workshop on Gate Stack Technology and Physics., 2011, p.107.
38
ALD of La2O3
Metal (Silicide) S/D
Extreme scaling in MOSFET Lphy
Dop
antC
onc. Gate
Met
al C
onc.
Gate
Lphy = Leff- Atomically abrupt junction- Lowering S/D resistances- Low temperature process for S/D
Metal Schottky S/D junctions
- Dopant abruptness at S/D- Vt and ION variation- GIDL
Schottky Barrier FET is a strong candidate for extremely scaled MOSFET S DChannel
S DChannel
n+-Sin+-Si
Metal Silicide
Metal Silicide
41
Surface or interface controlDiffusion species:
metal atom (Ni, Co)Rough interface at silicide/Si- Excess silicide formation- Different Bn presented
at interface- Process temperature
dependent composition
Diffusion species: Si atom (Ti)Surface roughness increases- Line dependent
resistivity change
Line widthof 0.1 m
H. Iwai et al., Microelectron. Eng., 60, 157 (2002).
Top view
Epitaxial NiSi2
O. Nakatsuka et al., Microelectron. Eng.,83, 2272 (2006).
Si(001) sub.Annealing: 650 oC
42
Si substrate
Ni-silicide
Si substrate
Si substrate
Ni-silicide
Si substrate
Deposition of Ni film
Deposition fromNiSi2 source Annealing Flat interface
Roughinterface
No Si substrateconsumption
Annealing
Deposition of Ni-Si mixed films from NiSi2 source
- No consumption of Si atoms from substrate- No structural size effect in silicidation process- Stable in a wide process temperature range
43
SEM views of silicide/Si interfaces
NiSi2 source
‐ Rough interfaces‐ Consumed Si substrate ‐ Thickness increase ~100 nm
Ni source
‐ Atomically flat interfaces‐ No Si consumption‐ Temperature‐independent
Si substrate
Ni-silicide
Ni source
Ni-silicide
Si substrate
NiSi2 source
STI
44
Ideal characteristics (n = 1.00, suppressed leakage current)
Suppressed reverse leakage current- Flat interface and No Si substrate consumption- No defects in Si substrate
Ni
NiSi2
-0.8 -0.6 0.0 0.2Diode voltage (V)
-0.4 -0.210-5
10-4
10-3
10-2
Dio
de c
urre
nt (A
/cm
2 )
1.001.08
n
0.659NiSi2
0.676NiBn (eV)Source
1.001.08
n
0.659NiSi2
0.676NiBn (eV)Source
Generation current
RTA：500oC, 1min
Schottky diode structures
Leakage currentAl contact
Ni source
Al contact
NiSi2 source
Si substrate
Si substrate
NiSi2 sourceApplied Voltage (V)
Cur
rent
den
sity
(A/c
m2 )
45
III-V/Ge Channel
S D
1) High injection Velocity of carriers
2) High mobility of carriers
Both 1) and 2) are important
Arming higher performance at lower supply voltage
Problems: Technologies and CostInterfacial properties at the gate insulator/semiconductor
Contact resistance at Source/Drain and semiconductor
Different semiconductors for n- and p- channel FETs
Integration on Si wafer
vinj
III-V (n-channel) or Ge (p-channel)
47
Why high mobility channel materials?
Ge,III-V bulk properties
S. Takagi., IEDM2011, Short course (Tokyo Uni)48
Tri‐gate InGaAs QW‐FET(Intel)M. Radosavljevic, et al.(Intel), IEDM2011, p.765.
Steepest SS and smallest DIBL ever reported (Wfin = 30nm)
Tri‐gate structure has superiority electrostatic controllability compared to ultra‐thin body planar structure
49
Ge‐nanowire pMOSFET (AIST,Tsukuba)
Using Ni‐Ge alloy as metal S/D
Significantly reduces contact resistance
K. Ikeda, et al. (AIST, Tsukuba), VLSI2012, p.165.
High saturation current and high mobility
μeff = 855 cm2/Vs at Ns =5x1012cm‐2
and saturation drain current of 731μA/μm at Vd = ‐1V
Lg= 65nm Wwire= 20nmVD= -1V
VD= -0.5V
VD=-0.05V
Vg-Vth= -2V
50
Planar(metal S/D, Strain, Buffer…) FinFET Tri‐gate Gate‐all‐around
MOSFET Nanowire
material InGaAs Ge InGaSn InGaAs Ge InGaAs Ge InGaAs Ge InGaAs(multishell)
Ge
Dieletric/EOT
Al2O3/ 3.5 nm
7.6 Ao
HfO2+ Al2O3+GeO2
5nm ALDAl2O3
5nm ALD Al2O3
SiON 1.2 nm5.5 nm(Al2O3+GeO2)
10nm‐ALD Al2O3
HfO2:11nm
HfAlO14.8 nm
3.0 nm(ALD Al2O3)
Mobility ‐ ~600(cm2/Vs)
e: 200h: 400
~700(S/m)
‐ ‐ ‐ 701(S/m)
‐ ~500(S/m)
~850(cm2/Vs)
Lch (nm) 55 W/L=30/5 m 50 m 100 4.5 m 60 183 50 200 200 65
DIBL(mV/V) 84 ‐ ‐ 180 ‐ ~50 ‐ 210 ‐ ‐ ‐
SS(mV/dec) 105 ‐ 61pMOS
33nMOS 145 750 90 130 150 160 ‐ ‐
ION(A/m)
278(VD=0.5V)
3(VD=‐0.2V)
4 (n,p)(VD=0.5V)
‐ 10(VD=0.5V)
400(VD=0.5V)
235(VD=‐1V)
180(VD=0.5V)
604(VD=‐0.5V)
100(VD=0.5V)
731(VD=‐1V)
ResearchGroup
Tokyo UniVLSI 2012
Tokyo UniVLSI 2012
Stanford Uni VLSI 2012
Purdue Uni IEDM 2009
Stanford Uni ELD 2007
IntelIEDM 2011
NNDL Taiwan
IEDM 2011
Purdue Uni IEDM 2011
ASTARSingapore IEDM 2009
Hokkaido Uni, IEDM
2011
AIST Tsukuba VLSI 2012
150K
120K
(cm2/Vs)
Ns: 5e12
III-V/Ge benchmark for various structures
51
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
0 0.4 0.8 1.21.E-09
1.E-08
1.E-07
1.E-06
1.E-05
0 0.4 0.8 1.2
Metal S/D InGaAs‐OILch= 55nm, EOT 3.5nmVDS=0.5V(Tokyo Uni.)[5]
InGaAs NanowireLg= 200nm, Tox 14.8nmVDS=0.5V(Hokkaido Uni.)[4]
InGaAs FinFETLch=130nmEOT 3.8nmVDS=0.5V (NUS)[3]
InGaAs Tri‐gateLg=60 nm,EOT 12AVDS=0.5V (Intel) [2]
InGaAs GAALch=50nm, Dielectric: 10nm Al2O3VDS=0.5V (Purdue Uni.) [1]
Ge Tri‐gateLg=183nm, EOT 5.5nmVD=‐1V (NNDL Taiwan)[9]
Ge GAA Lg= 300nm, dielectric: GeO2(7nm)‐HfO2(10nm)VD= ‐0.8V (ASTAR Singapore)[8]
Ge FinFETLg=4.5 mm, Dielectric: SiON, VDS=‐1V(Stanford Uni.)[7]
GOI Tri‐gateLg: 65nm. EOT 3.0nmVD=‐1V (AIST Tsukuba)[6]
Si‐bulk 45nmIntel VDD=1V
I OFF(A/m)
ION (mA/m)
nMOS pMOS
ION (mA/m)[1] J. J. Gu et al., pp.769, IEDM2011 (Purdue).[2] M. Radosavljevic et al., pp.765, IEDM201(Intel).[3] H. –C. Chin et al., EDL 32, 2 (2011) (NUS)[4] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni).
[6] K. Ikeda et al., pp.165, VLSI2012 (AIST, Tsukuba).[7] J. Feng et al., IEEE EDL 28(2007)637 (Stanford Uni)[8] J. Peng et al., pp.931, IEDM2009 (ASTAR Singapore)[9] S. Hsu et al., pp.825, IEDM2011 (NNDL Taiwan)
[5] S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)
Si‐bulk 45nmIntel VDD=1V[11]
Si‐FinFET 32nmIntel VDD=0.8V [10]
Si‐FinFET 32nmIntel VDD=0.8V [10]
[10] C. Auth et al., pp.131, VLSI2012 (Intel).
[11] K. Mistry et al., pp.247, IEDM2007 (Intel).
Si‐FinFET 22nmIntel VDD=0.8V [10]
Si‐FinFET 22nmIntel VDD=0.8V [10]
Multi-gate III-V and Si benchmark
52
2018 2022 2024 2026
Lg (nm)
Vdd (V)
EOT (nm)Mobility enhancement
factor due tochannel material
Year of Production 2020
14 11.7 9.3 7.4 5.80.63 0.61 0.58 0.56 0.540.68 0.62 0.56
8 8 8 8 80.50 0.45
4 4 4 4 4GeIII-V
0.28 0.24 0.20 0.16 0.130.41 0.36 0.30 0.25 0.21Ge
III-VCg Ideal(fF/m)
229 230 238 245 251230 231 241 249 254Ge
III-VVt,sat (mV)
0.13 0.11 0.09 0.07 0.060.21 0.17 0.13 0.10 0.08Ge
III-VCV/I (ps)
Manufacturing solutionsare NOT known
53
ITRS 2011 for III‐V/Ge
2018 2022 2024 2026
Lg (nm)
Year of Production 2020
14 11.7 9.3 7.4 5.84.29 4.58 5.32 5.93 6.642.26 2.44 2.86 3.19 3.63Ge
III-V
2.200 2.343 2.523 2.703 2.8841.769 1.932 2.121 2.330 2.555Ge
III-V
131 113 96 82 70149 126 105 85 72Ge
III-V
0.18 0.15 0.13 0.11 0.090.23 0.20 0.16 0.14 0.11Ge
III-V
Equivalent Injection velocity
Vinj (107 cm/s)
Id,sat(mA/m)
Isd,leak (nA/m) 100 100 100 100 100Rsd
(Ω-m)
CV2
(fJ/m)
Manufacturing solutionsare NOT known
54
ITRS 2011 for III‐V/Ge, Contd
C based materials
55
A. D. Franklin et al., pp.525, IEDM2011 (IBM)
Sub-10nm carbon nanotube transistor
Transistor operation with Lch of 9nm 56
Z. Chen et al., pp.509, IEDM2008 (IBM)
Graphene Field-effect TransistorJ. B. Oostinga et al., Nature Materials 7 (2008) 151
・Ambipolar Characteristics
・Bi-layer graphene and double gates can open the gap
57・ Ioff is very large No bandgap
58
Conclusions
Si-MOSFET is the most fundamental and smallest functional device available for manufacturing.
In order to keep the scaling of MOSFETs, aggressive introduction of new materials is inevitable.
Thank you for your attention!
59
