258 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, …rwe/references/LevBus2016.pdfple, while regulating the bus voltage efﬁciently during transients, and must therefore balance

258 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 1, JANUARY 2016

Bus Voltage Control With Zero Distortion and HighBandwidth for Single-Phase Solar Inverters

Yoash Levron, Member, IEEE, Sebastian Canaday, and Robert W. Erickson, Fellow, IEEE

Abstract—Single-phase inverters must include an energy storagedevice, typically a high-voltage bus capacitor, to match the inverterconstant input power to its pulsating output power. Because of itsincreased cost, the size of this bus capacitor must be minimized.However, when the bus capacitor is small, the bus voltage includes ahigh ripple at the ac line second harmonic frequency, which causesharmonic distortion. The bus voltage controller must filter this rip-ple, while regulating the bus voltage efficiently during transients,and must therefore balance a tradeoff between two conflicting con-straints, low-harmonic distortion and high bandwidth. This paperanalyzes this tradeoff, and proposes a new control method for solv-ing it without using addition hardware. Instead of reducing thedistortion by lowering the loop gain, the new controller employs adigital FIR filter that samples the bus voltage at an integer multipleof the second harmonic frequency. The filter presents a notch thatremoves the second harmonic ripple, enabling a design that oper-ates with zero distortion and high bandwidth simultaneously, andis suitable for inverters with small bus capacitors. The proposedcontroller is tested on a microinverter prototype with a 300-Wphotovoltaic panel and a 20-μF bus capacitor.

Index Terms—Bus capacitor, dc bus, dc link, harmonic distor-tion, microinverter, photovoltaic, solar.

I. INTRODUCTION

IN comparison to other photovoltaic (PV) architectures, amain advantage of the microinverter architecture is flexibil-

ity and modularity [1]. For this reason, these devices have beengaining popularity, especially at small urban installations, wheremodularity and individual maximum power point (MPP) track-ing are an advantage [2], [3]. Each microinverter is connectedto a single PV source and directly to the ac line so they are easyto install, and can track the MPP of their adjacent PV sources.In addition, the microinverter architecture is tolerant to failures,because any single failure does not disproportionately reducesthe output power of the system [4].

A common topology for microinverters is the two-stage topol-ogy [5], [6], shown in Fig. 1. Typically, the first stage tracks theMPP of the source, and boosts the low input voltage, provid-ing suitable high voltage for the second stage. The second stagegenerates the ac that is injected to the ac line, a current that is typ-ically synchronized to the line voltage. The capacitor betweenthese stages, the bus capacitor, is an internal energy storage

Manuscript received September 19, 2014; revised November 26, 2014; ac-cepted January 26, 2015. Date of publication February 2, 2015; date of currentversion September 21, 2015. Recommended for publication by Associate EditorV. Agarwal.

The authors are with the Department of Electrical, Computer, and En-ergy Engineering, University of Colorado, Boulder, CO 80309 USA (e-mail:[email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2015.2399431

Fig. 1. Two-stage single-phase microinverter with an intermediate high-voltage bus capacitor.

device [7]. The energy and, consequently, the voltage on thiscapacitor are determined by the difference in power, the con-stant input power that charges the capacitor, and the pulsatingoutput power that discharges it. Due to this difference, the busvoltage includes a harmonic component at twice the ac line fre-quency, which is a direct outcome of the balance of powers andcannot be mitigated by control. This harmonic component, thesecond harmonic ripple, may degrade the efficiency and stabilityof the inverter if not handled appropriately by the inverter con-trol circuitry [8], [9]. Traditionally, the bus capacitor has beena high-capacitance low-voltage electrolytic capacitor. However,electrolytic capacitors are known to have limited lifetime andare not compatible with the 20 year or longer lifetime that isdesired for modern solar power systems [10]. To increase thesystem lifetime, a high-voltage film or similar capacitor for en-ergy storage is preferred. Because of their increased cost, thesize of these capacitors must be minimized [11].

The bus capacitor voltage must be regulated within a boundedrange that is typically higher than the peak ac voltage but lowerthan the rated voltage of the bus capacitor and switching devices.This regulation is done by the bus voltage controller, a negativefeedback loop that stabilizes the bus voltage against variationin input power, output voltage, and other variations. The loopsenses the bus voltage and controls the output current in orderto balance the voltage on the bus. It should be quick enough tomaintain the bus voltage within acceptable range during tran-sients and, therefore, it is imperative that the loop be designedwith sufficient bandwidth. In addition to bandwidth, a seconddesign constraint is harmonic distortion in the output current[12], [13]. This distortion must be low to comply with interna-tional standards, such as the IEEE 1547 standard [14], whichrequires that the total harmonic distortion (THD) be lower than5% at rated power. As a result, the bus voltage loop must complywith two constraints: sufficient bandwidth and low-harmonicdistortion, constraints that are often contradicting, particularlywhen the bus capacitance is low [15].

0885-8993 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

LEVRON et al.: BUS VOLTAGE CONTROL WITH ZERO DISTORTION AND HIGH BANDWIDTH FOR SINGLE-PHASE SOLAR INVERTERS 259

To be cost competitive, new inverters are designed with smallbus capacitors [16], and consequently their bus voltage includesa high second harmonic ripple. With high ripple, however, itis challenging to design a loop that achieves both sufficientbandwidth and low harmonic distortion [17]. If the loop hashigh bandwidth, it responds to changes quickly and can tightlyregulate the bus voltage. However, this also introduces variationsin the output current that can lead to high and unacceptabledistortion on the ac line.

To settle the contradicting constraints of distortion and band-width, there is need for innovative designs and control methodsthat can operate with small bus capacitors that cause high secondharmonic ripple. A straightforward approach is to use a passivefilter to attenuate this ripple.

Balog and Krein [18], for example, propose a coupled induc-tor that presents a notch at the ripple frequency. Another solutionis a loop compensator that filters the second harmonic ripple,while maintaining high gain at low frequencies [15], [17]. Thistype of solution enables low distortion and high bandwidth, butrequires a high-order filters with poles and zeroes at low fre-quencies. In recent years, the majority of research works haveattempted to solve this problem by means of active filters [16],[19]–[26]. While these works differ in details, the main idea isto connect the energy storage elements to the bus through anadditional converter that regulates the bus voltage, a topologythat can be viewed as a three-port converter [16]. This approachsolves the problem by essentially eliminating the ripple at thebus voltage, while using a minimal bus capacitor. However,it requires additional hardware, which affects both cost andefficiency.

This paper explains the tradeoff between bandwidth and har-monic distortion in the bus voltage loop, and provides a newcontrol method for regulating the bus voltage, a method that issimple, low cost, and does not require additional hardware. Theproposed controller uses a digital finite impulse response (FIR)filter that samples the bus voltage at a slow sampling rate thatis an integer multiple of the ac line second harmonic frequency.This digital filter achieves what a simple analog feedback can-not; it extracts the low-frequency components of the bus voltagesignal, measuring the average bus voltage, while effectively fil-tering the noise of the second harmonic ripple. The digital filterthus combines three properties that are desired in this applica-tion: it operates at a very low sampling frequency and, thus, itis potentially low cost, it attenuates the second harmonic ripplewell, and eliminates the distortion due to a notch in its transferfunction, and it is quick enough to obtain highly stable dynamicresponse that maintains the bus voltage well regulated duringtransients.

The paper continues as follows. Section II explains the rea-sons for distortion in the bus voltage loop, and explains thetradeoff between distortion and bandwidth. Section III intro-duces the digital controller and FIR filter, and shows how thiscontroller eliminates this tradeoff. Section IV develops a dy-namic model of the bus voltage loop and introduces methodsfor designing an optimized loop compensator. Section V de-scribes tests with an experimental inverter prototype. Section VIsummarizes key conclusions.

Fig. 2. Basic bus voltage feedback loop. The amplitude of the output currentis controlled so that the average power flowing into the capacitor is zero, andthe average bus voltage is constant.

II. TRADEOFF BETWEEN BUS CAPACITANCE, BANDWIDTH

AND DISTORTION

This section presents the tradeoff between bandwidth andharmonic distortion in the bus voltage loop. It is explained howthe loop creates harmonic distortion, and how this distortionis affected by the loop bandwidth. Then, it is shown how theseparameters, distortion and bandwidth, are controlled by the loopgain, and why finding a good balance between them is morechallenging when the bus capacitor is small and the second-harmonic ripple is high.

A basic feedback loop that regulates the bus voltage is shownin Fig. 2. It generates a sinusoidal output current iac(t) synchro-nized to the output voltage. This synchronization is done by aphased-locked loop (PLL) that tracks the phase of the outputvoltage. The loop senses the bus voltage vbus(t) and controlsit by adjusting the current amplitude iac,pk(t). When the busvoltage is high, this amplitude is increased, which causes theaverage output power to increase, and the bus capacitor to dis-charge. This process is reversed when the bus voltage is low.This negative feedback equalizes the average output power tothe input PV power, and maintains the average bus voltage at adesired set point Vbus,avg .

In the discussion that follows, it is assumed that the powerstages are ideal, and a focus is given to the fundamental oper-ation of the feedback loop. Harmonic distortion in the currentiac(t) is created when the second harmonic ripple is not suffi-ciently filtered by the loop compensator, and this second har-monic frequency modulates the output current, which is given bythe following equation:

iac(t) = iac,pk(t) · sin(ωact). (1)

To achieve zero distortion, the current iac(t) should consistsof only the fundamental harmonic component ωac , which im-plies that the amplitude iac,pk(t) must be constant. If it is notconstant, because it includes the harmonic component at 2ωac ,distortion is created. A computation of the harmonic distortionin the output current is shown next. The bus voltage and its sec-ond harmonic ripple are computed by the balance of input andoutput powers in the inverter, and may be approximated by the


following expression, given in [20] and [21]:

vbus(t) ≈ Vbus,avg +Ppv

2ωacVbus,avgCbussin(2ωact) (2)

where Vbus,avg is the average bus voltage, Ppv is the inputpower, and Cbus is the bus capacitance. The amplitude of currentiac,pk(t) is given in steady state by

iac,pk (t) = average amplitude + (compensator gain at 2ωac)

· (ripple at 2ωac)

iac,pk(t) = Iac,pk + |H (j · 2ωac)|

· Ppv

2ωacVbus,avgCbussin(2ωact). (3)

By few trigonometric identities and by expressing the averageamplitude Iac,pk using the line voltage and output power, theoutput current is expressed by

iac(t) =

⎛⎝

√(2Ppv

Vac,pk

)2

+(

Ppv |H (j · 2ωac)|4ωacVbus,avgCbus

)2⎞⎠

sin (ωact + ϕ) +Ppv |H (j · 2ωac)|4ωacVbus,avgCbus

cos (3ωact) (4)

where |H(j2ωac)| is the gain of the loop compensator at the sec-ond harmonic frequency 2ωac , and Vac,pk is the ac line voltageamplitude. In addition to the fundamental harmonic compo-nent, the current also includes a harmonic component at 3ωacthat causes distortion. The THD of this signal is therefore

THD in iac(t) =Ppv |H (j · 2ωac)|4ωacVbus,avgCbus

·((

2Ppv

Vac,pk

)2

+(

Ppv |H (j · 2ωac)|4ωacVbus,avgCbus

)2)−0.5

(5)

which may be approximated by its first-order Taylor series, inrespect to its nominator

THD in iac(t) ≈(

Vac,pk

8ωacVbus,avg

)· |H (j · 2ωac)|

Cbus. (6)

This last expression approximates the THD in the outputcurrent iac(t). This approximation is accurate for low THDvalues, typically lower than 20%. According to this expression,the THD is proportional to the gain of the compensator at 2ωacand inversely proportional to the bus capacitance Cbus . With alow gain or a high bus capacitance, there is less distortion in theline current so one approach to obtain low distortion is to reducethe loop gain.

However, a low gain may lead to poor transient response or toinstability, two properties that are affected by one main param-eter, the loop bandwidth. As an example, consider a scenario inwhich the loop bandwidth is low, and there is a step in the inputpower ppv(t). Following this step, the input power is higher thanthe average output power, the bus capacitor charges, and its volt-age gradually increases. If the loop is designed with low gain

and low bandwidth, it will respond to this change slowly, result-ing in a bus voltage transient that may exceed the componentratings.

Therefore, the loop presents a tradeoff between harmonic dis-tortion and bandwidth, a tradeoff that is controlled by the loopgain. To reduce the harmonic distortion, the compensator gain at2ωac should be low, however to obtain sufficient regulation of thebus voltage this gain should be high. An example for this tradeoffis shown in Fig. 3, in which these two main parameters, the har-monic distortion in the output current and transient response inthe bus voltage are tested in simulation. The simulation assumeslossless power stages, and is done with the following parame-ters: Ppv = 150 W, Vac = 220 V rms, 60 Hz, Cbus = 20 μF,Vbus,avg = 425 V. The compensator H(s) includes an integrator,and a zero at 100.9 rad/s, which is required for stability. Thetransient response is tested with a step change in the input powerppv(t) from 150 to 300 W. Results are shown for three gainsof the compensator at the second harmonic frequency 120 Hz,where the gain is defined as |H(j2ωac)|.

With a low compensator gain of −60 dB, the output currentis nearly a pure sinusoid with low distortion, but the transient inthe bus voltage is unacceptably high. The opposite occurs with ahigh gain of −30 dB, for which the bus voltage is well regulatedduring the transient, but the distortion is high. Thus, with thesimple loop compensator used in this example, the tradeoffbetween bandwidth and distortion seems unsolvable, and thedesigner must use a larger bus capacitor to make the loop work.To design this loop with the small capacitor of this example(20 μF), a more sophisticated loop compensator is required.Such compensator is presented in the following section.

III. DIGITAL BUS VOLTAGE CONTROLLER AND FIR FILTER

This section introduces the proposed digital controller, a sim-ple and efficient method for regulating the bus voltage in thepresence of high second harmonic ripple. This loop is basedon a digital FIR filter that accurately measures the average busvoltage but rejects the second harmonic ripple, enabling a closedloop that provides both high bandwidth and low distortion.

Section II presents two desired properties of the bus voltageloop: it should have high gain at low frequencies, to providesufficient bandwidth, and low gain at the second harmonic fre-quency 2ωac , to reduce the distortion. Section II also explainshow balancing these opposing constraints with a simple loopcompensator is challenging, especially when the bus capacitanceis low. A possible solution is to design a loop compensator thatincludes a low-pass filter with a sharp cutoff at 2ωac , a low-passwith unity gain at low frequencies that enables high bandwidth,and zero gain at the second harmonic frequency that eliminatesthe distortion. One approach for designing such ideal low passis to approximate it with an analog filter. Such an analog filter,however, may be complex and expensive, because it probablyincludes several stages and operates at frequencies well below120 Hz.

Instead of a complex multistage filter, this study proposes adifferent approach, in which the desired filter is implemented bya digital FIR filter that samples the bus voltage at a slow sampling


Fig. 3. Tradeoff between distortion and transient response (bandwidth). Results are shown for three gains of the loop compensator H(s) at the second harmonicfrequency 120 Hz. Low gain leads to poor transient response due to low bandwidth, while a higher gain causes high distortion in the output current.

Fig. 4. Bus voltage is filtered by a digital FIR filter with a sampling rate thatis an integer multiple of the second harmonic frequency (at 120 Hz). Above:Samples in the time domain. Below: The equivalent gain in the frequencydomain.

rate. The FIR filter implements a transfer function with unitygain at low frequencies, and a notch at the second harmonicfrequency, a gain profile that approximates the required ideallow-pass filter. This gain profile is created by the samplingrate of the filter, which is chosen to be an integer multipleof the second harmonic ripple. Such sampling rate is high incomparison to low-frequency components of the bus voltage,and so these components pass with a gain of unity. However,this sampling rate causes the second harmonic component to beremoved by the FIR filter, so the second harmonic componenthas a gain of zero and is rejected.

The operation of the FIR filter is demonstrated in Fig. 4.The filter is designed with equal coefficients [1/N . . . 1/N ], asfollows:

HFIR (z) =1N

+1N

z−1 + · · · + 1N

z−(N −1) (7)

where N is the length of the filter, and is the ratio of the samplingrate and the second harmonic frequency. For example, with asecond harmonic at 120 Hz, a typical sampling rate is 480 Hz,for which the length of the FIR filter is N = 4, and the filtercoefficients are [1/4, 1/4, 1/4, 1/4]. Such FIR filter samples thebus voltage four times at every half line cycle and averages thesesamples. Because the number of samples in each cycle is aninteger number, the average of every four consecutive samplesis exactly the average bus voltage. In the frequency domain, thisaveraging process is manifested as unity gain at low frequencies,and a notch at the second harmonic frequency 2ωac , a gainprofile that approximates the required ideal low-pass filter. Inthe time domain, the FIR filter accurately extracts the averagebus voltage, while completely rejecting the ripple component,providing a clean feedback signal to the loop compensator.

A digital feedback loop that includes this FIR filter is shownin Fig. 5. The loop uses the FIR filter to extract the average busvoltage without ripple and, thus, can drive the output currentquickly and with zero distortion. The objective of the feedbackloop, as in the basic loop in Fig. 2, is to control the amplitude ofthe output current to maintain a balance of powers on the bus ca-pacitor, thus regulating the average bus voltage. The bus voltageis sampled and compared to a desired set point, producing thesampled error signal err[n], a signal that is filtered by the FIRfilter and drives the loop compensator Hd(z). The compensatorgenerates the digital amplitude signal iac,pk [n], which is multi-plied with a reference signal from the PLL to produce the outputcurrent signal. The major difference of this loop, in comparisonto the basic feedback loop in Fig. 2, is that the compensatorprocesses a filtered error signal to close the loop, and this signalthat does not include the ripple. As a result, the amplitude sig-nal iac,pk [n] holds only low-frequency components, with zero


Fig. 5. Digital bus voltage controller. The FIR filter removes the secondharmonic ripple, providing a clean feedback signal that drives the output currentwith high bandwidth and zero distortion.

second harmonic ripple, and does not create distortion in theoutput current.

The following analysis develops the equivalent transfer func-tion H(s), which is the continuous-time equivalent of the digitalcompensator and the FIR filter. This transfer function definesthe relationship between the error signal err(t) and the outputcurrent amplitude iac,pk(t)

H (s) =iac,pk (s)err (s)

err (t) = vbus (t) − Vref , iac (t) = iac,pk (t) · sin (ωact) . (8)

The sampled signal err[n] is

err[n] = KA/D · err (nTs) . (9)

The reconstructed iac,pk(t) signal is given by

iac (t) = KD/A

(∑n

iac,pk [n]·r (t − nTs)

)· sin (ωact)

⇒ iac,pk (t) = KD/A

∑n

iac,pk [n]·r (t − nTs) (10)

where KA/D and KD/A are gains (see Table I), Ts is the sam-pling time, and r(t) is the zero order hold reconstruction signal,defined as

r (t − nTs) =

{1, for nTs ≤ t < (n + 1) Ts

0, otherwise

}. (11)

In (10), the sampled sine wave at the PLL output is approxi-mated as a continuous signal, because the sampling rate of thePLL is much faster than the sampling frequency of the compen-sator. The sampling and reconstruction theorem is used to obtainthe relation between the transforms of the continuous time andsampled signals

err (s) =Ts

KA/Derr (z)|z=exp(sTs )

iac,pk (s) = KD/A · 1 − e−Ts ·s

s· iac,pk (z)|z=exp(sTs ) . (12)

TABLE IPARAMETERS OF THE INVERTER PROTOTYPE

PV panel peak power = 300 W, Vm p p = 37.5 V, Im p p = 8 AAC line voltage Va c , p k =

√2·220 V, ωa c = 2π ·60 rad/sec

Bus capacitor Cb u s = 20 μF, 700 V, Film capacitor (WIMA)Bus capacitorvoltage

Vb u s , av g = 425V , overvoltage protection = 500 V, undervoltage protection = 375 V

DCX stage switching frequency = 80 kHz, input cap: Cpv = 37 μF,output cap: CD C X = 2 μF, Cb lo ck = 37 μF,

L t a n k = 400 nHDCX transformerdesign

Turns ratio: 6:56, magnetic core: PQ35/35, Primarywinding: 6 turns Litz #44 1000 strands, Secondary winding:

56 turns Litz #46 270 strandsBoost power stage Lb o o s t = 550 μH 2.5 A, PQ20/20, variable frequency

peak current control with Ip k = 2.2 A, switchingfrequency 6– 87 kHz

Buck power stage Lb u ck = 360 μH 4.3 A, PQ26/20, output cap = 1.3 μF,variable frequency peak current control with Ip k = 4.0 A,

max switching frequency 85 kHzEMI filter Two EMI inductors—500 μH, 2 A (each)Microprocessor Atmel ATTINY84 A, 20 MHz, 8 bitBus voltage A/D Sample rate = 1/T s = 480 Hz, Resolution: 8 bit (3.0 V),

amplifier (scaling): VA / D = (Vb u s − 346.7)/57.03,gain: KA / D = (1/57.03) · 28 /3.0

output current D/A The uP PWM channel is used as low cost D/A PWMresolution: 8 bits, gain: KD / A = (1/28 ) · 1.866

FIR filter Sample rate = 1/T s = 480 Hz, Length: N = 4 samplesy [n ] = (1/4) · (err[n ] + err[n − 1] + err[n − 2] +

err[n − 3])Nominal digitalcompensator

sample rate = 1/T s = 480 Hz, software gains: a = 1,b = 8, g = 1/16

PLL block sample rate = 1/TP L L = 61.44 kHz (512 samples perhalf line cycle), sine-wave look-up table = 8 bits

The bandwidth of err(s) is assumed much smaller than thesampling frequency 1/Ts , and so aliasing bands in the signalerr(s) are neglected. By dividing the equations, and substitutingthe compensator and FIR filter transfer functions for the ratioiac,pk(z)/err(z), the following transfer function is obtained:

H (s) =iac,pk (s)err (s)

= KA/D KD/A ·(

1 − e−Ts ·s

Ts · s

)

HFIR (z)Hd (z)|z=exp(sTs ) (13)

where Hd(z) is the z-transform of the digital compensator,and HFIR(z) is the z-transform of the FIR filter. This expres-sion defines the equivalent continuous-time transfer compen-sator of the digital loop. The FIR filter has N equal coefficients[1/N . . . 1/N ], where N is the filter length, so its transfer func-tion HFIR(z) is

y[n] =1N

N −1∑k=0

err[n − k] ⇔ HFIR (z) =1N

(N −1∑k=0

z−k

).

(14)According the result of (13), the equivalent continuous-time

gain of this filter is obtained by the transformation z = exp(sTs)

HFIR(jω) = HFIR(s) =1N

(N −1∑k=0

e−jωTs k

)

=1N

1 − e−jωTs N

1 − e−jωTs. (15)


The sampling rate 1/Ts is chosen to be an integer multiple ofthe second harmonic ripple

1Ts

= N · 2fac = N · ωac

π. (16)

This results in the following transfer function of the FIR filter:

HFIR (jω) =1N

1 − e−jπω/ωa c

1 − e−jπω/(N ωa c ) . (17)

The gain of this transfer function is plotted in Fig. 4, forN = 3 and N = 4. Using this result, the compensator transferfunction H(s) in (13) exhibits two desired properties

ω = 2ωac ⇒ H(s) = 0

ω → 0 ⇒ H(s) = KA/D KD/A · Hd(z)|z=exp(sTs ) . (18)

These equations describe the key advantage of the digital con-troller and FIR filter. The fundamental harmonic of the rippleat the 2ωac is rejected by the filter, and so this frequency doesnot create distortion on the ac line. Higher harmonics of theripple (at 4ωac , 6ωac . . .) are rejected as well. However, at lowfrequencies, the FIR filter exhibits a gain of unity, and the com-pensator is governed at these frequencies by the digital transferfunction Hd(z), which can be designed with high gain and highbandwidth.

IV. SYSTEM DYNAMICS AND STABILITY ANALYSIS USING

AVERAGE SIGNALS

The objective in this section is to develop a dynamic modelof the system, a model that is linear and time invariant and,therefore, enables evaluation of dynamic phenomena, such asstability and transients. This model also provides a frameworkfor designing a suitable loop compensator.

A main challenge toward a linear model is that the bus voltageloop is not linear and not time invariant, because several key sig-nals include harmonic components that are synchronized to theac line. For example, the output current is generated by a mul-tiplication of the amplitude signal with a reference sinusoidalsignal, an operator that is not time invariant and is modeledby convolution in the frequency domain. Another challengeemerges from the dynamics in the bus capacitor voltage, whichare governed by the output power, a signal that is generated bythe multiplication of the sinusoidal output current and voltage.Due to these nonlinear operators, a direct analysis of the loopleads to a dynamic model that is highly complex and inefficient.To overcome such complexities, a simpler approach is to modelthe interactions between signals that are averaged over half aline cycle [27]. This approach is useful because it leads to asimple model that predicts the major dynamic phenomena inthe system.

Several key signals in the bus voltage loop may be expressedas a sum of a slowly changing average signals, and a har-monic component at 2ωac . For example, a typical spectrumof the bus voltage vbus(t) is shown in Fig. 6. It includes low-frequency components, which correspond to the slowly chang-ing average voltage, and a second harmonic component at 2ωac ,which describes the ripple. The second harmonic component is

Fig. 6. Spectrum of the bus voltage signal, showing the low-frequency com-ponents and the second harmonic ripple.

determined by the balance of input and output powers, so thiscomponent is known and nearly constant. However, the low-frequency components are determined by the loop dynamicsand, therefore, it is those components that describe the mostinteresting dynamics of the signal.

An advantage of the averaged signals approach is that it leadsto a dynamic model that is linear and time invariant. Because theaveraged signals do not contain second harmonic components,they interact through operators that may be approximated aslinear and time invariant and, thus, lead to a suitable linearmodel. This model is developed in the following analysis.

Average signals are defined by averaging instantaneous sig-nals over half of a line cycle

〈vbus (t)〉 =

t+ π2 ω a c∫

t− π2 ω a c

vbus (τ)dτ, 〈pac (t)〉=t+ π

2 ω a c∫

t− π2 /ωac

pac (τ)dτ

〈err (t)〉 =

t+ π2 ω a c∫

t− π2 ω a c

err (τ)dτ = 〈vbus (t)〉 − Vbus,avg ,

〈iac,pk (t)〉 =

t+ π2 ω a c∫

t− π2 ω a c

iac,pk (τ)dτ. (19)

The instantaneous output power is as follows:

pac (t) = vac (t) iac (t)

= (Vac,pk sin (ωact)) (iac,pk (t) sin (ωact))

=12Vac,pkiac,pk (t) − 1

2Vac,pkiac,pk (t) cos (2ωact) .

(20)

By integrating the above equation, the average output poweris obtained

〈pac (t)〉 =12Vac,pk

⎛⎜⎝

t+ π2 ω a c∫

t− π2 ω a c

iac,pk (τ) dτ−t+ π

2 ω a c∫

t− π2 ω a c

iac,pk (τ) cos (2ωacτ)dτ

⎞⎟⎠ . (21)


The FIR filter has zero gain at ω = 2ωac , and so the signaliac,pk(t) contains no harmonic component at that frequency. Asa result, the signals iac,pk(t) and cos(2ωact) are orthogonal, andthe right-side integral in (21) is zero. The average output poweris therefore

〈pac (t)〉 =12Vac,pk 〈iac,pk (t)〉 . (22)

This result demonstrates that although the instantaneous sig-nals are related by complex nonlinear operators, the averagesignals are related by linear operators. In (22), this linear op-erator is a simple constant gain. The relationship between theaveraged output power and bus voltage is considered next. Theinstantaneous bus voltage is determined by integrating the buscapacitor current

vbus (t) =1

Cbus

t∫

−∞

Ppv − pac (τ)vbus (τ)

dτ. (23)

The averaged bus voltage is defined by

〈vbus (t)〉 =1

Cbus

t+ π2 ω a c∫

t− π2 ω a c

τ∫

−∞

Ppv − pac(α)vbus(α)

dαdτ. (24)

On exchanging the order of integration in this last equation

〈vbus (t)〉 =1

Cbus

t∫

−∞

τ + π2 ω a c∫

τ− π2 ω a c

Ppv − pac(α)vbus(α)

dτdα. (25)

Next, it is assumed that the ripple in the bus voltage is muchsmaller than the average bus voltage:

vbus (t) = Vbus,avg + ripple (t) , ripple (t) << Vbus,avg

⇒ 1vbus (t)

≈ 1Vbus,avg

. (26)

This approximation is justified in practical designs, becausethe average bus voltage is typically hundreds of volts, while theripple is tens of volts in the worst case. This approximation leadsto the following expression:

〈vbus (t)〉 ≈ 1Cbus

t∫

−∞

τ + π2 /ωac∫

τ− π2 /ωac

Ppv − pac (α)Vbus,avg

dαdτ

=1

CbusVbus,avg

t∫

−∞

(Ppv − 〈pac (τ)〉) dτ. (27)

Last, the relationship between the error signal and the out-put current amplitude is developed. These average signals aredefined in (19) by integration over a finite time period, an opera-tion that can be modeled in the time domain by convolution witha rectangular pulse. Following this representation, the Laplacetransforms of the averaged signals are as follows:

L{〈err (t)〉} (s) =2 sinh

(π

2ωac · s)

s· err (s) ,

L{〈iac,pk (t)〉} (s) =2 sinh

(π

2ωac · s)

s· iac,pk (s) . (28)

Fig. 7. Dynamics of the bus voltage loop, in terms of average signals.

A division of these expressions results in

L{〈iac,pk (t)〉} (s)L{〈err (t)〉} (s)

=iac,pk (s)err (s)

. (29)

Equation (8) leads to the following ratio:


= H (s) . (30)

To conclude, the dynamic equations of the system are asfollows:

〈pac (t)〉 =12Vac,pk 〈iac,pk (t)〉

〈vbus (t)〉 ≈ 1CbusVbus,avg

t∫

−∞

(Ppv − 〈pac (τ)〉) dτ


= H (s) . (31)

These dynamic equations are summarized by the averagesignal model shown in Fig. 7. This model describes the loopdynamics in terms of average signals, and is linear and timeinvariant, but is valid only at low frequencies, which are suffi-ciently smaller than the second harmonic frequency 2ωac .

An immediate result that emerges from this model is thesystem open-loop transfer function T(s)

T (s) =(

Vac,pk

2CbusVbus,avg

)1sH (s)

H (s) = KA/D KD/A ·(

1 − e−Ts ·s

Ts · s

)

HFIR (z) Hd (z)|z=exp(sTs ) . (32)

This function may be evaluated at low frequencies (Ts · |s| =1), by using the following approximations:

for Ts · |s| << 1:(

1 − e−Ts ·s

Ts · s

)≈ 1, HFIR (s)

=1N

1 − e−sTs N

1 − e−sTs≈ 1. (33)


Fig. 8. Experimental microinverter power topology. The step-up stage is implemented with a DCX, cascaded to a boost converter, and the step-down inverterstage is implemented with a buck inverter and an unfolder circuit.

These approximations lead to simplified open-loop transferfunction for Ts · |s| � 1

T (s) ≈(

KA/D KD/AVac,pk

2CbusVbus,avg

)

︸︷︷︸constant

·1s· Hd (z)|

z= 1 + (T s / 2 ) s1−(T s / 2 ) s

. (34)

In (34), the sampled system is mapped to continuous time us-ing the bilinear transformation. This leads to a transfer functionthat is defined by rational polynomials in s, which enables designof the loop compensator in continuous time before evaluatingthe exact open-loop transfer functions in (32).

V. EXPERIMENTAL RESULTS WITH

A MICROINVERTER PROTOTYPE

The proposed digital feedback loop was tested on a microin-verter prototype whose power topology is shown in Fig. 8. Themicroinverter is based on a two-stage topology, and includes astep-up stage, which boosts the input PV voltage to the highvoltage on the bus capacitor, and a step-down inverter stage,which generates the output ac line current. The prototype is de-signed for a 300-W PV panel. It interfaces to an output voltage of220-V rms and a 60-Hz frequency. The bus voltage is regulatedto 425 V. The bus capacitor is 20 μF and is rated at 700 V. Withthis small bus capacitor, the amplitude of the second harmonicripple is 93 V peak-to-peak at full power. At nominal voltageand 75% power, the efficiency of the inverter system is 95.8%.A summary of the design parameters is shown in Table I.

A primary function of the step-up stage is to boost the voltageefficiently, while maintaining the input voltage constant at thePV panel MPP. Because the input PV voltage is constant, andthe voltage on the bus capacitor is fluctuating, the voltage gainof the step-up stage is continuously varying. To implement anefficient power stage with variable gain, the step up stage is com-posed of two cascaded converters: a “DC transformer” (DCX),and a cascaded boost. The DCX is highly efficient (∼98.0%),but operates with a constant gain, equal to the voltage gain ofthe transformer. Variations in the step-up gain are achieved by

controlling the boost converter PWM signal. This is done by theinput voltage controller, a feedback loop that consists of the op-erational amplifier and PWM generator shown at the bottom ofFig. 8. The boost operates with a constant peak inductor currentand a variable switching frequency. Its control loop senses theinput voltage on the PV panel and controls the boost switchingfrequency, which is increased to reduce the input voltage, anddecreased to increase the input voltage. Due to this control, theinput voltage is maintained constant. Because the peak currentin the boost inductor is constant and low, and because switch-ing losses decrease at low powers, the boost converter remainshighly efficient at varying power levels.

The objective of the step-down inverter stage is to generatethe output current iac(t). This stage consists of a buck con-verter and an unfolder circuit. The buck converter generates arectified sine-wave output current that is synchronized to theac line. It is controlled with constant peak current and variablefrequency, a control method that achieves high efficiency (99.1%at 225 W). The unfolder circuit controls the polarity of the cur-rent, converting the rectified sine-wave current to a full sinewave at the output. This is accomplished by a bridge topology,implemented with BJT switching devices that switches whenthe ac line voltage crosses zero. The inverter stage is controlledby a cycle-by-cycle controller, which bandwidth is higher than10 kHz. In comparison, the bandwidth of the bus voltage loopis less than 10 Hz. This justifies ideal inverter model that isassumed in the analysis of the loop dynamics.

A block diagram of the software that implements the digitalloop is shown in Fig. 9. An important objective of the proto-type was to achieve a low cost design, and so the software wascoded on an 8-bit microprocessor (ATTINY84), which includesonly basic arithmetic functions. The code composes of threemain blocks. The “fast block” executes at a rate of 61.44 kHz,and contains the PLL and the multiplier. The “slow block” ex-ecutes at a rate of 480 Hz, and contains the FIR filter andthe digital loop compensator. The FIR filter averages its lastfour consecutive samples, and so have four equal coefficients[1/4, 1/4, 1/4, 1/4]. The compensator Hd(z) is implementedas an IIR filter having the structure shown in Fig. 9. It usesthree gain variables, a, b, and g, and is described by the transfer


Fig. 9. Block diagram of the inverter software, implementing the digital bus voltage loop.

Fig. 10. Dynamics of a stable compensator (left), with phase margin of +55°, and unstable compensator (right), with phase margin of −2.3°. In the scopeimages: vpv is the input PV voltage, iac is the (rectified) output ac, vbus is the bus capacitor voltage, and vref is the current reference signal that is generated bythe control loop.

function in (35). These three gains may be tuned to optimize theloop stability, bandwidth, and transient response. The digitalcompensator in the inverter prototype is

Hd (z) = g(a + b) − bz−1

1 − z−1 . (35)

where the gains a, b, and g are shown in Fig. 9.The “very slow block” executes at a rate of 2 Hz, and imple-

ments the maximum power point tracking (MPPT, [28], [29])algorithm. This block attempts to maximize the output cur-rent, by controlling the input voltage on the PV. It relies onthe correlation between the ac amplitude and the average out-put power, assuming that the average output power is highestwhen the current amplitude is highest. The MPPT accepts theamplitude signal as an input, and uses this signal to estimate theaverage output power, using (22). At its output, the MPPT con-

trols the input voltage by varying the reference signal to theinput voltage loop (see Fig. 8). It constantly perturbs the in-put voltage, searching for the value that maximizes the currentamplitude. By this mechanism, the MPPT avoids sampling theinput voltage and current, and eliminates the need for additionalsensors. It should be noted that when the line voltage ampli-tude varies in time, the proposed MPPT algorithm might not beaccurate.

Two designs, one stable and one unstable are shown in Fig. 10.The difference between the two is the set of gains a, b, and gin the loop compensator (see Fig. 9). For each set of gains,the phase margin of the loop is evaluated using the open-looptransfer function in (32). The stable design has a positive phasemargin of +55°, in which case, the average bus voltage is wellregulated and constant, and the current reference signal hasconstant amplitude and zero distortion. The unstable design has


Fig. 11. Transient response for a step in input power. The signal vset controls the input power and marks the step, vbus is the bus capacitor voltage, and vref isthe current reference signal that is generated by the control loop.

a negative phase margin of −2.3°, which results in an oscillatingbus voltage. These oscillations can be viewed as oscillations inthe bus voltage average. In both tests, the input voltage from thePV panel is maintained constant by the input voltage loop. Thetests in Fig. 10, were done under the following conditions: Inthe stable design, the set of gains is a = 1, b = 32, g = 1/256, andthe operating point of the test is Vpv = 36.8 V, Ipv = 2.82 A,Vac = 220 V rms, Iac = 0.454 A rms. In the unstable design,the set of gains is a = 1, b = 1, g = 1/64, and the operatingpoint of the test is Vpv = 36.8 V, Ipv = 4.9 A, Vac = 220 Vrms, Iac = 0.777 A rms.

Two transient response tests are shown in Fig. 11. This ex-periment tests the transient in the bus voltage during a step ininput power. Prior to the switch in input power, the bus voltageis regulated to its nominal value of 425 V. With a positive step,the bus capacitor charges and the average bus voltage increasesfor a short period, because the input power, immediately afterthe step, is higher than the average output power. The bus volt-age loop senses this deviation and increases the amplitude ofthe output current, as shown by the signal vref in Fig. 11. Thiscorrection returns the average bus voltage to its nominal value.In these tests, a constant voltage power supply is connected atthe input, and the boost converter is operated in open loop. Thestep in input power is done by manually shifting the frequencyof the boost PWM signal. The compensator gains in this testsare a = 1, b = 8, g = 1/16. The input voltage is 37.0 V in bothtests. The input power is switched from 164 to 124 W for anegative step, and from 124 to 164 W for a positive step. Theresponse of the system to a transient in the ac line voltage isshown in Fig. 12. The parameters in this test are the nominalsystem parameters, as given in Table I. Prior to the step, the busvoltage is regulated to 425 V. Then, the ac voltage is steppedfrom 220 to 240 V rms, and the corresponding response in acand bus voltage are shown.

Table II shows a comparison of two loop designs, one thatuses the proposed digital controller, and one that uses a standardanalog compensator. Both designs meet similar specificationsof distortion and transient response, and the major differencebetween them is the bus capacitance, which is higher with theanalog design. The digital loop uses the nominal values shown inTable I. The analog loop design is tested in simulation, using thefollowing transfer function: H(s) = 0.08(1 + s/31.4)/s. Thistransfer function includes a zero to stabilize the loop, and has a

Fig. 12. Loop response to a step in the ac line voltage.

TABLE IICOMPARISON OF THE DIGITAL AND ANALOG LOOP COMPENSATORS

Digital compensator Analog compensator(experimental results) (simulation results)

AC line 220 V rms, 60 HzPV panel 300 W peakaverage bus voltage 425 Vbus voltage limits with a150–200-W input step

min: 350 V, max: 500 V

THD in ac line current 0.17% @ 150 W 1.0% @ 150 WBandwidth 4.6 Hz 3.7 HzBus capacitor 20 μF 60 μF

gain of−51.9 dB at 120 Hz, to reject the second harmonic ripple.The two designs comply with the following specifications:

1) THD in steady state does not exceed 1%, for an inputpower of 150 W;

2) the bus voltage does not exceed 500 V when the inputpower steps from 150 to 200 W;

3) the bus voltage does not go below 350 V when the inputpower steps from 200 to 150 W.

The main conclusion from the comparison in Table II is thatthe analog compensator requires a bus capacitance that is threetimes larger. The digital compensator operates with essentiallyzero distortion, and can work well with a 20-μF capacitor, while


the analog compensator causes a 1% distortion and requires a60-μF capacitor.

Comments on Table II: Results for the digital compensatorare experimental results, measured on the nominal setup thatis described in Table I. The THD of the digital compensator isobtained by a Hall-effect current sensor and an FFT analyzeron the ac line. It should be noted that that the experimentalvalue of THD = 0.17% results mainly from measurement noise,and is not a result of the loop dynamics, because the digitalsignal iac,pk [n] remains strictly constant during the test. Thebandwidth is evaluated from the open-loop transfer function in(32), where H(s) is the transfer function of either the digital oranalog compensators.

VI. CONCLUSION

In PV microinverters, a major challenge that one encounterswhen designing the bus voltage loop is the tradeoff betweendistortion and bandwidth, and the bus capacitor size, a tradeoffthat is difficult and even impossible to solve when the bus capac-itor is small and the second harmonic ripple is high. This paperanalyzes this tradeoff, providing expressions for the harmonicdistortion, and evaluating the loop dynamics. A conclusion ofthis analysis is that both the distortion and the bandwidth areaffected by one main parameter, the loop gain. To eliminate thistradeoff, this paper proposes a digital controller that operateswith low distortion and high bandwidth simultaneously. Insteadof reducing the distortion by lowering the loop gain or employ-ing additional hardware for mitigating the ripple, the digitalcontroller uses a FIR filter that samples the bus voltage at a ratethat is an integer multiple of the second harmonic frequency, andpresents a notch that removes the second harmonic ripple. Thisenables a simple and low cost design, a design that has highbandwidth, causes negligible distortion in the ac line current,can be implemented with an inexpensive microcontroller, andoperates well with a small bus capacitor.

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Yoash Levron (M’14) received the M.Sc. and Ph.D.degrees in electrical engineering from the Universityof Tel-Aviv, Tel Aviv-Yafo, Israel.

Since 2014, he has been an Assistant Professor atthe Electrical Engineering Faculty, Technion, Haifa,Israel. His current research interests include sensingand estimation in power networks, control of dis-tributed generation units and energy storage devices,signal processing and pattern recognition in powersystems, and power conversion for photovoltaics andfuel cells.

Sebastian Canaday received the B.S. degree inelectrical engineering from the Colorado School ofMines, Golden, CO, USA, in 1997.

Since 2014, he has been a Research Assistantat the University of Colorado, Boulder, CO. His re-search interests include power electronics for motionsystems and renewable energy systems.

Robert W. Erickson (S’82–M’82–SM’97–F’01) re-ceived the B.S., M.S., and Ph.D. degrees from the Cal-ifornia Institute of Technology, Pasadena, CA, USA,in 1978, 1980, and 1982, respectively.

He and Professor Maksimovic codirect the Col-orado Power Electronics Center. Since 1982, he hasbeen with the Faculty of the Electrical, Computer,and Energy Engineering Department, University ofColorado, Boulder, CO, USA, where he served asa Chair in 2002–2006 and 2014–2015. His researchinterests include electric vehicle power electronics

(charger and drive train power conversion), grid interface of solar and windpower systems, low harmonic rectification, resonant power conversion, andpower electronics modeling and control. He is a Fellow of the UC-B/NRELRenewable and Sustainable Energy Institute, and an Author of the textbookFundamentals of Power Electronics (New York, NY, USA: Springer, 2001).

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258 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, …rwe/references/LevBus2016.pdfple, while regulating the bus voltage efﬁciently during transients, and must therefore balance