25280_STMICROELECTRONICS_TDA9109SN

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TDA9109/SN

LOW-COST DEFLECTION PROCESSORFOR MULTISYNC MONITORS

June 1998

PRELIMINARY DATA

SHRINK32(Plastic Package)

ORDER CODE : TDA9109/SN

HORIZONTAL.SELF-ADAPTATIVE.DUALPLL CONCEPT.150kHz MAXIMUM FREQUENCY.X-RAY PROTECTION INPUT. I2C CONTROLS : H-POSITION, FREQUENCYGENERATORFORBURN-INMODE

VERTICAL.VERTICALRAMPGENERATOR.50 TO 185Hz AGC LOOP.GEOMETRYTRACKING WITH VPOS & VAMP. I2C CONTROLS :VAMP, VPOS, S-CORR, C-CORR.DC BREATHING COMPENSATION

I2C GEOMETRYCORRECTIONS.VERTICALPARABOLAGENERATOR(Pin Cushion - E/W, Keystone,Corner)

.HORIZONTAL DYNAMIC PHASE(SidePin Balance & Parallelogram).VERTICALDYNAMIC FOCUS(Vertical FocusAmplitude)GENERAL.SYNCPROCESSOR.12V SUPPLY VOLTAGE.8V REFERENCE VOLTAGE.HOR. & VERT. LOCK/UNLOCK OUTPUTS.READ/WRITE I2C INTERFACE.HORIZONTAL AND VERTICALMOIRE.B+ REGULATOR- INTERNAL PWM GENERATOR FOR B+CURRENT MODE STEP-UP CONVERTER- SOFT START

- I2C ADJUSTABLEB+REFERENCE VOLTAGE- OUTPUT PULSES SYNCHRONIZED ON

HORIZONTAL FREQUENCY- INTERNALMAXIMUMCURRENTLIMITATION.COMPARED WITH THE TDA9109,THE TDA9109/SNHAS :- CORNER CORRECTION,- HORIZONTAL MOIR,

- B+ SOFT START,- INCREASEDMAX.VERTICALFREQUENCY,- NO HORIZONTAL FOCUS,- NOSTEPDOWNOPTIONFORDC/DCCON-

VERTER,- NO I

2C FREE RUNNING ADJUSTMENT,- FIXED HORIZONTAL DUTY CYCLE(48%),

- INCREASED MAXIMUM STORAGE TIMEOF THE HORIZONTAL SCANNING TRAN-SISTOR.

DESCRIPTIONThe TDA9109/SN is a monolithic integrated circuitassembledin 32-pinshrinkdual in line plastic pack-age. This IC controls all the functionsrelated to thehorizontal and vertical deflection in multimode ormulti-frequencycomputerdisplaymonitors.Theinternalsyncprocessor,combinedwiththeverypowerful geometry correction block make theTDA9109/SN suitable for very high performancemonitors, using very few external components.Thehorizontaljitter levelis verylow. It is particularlywell suited for high-end 15 and 17 monitors.Combined with the ST7275 Microcontroller fam-ily, TDA9206 (Video preamplifier) and STV942x(On-Screen Display controller) the TDA9109/SNallows fully I2C bus controlled computer displaymonitors to be built with a reduced number ofexternal components.

This isadvance information on a new product now in developmentor undergoingevaluation. Detailsare subject to change withoutnotice.

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1

2

3

4

5

6

7

8

9

1011

12

13

14

15

16

2223

24

25

26

21

20

19

18

17

5V

SDA

SCL

VCC

GND

HOUT

XRAY

EWOUT

VOUTVCAP

VREF

VAGCCAP

VGND

BREATH

B+GNDISENSE

REGIN

COMP

HREF

HFLY

HGNDFOCUS-OUT

HMOIRE

HPOSITION

PLL1F

R0

C0

PLL2C

HLOCKOUT

H/HVIN

VSYNCIN

32

31

30

29

28

27

BOUT

9109SN01.EPS

PIN CONNECTIONS

TDA9109/SN

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QUICK REFERENCE DATA

Parameter Value UnitHorizontal Frequency 15 to 150 kHzAutosynch Frequency (for given R0 and C0) 1 to 4.5 f0 Horizontal Sync Polarity Input YESPolarity Detection (on both Horizontal and Vertical Sections) YESTTL Composite Sync YESLock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) YESI2C Control for H-Position 10 %XRAY Protection YESI2C Horizontal Duty Fixed 48 %I2C Free Running Frequency Adjustment NOStand-by Function YESDual Polarity H-Drive Outputs NOSupply Voltage Monitoring YESPLL1 Inhibition Possibility NOBlanking Outputs NOVertical Frequency 35 to 200 HzVertical Autosync (for 150nF on Pin 22 and 470nF on Pin 20) 50 to 185 HzVertical S-Correction YESVertical C-Correction YESVertical Amplitude Adjustment YESDC Breathing Control on Vertical Amplitude YESVertical Position Adjustment YESEast/West (E/W) Parabola Output (also known as Pin Cushion Output) YESE/W Correction Amplitude Adjustment YESKeystone Adjustment YESCorner Correction YESInternal Dynamic Horizontal Phase Control YESSide Pin Balance Amplitude Adjustment YESParallelogram Adjustment YESTracking of Geometric Corrections with Vertical Amplitude and Position YESReference Voltage (both on Horizontal and Vertical) YESVertical Dynamic Focus YESI2C Horizontal Dynamic Focus Amplitude Adjustment NOI2C Horizontal Dynamic Focus Symmetry Adjustment NO

I2C Vertical Dynamic Focus Amplitude Adjustment YESDetection of Input Sync Type YESVertical Moir Output YESHorizontal Moir Output YESI2C Controlled Moir Amplitude YESFrequency Generator for Burn-in YESFast I2C Read/Write 400 kHzB+ Regulation adjustable by I2C YESB+ Soft Start YES

9109SN02.TBL

TDA9109/SN

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VREF

4

13

12

11

5

3

1

6

7

26

2

HSYNC

HORIZONTAL

MOIRECANCEL

5BITS+ON/OFF

9HM

OIRE

HREF

HGND

SYNC

PROCESSOR

SYNCINPUT

SELECT

(1bit)

B+

CONTROLLER

LOCK/UNLOCK

IDENTIFICATION

PHASE

COMPARATOR

PHASE

SHIFTER

H-DUTY

(48%)

HOUT

BUFFER

VCOForced

Frequency

2bits

VAMP

7bits

21

22

23

3019

24

32 31 27

VREF

VGND 5V

SDA

SCL

GND

VREF

SANDC

CORRECTION

VER

TICAL

OSCILLATOR

RAMPGENERATOR

GEOMETRY

TRACKING

6bits

6bits

Keyst.

6bits

E/W

7bits

PLL1F

HLOCKOUT

HPOSITION

R0

C0

HFLY

PLL2C

HOUT

VCAP

VAGCCAP

VOUT

VSYNCIN

H/HVIN

EWOUT

X2 X

2529

XRAY

VCC

RESET

GENERATOR

I2CINTERFACE

VPOS

7bits

20

AMPVDF

6bits

10FO

CUS

Parallelogram

6bits

SpinBal

6bits

X2 X

VSYNC

SAFETY

PROCESSOR

XRAY

VCC

17BG

ND

16ISENSE

15RE

GIN

28B+OUT

14CO

MP

B+Adjust

7bits

18 BREATH

PHASE/FREQUENCY

COMPARATOR

H-PHASE(7bits)

8

VERTICAL

MOIRE

CANCEL

5

BITS+ON/OFF

5VCorner

7bits X4

TDA9109/SN

9109SN02.EPS

BLOCK DIAGRAM

TDA9109/SN

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HORIZONTAL SECTIONOperating Conditions

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VCOR0(Min.) Minimum Oscillator Resistor Pin 6 6 kC0(Min.) Minimum Oscillator Capacitor Pin 5 390 pFF(Max.) Maximum Oscillator Frequency 150 kHz

OUTPUT SECTIONI12m Maximum Input Peak Current Pin 12 5 mAHOI Horizontal Drive O utput Maximum Current Pin 26, Sunk current 30 mA

Electrical Characteristics (VCC =12V,Tamb = 25oC)Symbol Parameter Test Conditions Min. Typ. Max. Unit

SUPPLY AND REFERENCE VOLTAGESVCC Supply Voltage Pin 29 10.8 12 13.2 VVDD Supply Voltage Pin 32 4.5 5 5.5 VICC Supply Current Pin 29 50 mAIDD Supply Current Pin 32 5 mA

VREF-H Horizontal Reference Voltage Pin 13, I = -2mA 7.4 8 8.6 VVREF-V Vertical Reference Voltage Pin 21, I = -2mA 7.4 8 8.6 VIREF-H Max. Sourced Current on VREF-H Pin 13 5 mAIREF-V Max. Sourced Current on VREF-V Pin 21 5 mA

1st PLL SECTIONHpolT Delay Time for detecting polarity change

(see Note 3)Pin 1 0.75 ms

VVCO VCO Control Voltage (Pin 7) VREF-H= 8V f0fH(Max.)

1.36.2

VV

Vcog VCO Gain (Pin 7) R0 = 6.49k, C0 = 820pF,dF/dV = 1/11R0C0

17.1 kHz/V

Hph Horizontal Phase Adjustment(see Note 4) % of Horizontal Period 10 %

VbminVbtypVbmax

Horizontal PhaseSetting Value (Pin 8) (seeNote 4)MinimumValueTypical ValueMaximum Value

Sub-Address 01Byte x1111111Byte x1000000Byte x0000000

2.83.44.0

VVV

IPll1UIPll1L

PLL1 Filter Current Charge PLL1 is UnlockedPLL1 is Locked

140 1

AmA

f0 Free Running Frequency R0 = 6.49k, C0 = 820pF,f0 = 0.97/8R0C0

22.8 kHz

df0/dT Free Running Frequency Thermal Drift(No drift on external components) (see Note 5) -150 ppm/C

CR PLL1 Capture Range R0 = 6.49k, C0 = 820pF,from f0+0.5kHz to 4.5f0

fH(Min.)fH(Max.) 90

25 kHzkHz

FF Forced Frequency FF1 Byte 11xxxxxxFF2 Byte 10xxxxxx

Sub-Address 02 2f03f0

Notes : 3. This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync.4. See Figure 10 for explanation of reference phase.5. These parametersare not tested on each unit. They are measured during our internalqualification.6. This PLLcapture range maybe obtained only if f0 is captured(for instance bu adjustingR0). Ifnot , more margin must be provided

between fH (Min.) and f0, to cope with the components spread.

9109SN05.TBL

TDA9109/SN

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HORIZONTAL SECTION (continued)Electrical Characteristics (VCC =12V,Tamb = 25oC) (continued)


2nd PLL SECTION AND HORIZONTAL OUTPUT SECTIONFBth Flyback Input Threshold Voltage (Pin 12) 0.65 0.75 VHjit Horizontal Jitter At 31.4kHz 70 ppmHD Horizontal Drive Output Duty-Cycle

(Pin 26) (see Note 7)48 %

XRAYth X-RAY Protection Input T hreshold Voltage Pin 25, see Note 8 8 VVphi2 Internal Clamping Levels on 2nd PLL

Loop Filter (Pin 4)Low LevelHigh Level

1.64.0

VV

VSCinh Threshold Voltage to Stop H-Out,V-Out,B-Out and Reset XRAYwhen VCC < VSCinh (see Note 8)

Pin 29 7.5 V

VSDinh Threshold Voltage to Stop H-Out,V-Out,B-Out and Reset XRAYwhen VDD < VSDinh

Pin 32 4.0 V

HDvd Horizontal Drive Output(low level) Pin 26, IOUT= 30mA 0.4 VVERTICAL DYNAMIC FOCUS FUNCTION (positive parabola)

HDFDC Bottom DC Output Level RLOAD= 10k, Pin 10 2 VTDHDF DC Output Voltage Thermal Drift (see

Note 5)200 ppm/C

AMPVDF Vertical Dynamic Focus ParabolaAmplitude with VAMP and VPOS Typical

Min. Byte 000000Typ. Byte 100000Max. Byte 111111

Sub-Address 0F

00.51

VPPVPPVPP

VDFAMP Parabola Amplitude Function of VAMP(tracking between VAMP and VDF) withVPOS Typ. (see Figure 1 and Note 9)

Sub-Address 05Byte 10000000Byte 11000000Byte 11111111

0.611.5

VPPVPPVPP

VHDFKeyt Parabola Asymetry Function of VPOSControl(trackingbetween VPOSand VDF)with VAMP Max.

Sub-Address 06Byte x0000000Byte x1111111

0.520.52

VPPVPP

Notes : 5. These parametersare not tested on each unit. They are measured during our internalqualification.7. Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is controlled OFF when the

output transistor is OFF.7. Initial Condition for Safe Operation Start Up8. See Figure 14.9. S and C correction are inhibited so the output sawtooth has a linear shape.

9109SN05.TBL

TDA9109/SN

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VERTICAL SECTION (continued)Electrical Characteristics (VCC =12V,Tamb = 25oC) (continued)


East/West (E/W) FUNCTIONEWDC DC Output Voltage with Typ. VPOS,Keystone and

Corner inhibitedPin 24, see Figure 2 2.5 V

TDEWDC DC Output Voltage Thermal Drift See Note 13 100 ppm/CEWpara Parabola Amplitude with Max. VAMP, Typ. VPOS,

Keystone and Corner inhibitedSubaddress 0A

Byte 11111111Byte 11000000Byte 10000000

1.70.85

0

VPPVPPVPP

EWtrack Parabola Amplitude Function of VAMP Control(tracking between VAMPand E/W)with Typ.VPOS,Typ. E/W Amplitude,Keystone and Cornerinhibited(see Note 10)

Subaddress 05Byte 10000000Byte 11000000Byte 11111111

0.300.550.85

VPPVPPVPP

KeyAdj Keystone Adjustment Capability with Typ. VPOS,Corner and E/W inhibited and Max. VerticalAmplitude (see Note 10 and Figure 4)

Subaddress 09Byte 1x000000Byte 1x111111

0.650.65

VPPVPP

KeyTrack Intrinsic Keystone Function of VPOS Control(tracking between VPOS and E/W) with Max. E/WAmplitude,Max. Vertical Amplitude and Cornerinhibited (see Note 13 and Figure 2)

A/B RatioB/A Ratio

Subaddress 06

Byte x0000000Byte x1111111

0.520.52

Corner Corner Amplitude with Max. VAMP, Typ. VPOS,Keystone and E/W inhibited

Subaddress 0BByte 11111111Byte 11000000Byte 10000000

1.70

-1.7

VPPVPPVPP

INTERNAL DYNAMIC HORIZONTAL PHASE CONTROLSPBpara Side PinBalance Parabola Amplitude (Figure 3)with

Max. VAMP, Typ.VPOS and Parallelograminhibited(see Notes 10 & 14)

Subaddress 0DByte x1111111Byte x1000000

+1.4-1.4

%TH%TH

SPBtrack Side Pin Balance Parabola Amplitude function ofVAMP Control (tracking between VAMP and SPB)with Max. SPB, Typ. VPOS and Parallelograminhibited (see Notes 10 & 14)

Subaddress 05Byte 10000000Byte 11000000Byte 11111111

0.50.91.4

%TH%TH%TH

ParAdj Parallelogram Adjustment Capabili ty withMax . VAMP, Typ . VPOS and Max . SPB(see Notes 10 & 14)

Subaddress 0EByte x1111111Byte x1000000

+1.4-1.4

%TH%TH

Partrack Intrinsic Parallelogram Function of VPOS Control(tracking between VPOS and DHPC) withMax. VAMP, Max. SPB and Parallelogram inhibited(see Notes 10 & 14)

A/B RatioB/A Ratio

Subaddress 06

Byte x0000000Byte x1111111

0.520.52

VERTICALMOIREVMOIRE Vertical Moir (measured on VOUT : Pin 23) Subaddress 0C

Byte 01x11111 6 mVBREATHING COMPENSATIONBRRANG DC Breathing Control Range (see Note 15) V18 1 12 V

BRADj Vertical Output Variation versus DC BreathingControl (Pin 23)

V18 VREF-VV18 = 4V

0-10

%%

Notes : 10. With Register 07 at Byte x0xxxxxx (S correction is inhibited)and withRegister 08at Byte x0xxxxxx (C correction is inhibited),thesawtooth has a linear shape.

13. These parameters are not tested on each unit. They are measured during our internal qualification.14. TH is the horizontal period.15. When not used the DC breathing control pin must be connected to 12V.

9109SN05.TBL

TDA9109/SN

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B+ SECTIONOperating Conditions

Symbol Parameter Test conditions Min. Typ. Max. Unit

FeedRes Minimum Feedback Resistor Resistor between Pins 15 and 14 5 k

Electrical Characteristics (VCC =12V,Tamb = 25oC)Symbol Parameter Test conditions Min. Typ. Max. Unit

OLG Error Amplifier Open Loop Gain At low frequency (see Note 16) 85 dBICOMP Sunk Current on Error Amplifier

Output when BOUT is in safetycondition

Pin 14 (see Figure 14) 0.5 mA

UGBW Unity Gain Bandwidth (see Note 13) 6 MHzIRI Regulation Input Bias Current Current sourced by Pin 15 (PNP base) 0.2 A

EAOI Error Amplifier Output Current Current sourced by Pin 14Current sunk by Pin 14

0.52

mAmA

CSG Current Sense Input Voltage Gain Pin 16 3MCEth Max Current Sense Input Threshold

VoltagePin 16 1.2 V

ISI Current Sense InputBias Current Current sourced by Pin 16 (PNP base) 1 ATonmax Maximum ON Time of the external

power transistor% of Horizontal period,f0 = 27kHz (see Note 17)

100 %

B+OSV B+ Output Saturation Voltage V28 with I28 = 10mA 0.25 VIVREF Internal Reference Voltage Onerroramp(+)inputforSubaddress0B

Byte 10000004.8 V

VREFADJ I n te rn al R e fe r en ce Vol ta geAdjustment Range

Byte 1111111Byte 0000000

+20-20

%%

tFB+ Fall Time Pin 28 100 nsNotes : 13. These parameters are not tested on each unit. They are measured during our internal qualification.

16. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includescharacterization on batches coming from corners of our processes and also temperature characterization.

17. The external power transistor is OFF during about 400ns.

9109SN05.TBL

HDFDC

A

BVDFAMP

9109SN03.EPS

Figure 1 : VerticalDynamic Focus Function

DHPCDC

AB

SPBPARA

9109SN05.EPS

Figure 3 : Dynamic Horizontal Phase ControlOutput

EWDC

A

BEWPARA

9109SN04.EPS

Figure 2 : E/WOutput

Keyadj

9109SN06.EPS

Figure 4 : Keystone Effect on E/W Output(PCC and Corner Inhibited)

TDA9109/SN

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TYPICAL VERTICAL OUTPUT WAVEFORMS

Function SubAddress Pin Byte Specification Effect on Screen

Vertical Size 05 23

10000000

11111111

VerticalPosition

DCControl

06 23x0000000x1000000

x1111111

VOUTDC= 3.2VVOUTDC= 3.5VV

OUTDC= 3.8V

VerticalS

Linearity07 23

0xxxxxxxInhibited

1x111111

VerticalC

Linearity08 23

1x000000

1x111111

9109SN06.TBL/9109SN07.EPSTO9109SN13.EPS

2.25V

3.75VVOUTDC

VOUTDC

VPP

V

VVPP

= 4%

VPP

V

VVPP

= 3%

VVPPVVPP

= 3%

TDA9109/SN

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GEOMETRY OUTPUT WAVEFORMS

Function SubAddress Pin Byte Specification Effect on Screen

Keystone(Trapezoid)

Control09 24

E/W+ Cornerinhibited

1x000000

1x111111

E/W(Pin Cushion)

Control0A 24

Keystone +Corner

inhibited

10000000

11111111

CornerControl 0B 24

Keystone+E/W inhibited

11111111

10000000

ParrallelogramControl 0E Internal

SPBinhibited

1x000000

1x111111

Side PinBalanceControl

0D Internal

Parallelograminhibited

1x000000

1x111111

VerticalDynamicFocus

0F 10

9109SN07.TBL/9109SN14.EPSTO9109SN24.EPS

1.7V

2.5V

1.7V

1.4% TH3.7V

3.7V 1.4% TH

1.4% TH3.7V

1.4% TH3.7V

2VTV

2.5V

2.5V

0.65V

0.65V

0V

1.7V

2.5V

TDA9109/SN

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I2C BUSADDRESS TABLESlave Address (8C) : WriteModeSub Address Definition

D8 D7 D6 D5 D4 D3 D2 D10 0 0 0 0 0 0 0 0 Horizontal Drive Selection1 0 0 0 0 0 0 0 1 Horizontal Position2 0 0 0 0 0 0 1 0 Forced Frequency3 0 0 0 0 0 0 1 1 Sync Priority / Horizontal Moir Amplitude4 0 0 0 0 0 1 0 0 Refresh / B+ Reference Adjustment5 0 0 0 0 0 1 0 1 Vertical Ramp Amplitude6 0 0 0 0 0 1 1 0 Vertical Position Adjustment7 0 0 0 0 0 1 1 1 S Correction8 0 0 0 0 1 0 0 0 C Correction9 0 0 0 0 1 0 0 1 E/W KeystoneA 0 0 0 0 1 0 1 0 E/W AmplitudeB 0 0 0 0 1 0 1 1 E/W Corner AdjustmentC 0 0 0 0 1 1 0 0 Vertical Moir AmplitudeD 0 0 0 0 1 1 0 1 Side Pin BalanceE 0 0 0 0 1 1 1 0 ParallelogramF 0 0 0 0 1 1 1 1 Vertical Dynamic Focus Amplitude

Slave Address (8D) : Read ModeNo sub addressneeded.

TDA9109/SN

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D8 D7 D6 D5 D4 D3 D2 D1

WRITE MODE

00HDrive0, off[1], on

01Xray

1, reset[0]

Horizontal Phase Adjustment[1] [0] [0] [0] [0] [0] [0]

02Forced Frequency1,on[0], off

1, f0 x 2[0], f0 x 3

03Sync

0, Comp[1], Sep

HMoir1,on[0]

Horizontal Moir Amplitude[0] [0] [0] [0] [0]

04DetectRefresh[0], off

B+ Reference Adjustment

[1] [0] [0] [0] [0] [0] [0]

05Vramp0, off[1], on

Vertical Ramp Amplitude Adjustment[1] [0] [0] [0] [0] [0] [0]

06 Vertical Position Adjustment[1] [0] [0] [0] [0] [0] [0]

07S Select

1,on[0]

S Correction[1] [0] [0] [0] [0] [0]

08C Select

1,on[0]

C Correction[1] [0] [0] [0] [0] [0]

09E/W Key

0, off[1]

E/W Keystone

[1] [0] [0] [0] [0] [0]0A E/W Amplitude

[1] [0] [0] [0] [0] [0] [0]

0BE/W Cor

0, off[1]

E/W Corner Adjustment[1] [0] [0] [0] [0] [0] [0]

0CTestV1,on[0], off

VMoir1,on[0]

Vertical Moir Amplitude[0] [0] [0] [0] [0]

0DSPB Sel

0, off[1]

Side Pin Balance[1] [0] [0] [0] [0] [0]

0EParallelo

0, off[1]

Parallelogram

[1] [0] [0] [0] [0] [0]

0FTest H1,on

[0], off

Vertical Dynamic Focus Amplitude[1] [0] [0] [0] [0] [0]

READ MODEHlock0,on

[1], no

Vlock0,on

[1], no

Xray1,on[0], off

Polarity Detection Sync DetectionH/V pol

[1], negativeV pol

[1], negativeVext det

[0], no detH/V det

[0], no detV det

[0], no det[ ] initial value

Data is transferred with vertical sawtooth retrace.We recommend to set the unspecified bit to [0] in order to assure the compatibility with future devices.

I2C BUSADDRESS TABLE (continued)

TDA9109/SN

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OPERATING DESCRIPTIONI - GENERAL CONSIDERATIONSI.1 - Power Supply

The typical values of the power supply voltagesVCC and VDD are 12V and 5V respectively. Opti-mum operation is obtained for VCC between 10.8and 13.2V and VDD between 4.5 and 5.5V.Inorderto avoiderraticoperationof thecircuitduringthetransientphaseof VCC andVDDswitchingon,oroff,the value of VCC andVDDaremonitored : ifVCCislessthan7.5Vtyp.orifVDDislessthan4.0Vtyp.,theoutputsof the circuit are inhibited.Similarly,beforeVDDreaches4V,all theI2C registerare reset to theirdefault value.In order to have very good power supply rejection,the circuit is internally supplied by several voltagereferences (typ. value : 8V). Two of these voltagereferences are externally accessible, one for thevertical and one forthe horizontalpart.Theycanbeused to bias external circuitry (if ILOADis less than5mA).It is necessary to filterthe voltagereferencesbyexternalcapacitorsconnectedtoground,inorderto minimize the noise and consequentlythe jitteronvertical and horizontaloutputsignals.I.2 - I2C ControlTDA9109/SN belongs to the I2C controlled devicefamily. Instead of being controlled by DC voltageson dedicatedcontrolpins, each adjustmentcanbedone via the I2C Interface.TheI2C bus is a serial bus with a clockand a datainput.Thegeneralfunctionandthebusprotocolarespecified in the Philips-bus data sheets.Theinterface(Dataand Clock)is a comparatorwithhysteresis ; thethresholds(less then2.2V onrisingedge, more than 0.8V on falling edge with 5Vsupply) are TTL-compatible. Spikes of up to 50nsarefilteredby anintegratorandthe maximum clockspeedis limited to 400kHz.The data line (SDA) can be used bidirectionally.In read-mode the IC sends reply information(1 byte) to the micro-processor.The bus protocol prescribes a full-byte transmis-sion in all cases. The first byte after the startcondition is used to transmit the IC-address(hexa8C for write, 8D for read).

I.3 - Write ModeIn write mode the second byte sent contains thesubaddress of the selected function to adjust (orcontrolsto affect)and thethirdbytethecorrespond-ing data byte. It is possibleto sendmore than onedata byte to the IC. If after the thirdbyte no stop orstart condition is detected, the circuit incrementsautomaticallyby onethe momentarysubaddressinthe subaddress counter (auto-increment mode).So it is possible to transmit immediately the follow-ing data bytes without sending the IC address orsubaddress.This canbeusefulto reinitializeall thecontrols very quickly (flash manner). This proce-dure can be finished by a stop condition.Thecircuit has14adjustmentcapabilities : 1 forthehorizontal part, 4 for the vertical, 2 for the E/Wcorrection,2 for thedynamichorizontalphase con-trol,1 for the Moir option, 3 for the horizontal andthe vertical dynamic focus and 1 for the B+ refer-ence adjustment.17 bits are also dedicated to several controls(ON/OFF, Horizontal Forced Frequency,Sync Pri-ority, Detection Refresh and XRAY reset).

I.4 - Read ModeDuring the read mode the second byte transmitsthe reply information.

The reply byte contains the horizontal and verticallock/unlockstatus, the XRAY activationstatusand,the horizontalandvertical polaritydetection.It alsocontainsthe sync detectionstatuswhichis usedbythe MCU to assign the sync priority.Astopconditionalwaysstopsallthe activitiesof thebus decoderand switchesto high impedanceboththe data and clock line (SDAand SCL).See I2C subaddressand control tables.

I.5 - Sync ProcessorThe internal sync processor a l lows theTDA9109/SNto accept :- separated horizontal & vertical TTL-compatiblesync signal,- composite horizontal & vertical TTL-compatible

sync signal.

TDA9109/SN

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I.6 - Sync Identification StatusThe MCU can read (address read mode : 8D) thestatus register via the I2C bus, and then select thesync priority dependingon this status.Among other data this register indicates the pres-ence of sync pulses on H/HVIN, VSYNCIN and(when 12V is supplied) whether a Vext has beenextractedfromH/HVIN.Bothhorizontaland verticalsync are detected even if only 5V is supplied.In order to choose the right sync priority the MCUmay proceed as follows (see I2C AddressTable) :- refresh the status register,- wait at least for 20ms (Max. vertical period),- read this status register.Sync priority choice should be :Vextdet

H/Vdet

Vdet

Sync prioritySubaddress

03 (D8)CommentSync type

No Yes Yes 1 Separated H & VYes Yes No 0 Composite TTL H&V

Ofcourse,whenthechoiceismade,wecanrefreshthe sync detections and verify that the extractedVsync is present and that no sync type changehasoccured. The sync processor also gives sync po-larity information.I.7 - IC statusTheIC caninformtheMCU about the1sthorizontalPLLand vertical section status (locked or not)andabout the XRAY protection (activated or not).Resetting the XRAY internal latch can be doneeither by decreasing the VCC or VDD supply ordirectly resetting it via the I2C interface.I.8 - Sync InputsBothH/HVINandVSYNCINinputsareTTLcom-patible triggers with hysterisis to avoid erraticdetection. Both inputs include a pull up resistorconnected to VDD.I.9 - Sync ProcessorOutputThe sync processor indicates on the HLOCKOUTPin whether 1st PLL is locked to an incominghorizontal sync. HLOCKOUT is a TTL compatibleCMOS output. Its level goes to high when locked.In the same time the D8 bit of the status register isset to 0.This information is mainly used to trigger safetyprocedures (like reducing B+ value) as soon as achangeis detectedon the incoming sync.

II - HORIZONTAL PARTII.1 - Internal Input ConditionsA digital signal (horizontal sync pulse or TTLcomposite) is sent by the sync processor to the

OPERATING DESCRIPTION (continued)

9109SN25.EPS

Figure 5

d d

C

TRAMEXT

9109SN26.EPS

Figure 6

horizontalinput. Itmaybepositiveor negative(seeFigure5).

Using internal integration, both signals are recog-

nized if Z/T < 25%. Synchronizationoccurs on theleading edge of the internal sync signal. The mini-mum value of Z is 0.7s.Another integration is able to extract the verticalpulsefromcompositesyncif thedutycycleis higherthan25% (typically d = 35%) (see Figure 6).

The lastfeatureperformedis theremovalof equali-zationpulsesto avoidparasiticpulsesonthephasecomparator(which would be disturbed by missingor extraneouspulses).II.2 - PLL1The PLL1 consists of a phase comparator, anexternal filter and a voltage-controlled oscilla-tor (VCO).Thephasecomparator is a phasefrequencytypedesigned in CMOStechnology.This kind of phasedetectoravoids lockingon wrong frequencies.It isfollowed by a charge pump, composed of twocurrent sources : sunk and sourced (typi-cally I = 1mA when locked and I = 140A whenunlocked).This differencebetween lock/unlock al-lows smooth catching of the horizontal frequencyby PLL1. This effect is reinforced by an internaloriginal slow down system when PLL1 is locked,avoiding the horizontal frequency changing tooquickly.The dynamic behaviour of PLL1 is fixed by anexternal filter which integrates the current of thecharge pump. A CRC filter is generally used(seeFigure 7).

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6

7PLL1F(LoopFilter)

R0

1.6V

6.4V

5

C06.4V

1.6V0 0.875TH TH

RSFLIP FLOP

(1.3V < V < 6V)7

I02

4 I0

I0

9109SN29.EPS

Figure 9 : Details of VCO

LOCKDET

COMP1INPUTINTERFACEH/HVIN

HighCHARGE

PUMPLow

PLLINHIBITION VCO

7 6 5PLL1F R0 C0

PHASEADJUST

E2

I2CHPOSAdj.

OSCTramext

Tramext I2CForced

Frequency

Lock/UnlockStatus

8HPOSITION

1

9109SN28.EPS

Figure 8 : Block Diagram


7PLL1F

1F

4.7F

1.8k

9109SN27.EPS

Figure 7

ThePLL1 is internallyinhibitedduringextractedver-tical sync (if any) to avoid taking in account missing

pulses or wrong pulses on phase comparator.The inhibition is done by a switchlocated betweenthe charge pump and the filter (see Figure 8).The VCO usesan externalRC network. It deliversa linear sawtooth obtained by the charge and thedischarge of the capacitor, with a current propor-tional to the current in the resistor. The typicalthresholdsof the sawtoothare 1.6Vand 6.4V.The control voltage of the VCO is between 1.33Vand 6V (see Figure 9). The theorical frequencyrange of this VCO is in the ratio of 1 to 4.5. Theeffective frequency range has to be smaller(1 to 4.2) due to clamp intervention on the filterlowest value.

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BOUT

HORIZONTALOUTPUTINHIBITION

VERTICALOUTPUTINHIBITION

SR

Q

Horizontal Flyback0.7V

XRAY Protection

VCC Checking

VCC

VCC or VDD off or I2C ResetXRAY

VSCinh

I2C Drive on/off

I2C Rampon/off

VDD Checking

VDDVSDinh

9109SN34.EPS

Figure 14 : Safety Functions Block Diagram

OPERATING DESCRIPTION (continued)II.4 - Output SectionThe H-drive signal is sent to the output through ashaping stagewhich also controls the H-drivedutycycle (I2C adjustable) (see Figure 11). In order tosecure the scanning power part operation, theoutput is inhibited in the following cases :- when VCC or VDD are too low,- when the XRAY protection is activated,- during the Horizontal flyback,- when the HDrive I2C bit control is off.Theoutputstageconsistsof a NPNbipolar transis-tor.Only thecollector is accessible(seeFigure13).This output stage is intended for reverse basecontrol, where setting the output NPN in off-statewill control the power scanning transistor in off-state (see ApplicationDiagram).The maximum output current is 30mA, and thecorrespondingvoltage drop of theoutput VCEsat is0.4V Max.Obviouslythe powerscanningtransistorcannotbedirectlydriven by theintegratedcircuit.An interfacehas to beadded betweenthe circuitand the powertransistor eitherof bipolaror MOS type.

II.5 - X-RAY ProtectionTheX-Ray protectionis activatedby applicationofa high level on the X-Ray input (8V on Pin 25).It inhibits the H-Drive and B+ outputs.Thisprotectionis latched ; itmay be reset either byVCC or VDDswitchoff or by I2C (see Figure 14).

20k

Q1

GND 0V

12HFLY400

9109SN32.EPS

Figure 12 : Flyback Input Electrical Diagram

H-DRIVE26

VCC

9109SN33.EPS

Figure 13

II.6 - Vertical Dynamic FocusThe TDA9109/SN delivers a vertical parabolawaveform on Pin 10.This vertical dynamic focus is tracked with VPOSand VAMP. Its amplitudecan be adjusted.It is alsoaffectedby Sand Ccorrections.Thispositivesignalonce amplified is to be sent to the CRT focusinggrids.

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OPERATING DESCRIPTION (continued)III - VERTICAL PART

III.1 - Function

23 VOUT

18 BREATH

VERT_AMPSUB05/7bits

VMOIRESUB0C/5bitsVPOSITIONSUB06/7bits

2220

SYNCHRO OSCILLATOR2

OSCCAPDISCH.

VSYNCIN

POLARITY

SAMPLING SAMPLINGCAPACITANCE

VlowSawth.Disch.

REF

TRANSCONDUCTANCEAMPLIFIERCHARGE CURRENT

VS_AMPSUB07/6bitsCOR_CSUB08/6bits

S CORRECTION

C CORRECTION

9109SN35.EPS

Figure 15 : AGC LoopBlock Diagram

When the synchronizationpulse is not present, aninternal current source sets the free running fre-quency.For an external capacitor, COSC = 150nF,the typical free running frequency is 100Hz.The typical free running frequency can be calcu-lated by :

f0 (Hz) = 1.5 105 1COSCA negative or positive TTL level pulse applied onPin2 (VSYNC)as well asa TTLcompositesynconPin 1 can synchronize the ramp in the range

[fmin , fmax].This frequencyrangedependson theexternal capacitor connected on Pin 22.A 150nF ( 5%) capacitor is recommended for50Hz to 185Hzapplications.The typical maximum and minimum frequency, at25oC and without any correction (S correction orC correction), can be calculatedby :

f(Max.)= 3.5 x f0 and f(Min.)= 0.33 x f0

If S or C correctionsare applied, thesevalues areslighty affected.If a synchronizationpulse isapplied,the internaloscillator is synchonized immediately but itsamplitude changes. An internal correction thenadjusts it in less than half a second. The topvalue of the ramp (Pin 22) is sampled on theAGC capacitor (Pin 20) at each clock pulse anda transconductance amplifier modifies thecharge current of the capacitor in such a way tomake the amplitude again constant.Theread statusregisterprovides the verticalLock-Unlockand the vertical sync polarity information.We recommendthe use of an AGC capacitor withlow leakage current. A value lower than 100nA ismandatory.A good stability of the internal closed loop isreached by a 470nF 5% capacitor value onPin 20 (VAGC).

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III.2 - I2C Control AdjustmentsS and C correction shapes can then be added tothis ramp. These frequency independentS and Ccorrections are generated internally. Their ampli-tudesare adjustableby their respective I2C regis-ters. They canalso be inhibitedby their select bits.Finally, the amplitude of this S and C correctedramp can be adjusted by the vertical ramp ampli-tude control register.Theadjusted ramp is availableon Pin 23 (VOUT) todrive an externalpower stage.The gain of this stage can be adjusted ( 25%)dependingon its register value.The mean value of this ramp is driven by its ownI2C register (vertical position). Its value isVPOS = 7/16 VREF-V 300mV.

UsuallyVOUTis sent through a resistivedivider tothe inverting input of the booster. Since VPOSderives from VREF-V, the bias voltage sent to thenon-inverting input of the booster should also de-rive from VREF-Vto optimizethe accuracy(seeAp-plicationDiagram).III.3 - VerticalMoirBy using the vertical moir, VPOS can be modu-latedfromframeto frame. Thisfunctionis intendedtocancel the fringes which appearwhen line to line

interval is very close to the CRTvertical pitch.The amplitude of the modulation is controlled byregister VMOIRE on sub-address 0C and can beswitched-off via the control bit D7.III.4 - Basic EquationsIn first approximation,the amplitudeof theramp onPin 23 (VOUT) is :VOUT- VPOS= (VOSC - VDCMID) (1 + 0.25(VAMP))with:- VDCMID= 7/16 VREF (middle value of the ramp

on Pin 22, typically 3.5V)- VOSC = V22 (ramp with fixed amplitude)

- VAMP= -1for minimumvertical amplituderegistervalue and+1 formaximum- VPOSis calculatedby : VPOS= VDCMID+ 0.3VP

with VP equals -1 for minimum vertical positionregister value and +1 for maximum

The current available on Pin 22 is :

IOSC = 38 VREF COSC f

with: COSC : capacitor connected on Pin 22 andf : synchronizationfrequency.

III.5 - Geometric CorrectionsThe principle is representedin Figure 16.Startingfromthe vertical ramp, a parabola-shapedcurrentis generatedforE/Wcorrection(alsoknownas Pin Cushion correction), dynamic horizontalphase control correction, and vertical dynamic Fo-cus correction.The parabola generator is made by an analogmultiplier, the output current of which is equal to :

I = k (VOUT- VDCMID)2

where VOUT is theverticaloutput ramp (typically be-tween2and5V)andVDCMIDis3.5V(forVREF-V= 8V).Onemoremultiplierprovidesa currentproportionalto (VOUT- VDCMID)4 for corner correction.The VOUTsawtooth is typically centered on 3.5V.By changing the vertical position, the sawtoothshifts by 0.3V.In orderto havegoodscreengeometryfor any enduser adjustment, the TDA9109/SN has the ge-ometry tracking feature, which allows generationof a dissymetric parabola depending on the verti-cal position.Due to the large output stage voltage range (E/W,Keystone, Corner), the combination of trackingfunction with maximum vertical amplitude, maxi-mum or minimum vertical position and maximumgain on the DAC control may lead to the outputstage saturation. This must be avoidedby limitingthe output voltage with apropriate I2C registersvalues.Forthe E/Wpartandthe dynamichorizontalphasecontrol part, a sawtooth-shapeddifferential currentin thefollowing form is generated:

I = k (VOUT- VDCMID)Then I and I are added and converted intovoltage for the E/W part.Each of the three E/W components, and the twodynamichorizontalphasecontrolsmay beinhibitedby their own I2C select bit.The E/W parabola is available on Pin 24 via anemitter follower output stage which has to be bi-ased by an external resistor (10k to ground).Sincestable in temperature,the devicecanbe DCcoupled with an externalcircuitry.The vertical dynamic focus is availableon Pin 10.The dynamic horizontal phase control drives inter-nally the H-position, moving the HFLY position onthe horizontal sawtooth in the range of 1.4% THboth for side pin balance and parallelogram.


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EW Output

EW+ Amp

Keystone

Sidepin Amp

Parallelogram

Dynamic Focus

Sidepin BalanceOutputCurrent

To HorizontalPhase

VDCMID(3.5V)2

Vertical Ramp VOUT

V.FocusAmp

ParabolaGenerator

VDCMID(3.5V)

VDCMID(3.5V)

23

24

10

Corner

2

9109SN36.EPS

Figure 16 : GeometricCorrections PrincipleOPERATING DESCRIPTION (continued)

III.6 - E/WEWOUT = 2.5V + K1(VOUT- VDCMID)+ K2 (VOUT- VDCMID)2 + K3 (VOUT- VDCMID)4K1 is adjustableby the keystone I2C register,K2 is adjustableby the E/W amplitude I2C register,K3 is adjustableby the cornerI2C register.III.7 - Dynamic Horizontal Phase ControlIOUT= K4 (VOUT - VDCMID)+ K5 (VOUT- VDCMID)2

K4 is adjustable by the parallelogramI2C register,K5 is adjustableby the side pin balance I2C register.

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IV - DC/DC CONVERTER PARTOPERATING DESCRIPTION (continued)

This unit controls the switch-mode DC/DC con-verter. It converts a DC constant voltage into theB+ voltage (roughly proportional to the horizontalfrequency)necessary for thehorizontal scanning.ThisDC/DC converter must be configured in step-up mode. It operates very similarly to the wellknown UC3842.

IV.1 - Step-up ModeOperating Description- The power MOS is switched-on at the middle of

the horizontalflyback.- The power MOS is switched-offwhen its current

reachesa predeterminedvalue.Forthispurpose,a sense resistor is inserted in its source. Thevoltage on this resistor is sent to Pin16 (ISENSE).

- The feedback (coming either from the EHV orfrom the flyback)is divided to a voltage close to

4.8V andcompared to the internal4.8Vreference(IVREF). The difference is amplified by an erroramplifier, the output of which controls the powerMOS switch-off current.

Main Features- Switching synchronized on the horizontal fre-

quency,- B+ voltage always higher than the DC source,- Current limited on a pulse-by-pulsebasis.The DC/DC converter is disabled :- when VCC or VDDare too low,- when X-Rayprotection is latched,- directly through I2C bus.Whendisabled,BOUTisdriventoGNDbya 0.5mAcurrent source. This feature allows to implementexternallya soft start circuit.

161415

VB+

L+

C3

C21/3

S

RQ

400ns

Inhibit SMPS

28

12V

BOUT

ISENSECOMPREGIN

95dBA

Iadjust

DAC7bits

I2C

TDA9109/SN

1M22k

1.2V

1.2V

4.8V 20%

8V

InhibitSMPS Soft

Start

9109SN37.EPS

Figure 17 : DC/DC Converter

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INTERNAL SCHEMATICS

Pins 1 -2H/HVIN

VSYNCIN

20k

200

5V

9109SN38.EPS

Figure 18

5V

3 HLOCKOUT

9109SN39.EPS

Figure 19

4

13

12V

PLL2C

HREF

9109SN40.EPS

Figure 20

5

1312V

C0

HREF

9109SN41.EPS

Figure 21

6

13 1312V

HREF HREF

R0

9109SN42.E

PS

Figure 22

7PLL1F

9109SN43.E

PS

Figure 23

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INTERNAL SCHEMATICS (continued)

8

12V HREF

HPOSITION

9109SN44.EPS

Figure 24

9

12V

HMOIRE

5V

9109SN45.EPS

Figure 25

10FOCUSOUT

12V

12V

9109SN46.EPS

Figure 26

12

13

12V

HREF

HFLY

9109SN47.EPS

Figure 27

14COMP

9109SN48.EPS

Figure 28

15REGIN

12V

9109SN49.EPS

Figure 29

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16

12V

ISENSE

9109SN50.EPS

Figure 30

18BREATH

12V

9109SN51.EPS

Figure 31

20

12V

VAGCCAP

9109SN52.EPS

Figure 32

22VCAP

12V

9109SN53.EPS

Figure 33

23

12V

VOUT

9109SN54.EPS

Figure 34

24EWOUT

12V

9109SN55.EPS

Figure 35

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25

12V

XRAY

9109SN56.EPS

Figure 36

HOUT-BOUTPins 26-28

12V

9109SN57.EPS

Figure 37

12V

Pins 30-31SDA - SCL

9109SN58.EPS

Figure 38

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PMSDIP32.EPS

PACKAGE MECHANICAL DATA32 PINS - PLASTICSHRINK DIP

Dimensions Millimeters InchesMin. Typ. Max. Min. Typ. Max.

A 3.556 3.759 5.080 0.140 0.148 0.200A1 0.508 0.020A2 3.048 3.556 4.572 0.120 0.140 0.180B 0.356 0.457 0.584 0.014 0.018 0.023

B1 0.762 1.016 1.397 0.030 0.040 0.055C 0.203 0.254 0.356 0.008 0.010 0.014D 27.43 27.94 28.45 1.080 1.100 1.120E 9.906 10.41 11.05 0.390 0.410 0.435

E1 7.620 8.890 9.398 0.300 0.350 0.370e 1.778 0.070

eA 10.16 0.400eB 12.70 0.500L 2.540 3.048 3.810 0.100 0.120 0.150 SD

IP32.TBL

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of t hird parties which may result fromits use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviouslysupplied.STMicroelectronicsproducts are notauthorizedfor use as criticalcomp onentsin lifesupport devicesor systemswithout express written approval of STMicroelectronics.

The ST logo is a trademark of STMicroelectronics

1998 STMicroelectronics - All Rights Reserved

Purchase of I 2C Components of STMicroelectronics, conveys a licenseunder the Philips I 2C Patent.Rights to use thesecomponents in a I 2C system, is granted providedthat the system conforms to

the I 2C Standard Specifications as defined by Philips.

STMicroelectronics GROUP OF COMPANIESAustralia - Brazil - Canada- China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco- The Netherlands

Singapore - Spain- Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

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