2104 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 10 ...ims.unipv.it/FIRB2006/pub/Mazzanti10a.pdf · The technique allows covering an RF bandwidth three times ... low-noise

2104 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 10, OCTOBER 2010

A Low Phase-Noise Multi-Phase LO Generator forWideband Demodulators Based on Reconfigurable

Sub-Harmonic MixersAndrea Mazzanti, Member, IEEE, Mohammad B. Vahidfar, Student Member, IEEE, Marco Sosio, and

Francesco Svelto, Member, IEEE

Abstract—The advent of wideband systems, e.g., software de-fined radios, cognitive radios and UWB technology, motivates re-search for new transceiver architectures and circuit topologies toarrive at compact and low power solutions. Reference frequencygeneration in wideband CMOS receivers is usually power and areahungry. In this paper a wide band quadrature demodulator, basedon mixers reconfigurable between fundamental and sub-harmonicoperation modes is presented. The technique allows covering anRF bandwidth three times larger than the frequency covered bythe synthesizer. Multiple local oscillator phases are required forthe proposed architecture. For low phase noise and fast settlingtime, they are generated by means of a multi-stage injection lockedring oscillator. This solution proves very accurate and power effi-cient and may find applications in other communication systemsrequiring multiple phase references.

A demodulator test chip tailored to WiMedia UWB groups 1,3,4(3.1–9.5 GHz), and comprising mixers and frequency synthesizer,has been realized in a 65 nm CMOS technology. Experimental re-sults show 10 dB of conversion gain with 2.3 nV/sqrt(Hz) equivalentinput noise voltage spectral density. IIP2 and IIP3, with interferersin the GSM and WLAN bands, are 40 dBm and 11 dBm respec-tively. The synthesizer displays maximum spurs level of 43 dBc,a state of the art phase noise of 128 dBc/Hz@10 MHz offset anda settling time of less than 6 ns with 43 mW only.

Index Terms—Fast hopping synthesizer, injection locking, multiphase local oscillator, phase noise, ring oscillator, sub-harmonicmixers, ultra wide band, UWB.

I. INTRODUCTION

I N order to extract gain at RF, CMOS ICs largely rely ontuned circuits where purposely introduced inductors res-

onate out parasitic capacitors extracting gain at least in narrow-bands. Besides restoring impedance levels at gain nodes, LCfilters are also key for interferer selection and noise reduction

Manuscript received December 23, 2009; revised June 20, 2010; acceptedJune 27, 2010. Date of current version September 24, 2010. This paper was ap-proved by Associate Editor Ranjit Gharpurey. This work was supported in partby a National funded Research Program (F.I.R.B.) under Contract RBA06L4S5.

A. Mazzanti is with the Università degli Studi di Pavia. He is also with theDipartimento di Ingegneria dell’Informazione, Università di Modena e ReggioEmilia, 41100, Modena, Italy (e-mail: [email protected]).

M. B. Vahidfar was with the Istituto Universitario Studi Superiori di Pavia,and is now with SiTune, San Jose, CA.

M. Sosio and F. Svelto are with the Università degli Studi di Pavia, Italy.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2010.2060258

in sensitive blocks. The advent of wideband systems, e.g., soft-ware defined radios, cognitive radios and UWB technology, isdetermining new emphasis on innovative techniques for keyRF circuit blocks [1]–[5]. A flourishing design activity towardwide-band, low-noise RF front-ends has lead to new topologiesand techniques: multi-section input stage filters for widebandLNA matching [6], low noise wideband amplifiers based on re-active feedback [7], noise cancelling techniques in LNA [8], [9]and receiver front-ends [10]. In the frequency synthesis area, themost effective emerging technique consists in generating sumand difference frequencies from a single VCO and its dividedreplica by means of Single-Side-Band mixers but it comes witha set of problems: spurious tones due to mixer non-linearities,large power consumption and circuit complexity [11]–[15]. Thiswork proposes an alternative view, not suffering from the aboveshortcomings, to demodulate a wideband input spectrum. In par-ticular, RF signals belonging to a wide-frequency range can bedemodulated in a single receiver chain by means of a down-con-verter reconfigured between conventional and sub-harmonic op-eration modes. In this way, the Local Oscillator (LO) is requiredto cover only a fraction of the frequency range, demodulating thelower portion in conventional mode and the upper in sub-har-monic mode.

Multiple LO signals equally spaced in time are required bythe mixers operating in sub-harmonic mode. The frequency syn-thesizer is based on an injection locked four-stages differentialring oscillator. This solution proves very accurate, low noise andpower efficient and lends itself to other applications in systemsrequiring multiple phase references, like high speed transceiversfor serial links.

Test chips tailored to the WiMedia UWB band groups #1,3,4,shown in Fig. 1 have been designed in a 65 nm CMOS tech-nology [16]. The block diagram of the implemented demodu-lator is shown in Fig. 2. The fast-hopping frequency synthe-sizer employs LC based PLLs to injection lock a multi-phasering oscillator. The phase selector reconfigures I and Q mixersbetween conventional and sub-harmonic modes. Compared topreviously reported alternative solutions for WiMedia UWB fre-quency synthesizers, the proposed approach leads to the lowestpower dissipation.

The paper is organized as follows. Section II reviews the prin-ciple of sub-harmonic down-conversion tailored to the UWB-OFDM system. Section III presents the design of the injectionlocked oscillator for multi-phase LO generation. Other mainsynthesizer building blocks (LC based PLL and multiplexer) are

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MAZZANTI et al.: A LOW PHASE-NOISE MULTI-PHASE LO GENERATOR FOR WIDEBAND DEMODULATORS 2105

Fig. 1. Frequency allocation of UWB-OFDM, according to WiMedia specifi-cation.

Fig. 2. Block diagram of the I & Q demodulator.

discussed in Section IV while mixers requirements and designare presented in Section V. Experimental results for the com-plete demodulator and a performance comparison against alter-native solutions for UWB are presented in Section VI while theconclusions follow, in Section VII.

II. SYSTEM DESCRIPTION

Fig. 3 shows the schematic diagram of a CMOS sub-harmonicmixer. This circuit has been proposed to down-convert an RFsignal with a frequency synthesizer running at half frequency[17]. Assuming hard switching of the devices, the input RF cur-rent is sequentially multiplied by square waves aligned with thetwo local oscillator signals and . When the two LOsare in quadrature, as shown in Fig. 3(b), their multiplication pro-duces an equivalent LO at twice frequency. On the other hand, asshown by the timing diagram in Fig. 3(c), operation as a stan-dard mixer, e.g., in fundamental mode, is straightforward justproviding a DC voltage instead of one of the two LO signals.By exploiting these two distinct modes of operation, this cir-cuit can be adopted to cover an RF band much larger than thesynthesizer band. Referring to the UWB frequency allocationof Fig. 1, groups 3 and 4 fall at roughly twice the frequency ofgroup 1. With the mixer circuit of Fig. 3 working in fundamentalmode for group 1, and sub-harmonic mode for groups 3 and 4,all the 3 UWB groups can be demodulated with a synthesizercovering the bandwidth of group 1 only. Group 2 is typicallyof minor interest because the spectrum is shared with strong,narrow band, WLAN interferers and poses severe challenges inthe UWB receiver. For this reason it has been disregarded in thisimplementation.

For quadrature demodulation a pair of mixers with the ap-propriate LO phase sequence is required, as shown in Fig. 4.

Fig. 3. a) Schematic of a sub-harmonic mixer, b) LO waveforms for sub-har-monic mode and c) fundamental modes of operation.

Fig. 4. Quadrature demodulation with mixers working in fundamental mode(top) and sub-harmonic mode (bottom).

Sub-harmonic quadrature demodulation needs four (differen-tial) LO phases, equally spaced by 45 .

To provide spectral pure, low phase noise LO phases, a ringoscillator injection locked by a phase-locked loop (PLL) basedon a LC-VCO is proposed. Due to the specified fast frequencyhopping between the three channels in the same group, of lessthan 9 ns, the system is intended to operate with three multi-plexed PLLs. In the present implementation, only two have beenintegrated while the third input of the multiplexer is fed with areference signal generated off-chip for testing purposes. With


Fig. 5. (a) Injection-locked 4-stages ring oscillator, (b) schematic of a delay cell, (c) replica bias circuit and (d) schematic of the first delay cell with injection pair.

the two on-chip PLLs we intend to verify the fast-settling timeof the synthesizer/demodulator and check possible frequencypush/pull issues between them. The external synthesizer allowsa frequency tuning wider than the on-chip PLLs and is used tocharacterize the ring oscillator. The two on-chip PLLs are iden-tical. The tuning range of the VCOs have been overdesigned,with 34% fractional frequency coverage. Their design can befurther optimized dedicating each PLL to a specific channel ineach group. As an example, PLL-1 should provide only the ref-erence for channel 1 of group 1 (3432 MHz) and for channel 1in groups 3 and 4 (i.e. 1/2 6600 MHz and 1/2 8184 MHzrespectively) corresponding to a frequency tuning range require-ment for the VCO of 22%.

As explained in the next section, to avoid systematic quadra-ture phase error in the base band down converted signals, thefree-run frequency of the ring oscillator needs to be adjusted foreach channel. The ring oscillator is therefore digitally tunableand a frequency control word for each UWB channel is pre-determined during a calibration step and is stored in registerscontrolled by an serial interface. As shown in Fig. 2, thesame interface also allows the control of the phase selectorto feed the mixers with the correct LO phase sequence and thePLLs multiplexer.

III. INJECTION LOCKED RING OSCILLATOR

The block diagram of the 4 stages injection locked ring oscil-lator is reported in Fig. 5(a) while the schematic of the delay cellis shown in Fig. 5(b). It consists of a tail biased NMOS differ-ential pair with a resistive load implemented with PMOSdevices. The free-run frequency is tunable between 3 GHz and5.6 GHz by digitally switching the binary sized PMOS loads.The frequency tuning range is large enough to cover the de-sired channel frequency under process, voltage, and temperature(PVT) variations. In order to keep the output voltage swing con-stant, a replica biasing circuit, shown in Fig. 5(c), is introducedto adjust the current of each cell. Transistor keeps a con-stant voltage drop on a replica load. The biasing current changedue to a variation of the load resistance is then mirrored to thering delay cells by transistor . Total current consumption ofthe ring oscillator changes from 4.9 mA to 9.8 mA at minimumand maximum oscillation frequencies, respectively.

The frequency tuning resolution requirement is set by themaximum acceptable systematic LO phase errors. In fact theLO phases are equally spaced by exactly 45 only if the lockingsignal frequency is equal to the free-run frequency of the ringoscillator. As demonstrated in the Appendix, when the ring is


locked at frequency , the relative phase shift introduced byeach delay cell is given by

(1)

where is the free-run frequency. From (1), the relative phaseerror between consecutive LO signals is proportional tothe frequency offset between the locking signal and the free-runfrequency:

(2)

The LO phase error leads to a deviation from quadraturebetween the I & Q down converted signals. When the mixersare driven in fundamental mode, the LO signals, nominally inquadrature, bear a phase error of leading to the same erroron the base band down-converted signals. The same happenswhen the mixers are driven in sub-harmonic mode. In fact,referring to the LO phase sequence reported in Fig. 4 (bottom),we can rewrite the outputs as

(3)

showing a relative departure from quadrature still equal to .WiMedia UWB tolerates quadrature errors up to 20 in the

analog section when compensation is performed in the digitalbaseband [18], [19]. Even without effective correction in thedigital baseband, the required quadrature accuracy is still rel-atively relaxed, being a phase error of about 5 acceptable [20].Limiting the maximum quadrature error to 2.5 ( 0.044 rad) toaccount for other sources of error (like device mismatches andlayout asymmetries), from (2) the maximum tolerable frequencyerror between the locking frequency and the free-run fre-quency of the ring oscillator is 4.4%. This corresponds to alarge absolute frequency offset of 145 MHz and 203 MHzwhen the ring is tuned to the minimum and maximum channelfrequencies of 3.3 GHz and 4.62 GHz respectively (i.e. half thecarrier of ch1 in group 3 and ch3 in group 4). Due to temper-ature and supply variations, real-time calibrations in order torestore the nominal condition without exceeding the specifiedphase errors are required. Our design targets a fine tuning reso-lution of less than 20 MHz so as to maximize the tolerable fre-quency drift. From SpectreRF simulations the maximum sensi-tivities of the free-run frequency from temperature and supply

variations are 10 MHz and 5 GHz/V respectively. As a con-sequence, the maximum allowed temperature and supply vari-ation for a maximum frequency drift of less than 145 MHz arederived around or 30 mV, not mandating frequent cal-ibrations.

As shown in Fig. 5(a), the locking signal is provided by anadditional differential pair, shunting the first delay cell. Thedetailed schematic of the first cell is shown in Fig. 5(d). Thelocking range, i.e., the maximum frequency offset betweenthe locking and free-run frequency is set by the ratio be-tween the biasing currents and [21], [22]:

(4)

Both free-run phase noise suppression and settling time whenchanging the output frequency improve increasing the injectionratio [23]–[25]. To gain insight, Fig. 6 shows the sim-ulated phase noise of the oscillator in free-run and when lockedby a noiseless signal, for different ratios between and . Theresidual phase noise reduces as the ratio increases. We targeted afar-out phase noise below 140 dBc/Hz requiring higherthan 2/8. Fig. 7 shows the simulated output frequency transient(measured as the inverse of the time interval between consecu-tive zero crossings of the outputs) when the locking signal fre-quency is stepped, at , from channel 1 to channel 3 ofgroup 1 (i.e. from 3.432 GHz to 4.488 GHz) for three different

ratios. The time required to settle within 0.01% of thefinal value is 1.8 ns, 2.5 ns, 7.7 ns for equal to 1, 3/7, 1/9respectively. To achieve adequate phase noise suppression andto fulfill a frequency settling time lower than 9 ns with sufficientmargin, has been selected. A ratio larger than re-quired does not provide further benefits while, on the opposite,may lead to a non negligible systematic phase error between thegenerated waveforms. In fact injection of the locking signal inthe ring inevitably introduces a loop asymmetry. For this reason,particular care in the design of the first delay cell, reported inFig. 5(d), has been paid. The locking signal is provided by anadditional differential pair injecting current in the load of thefirst delay cell. To achieve good phase matching, the total cur-rent in the load impedance must match as close as possible thatof other stages. For this reason, the biasing current of the dif-ferential pair driven by the feedback signal has been reduced,compared to other stages. The selected ratio of 3/7 betweenand has been achieved by properly sizing the biasing tran-sistors ( and ). Transistors of the injecting and firstdifferential pairs have been proportionally sized, preserving thesame current density of the other cells. The locking signal isfed to the locking pair through AC coupling capacitors while, totrack the common-mode DC level of the other differential pairs,set by the static load voltage drop, the DC bias voltage is de-rived from the replica bias circuit ( in Fig. 5(c)) and appliedthrough resistors . Transistors are introduced in par-allel to the gates of the differential pair driven by the feedbacksignal to make the loading capacitance seen by the last stageequal to that loading the other stages. From post-layout simula-tions, the maximum systematic phase error, with the ring lockedat the free-run frequency, is 0.4 .


Fig. 6. Ring oscillator phase noise in free-run and when injection locked, fordifferent � �� ratios.

Fig. 7. Transient of the ring oscillator output frequency when the locking signaljumps from 3.432 GHz to 4.488 GHz.

IV. PHASE-LOCKED LOOPS AND MULTIPLEXER

A. Phase-Locked Loops

The on-chip PLLs, providing the locking signal throughthe multiplexer, are identical and deliver a programmableoutput frequency ranging from 3.30 GHz to 4.620 GHz with a132 MHz step. An integer-N architecture employing a refer-ence frequency of 66 MHz, shown in Fig. 8, has been selected.Frequency dividers are implemented with a divide-by-two cur-rent-mode-logic (CML) prescaler followed by a programmablepulse-swallow counter implemented with standard cells. Totalcurrent consumption of the frequency divider, mostly con-tributed by the CML stage, is 870 A. The schematic of theVCO is shown in Fig. 9(a). The voltage supply is set to 0.8 V,leaving enough headroom for a regulator (not implemented),working within the nominal supply of 1.2 V. Due to thelow selected supply, the oscillator is made of NMOS onlycross-coupled differential pair driving the resonant LC load.The inductor is a two-turns center tapped 1.8 nH differentialspiral with a quality factor ranging from 11 to 14 in the bandof interest. The oscillation frequency spans from 2.9 GHz to5.1 GHz in eight largely overlapped sub-bands. Fine tuning isachieved with accumulation-mode MOS varactors while band

Fig. 8. Block diagram of the PLL.

selection is implemented switching binary sized MOM capac-itors with 3 control bits. As shown in Fig. 9(a), the switchesare implemented with NMOS devices placed in the midpointof two tank capacitors. Minimum size inverters, driven by thesame switch control signal, set the drain and source voltage ofthe switches to the optimal value: when the switch is on, thedrain and source voltage is set to 0 V, maximizing the overdrivefor minimum on-resistance, while when the switches are turnedoff, the drain and source voltage rise to , reverse biasing thedrain and source to bulk junctions for minimum parasitic ca-pacitance [26]. To keep a constant voltage swing, the oscillatorbiasing current is regulated with a programmable tail currentsource. Maximum VCO current consumption is 3.2 mA, atthe minimum output frequency, where the impedance of theresonator is minimum. From simulations, phase noise is below

110 dBc/Hz at 1 MHz offset from the carrier.A particularly critical building block in low voltage PLLs is

the charge pump. Mismatch between the Up and Down currentsis a primary contributor of unwanted spurs which appear closeto the PLL output carrier [27]. Current mismatch is mainlydue to device channel length modulation and, achieving goodmatching over a large control voltage range, is troublesome.The schematic of the realized charge-pump is shown in Fig. 9(b)[28]. The Up and Down current sources are implemented withtransistors and respectively. Switches and ,driven by the signals DN and , control the two currentsources. A reference current is directly mirrored to theDown current generator. To compensate variations of the VCOtuning gain in each sub-band, the output current is made pro-grammable, from 50 A to 400 A, by changing the equivalentwidth of the diode connected device . The OpAmp forcesthe voltage at node X to follow the loop filter voltage. In thisway, the current in , which is then mirrored to the Up currentgenerator by means of , tracks the variations of the Downcurrent due to channel length modulation of . Dummydevices, and , are introduced to match the overdrivevoltages of the pairs – and – respectively. FromSpectre RF simulations the charge pump provides Up andDown currents matched within 3% for a tuning voltage rangingfrom 0.1 V to 1.1 V, when supplied by 1.2 V. The OpAmp isimplemented with parallel NMOS and PMOS input differentialpairs allowing a rail-to rail common-mode input voltage [27].The current consumption is 30 A. Capacitor Cc and resistorRz are introduced to stabilize the nested loop.


Fig. 9. (a) Voltage-controlled oscillator and (b) charge-pump with loop filter.

Fig. 10. Multiplexer schematic.

Fig. 11. Effect of the MUX input impedance variation on the free-run fre-quency of the LC VCO.

B. Multiplexer

The PLL outputs feed a three-inputs multiplexer (MUX)to select the appropriate locking signal for the ring oscillator,according to the WiMedia frequency hopping sequence. The

schematic diagram of the multiplexer is reported in Fig. 10. Itconsists of three differential pairs with stacked common-gatedevices. The gate voltages are set by the control signals (S1–S3)selecting the output current flowing in the shared load resis-tances . The VCOs in each PLL directly drive the MUXwithout any interface buffer. Minimizing VCO frequencychanges due to a variation of the MUX input impedance whenthe MUX is reconfigured is key. In fact the PLL would try to re-store the nominal VCO frequency with its time constant whichis much higher than the settling time of 9 ns, dictated by theWiMedia specifications for each frequency hop. To this extent,dummy branches, driven by complimentary control signals andmade of a replica of the load resistors and common-gate de-vices, have been introduced in the MUX. In this way, the outputcurrent from each differential pair is steered between the realoutput and the dummy loads, according to the control signals.The DC biasing point of the differential pair devices is constantand independent of the selected output, leading to negligibleinput impedance change and VCO pushing. The drawback ofthe adopted solution is a higher current dissipation because eachdifferential pair is always biased, even when the driving signalis not propagated to the MUX output. To gain insight in the


Fig. 12. Schematic of a reconfigurable Sub-Harmonic mixer with the RF transconductor and IF trans-resistance amplifier.

effectiveness of the proposed solution, Fig. 11 plots the VCOoutput frequency when the MUX output switches every 20 ns.The highest possible oscillation frequency, i.e., 4620 MHz,corresponding to half the center frequency of channel 3 ingroup 4, has been identified as the worst case for frequencypushing because the tank capacitance is minimum and thefrequency sensitivity to a variation of MUX impedance (mainlycapacitive) is maximum. From Fig. 11, without the dummybranches, the VCO frequency is down-shifted by 700 kHz(corresponding to about 150 ppm) when the VCO signal isselected as the MUX output, while no variations within 1 ppmare observed in presence of the dummy branches.

V. RECONFIGURABLE SUB-HARMONIC MIXERS

Noise and linearity requirements of the mixers are deter-mined by the receiver sensitivity and the interferers scenario.The WiMedia UWB standard assumes an overall noise figure(NF) of the receiver of 6.6 dB [5]. If an insertion loss of 2.5 dBis taken into account for a pre-filter, following the antenna,the front-end NF should be lower than 4.1 dB [29], [30]. TheLNA has not been implemented in this work. Specificationsfor the down-conversion stage are thus assumed based onLNA performances reported in the literature. A wide variety ofdifferent solutions, based on inductive degeneration, commongate, noise cancelling, various feedback configurations anddistributed gain stages have been recently presented [6], [7],[9], [31]–[34]. Among them, the most promising techniquesrely on resistive and reactive feedback topologies. Implementedin 90 nm CMOS, the resistive feedback LNA in [33] displays aNF dB over a frequency ranging from 0.5 GHz to 8.8 GHzwith a peak voltage gain of 25 dB. The 0.13 m CMOS LNAin [7], based on a transformer feedback configuration, fea-tures 15 dB gain with a NF ranging from 2.1 to 2.9 dB overthe 3.1 GHz to 10.6 GHz frequency band. Assuming 15 dBvoltage gain and 3 dB NF for the LNA, to achieve an overallfront-end double side-band NF of 4 dB the equivalent inputnoise voltage spectral density of the mixer must be lower than2.6 nV/sqrt(Hz).

The schematic of one of the realized mixers and inputtransconductor is shown in Fig. 12. Requiring two stacked

switching quads, the mixer core is passive for voltage roomsaving. The output current is collected by a trans-resistanceamplifier, followed by a common-drain buffer for measurementpurposes. The same transconductor feeds both I and Q mixers.The transconductance of the two differential pair devices is setto 30 mS, enough to fulfill the target equivalent input noisevoltage. The supply is provided through the center tap of adifferential load inductor acting as a choke. The switches ofthe mixers are relatively small (30 m/60 nm) presenting a lowinput capacitance of 40 fF. The LO waveforms are thereforebuffered by simple inverters, with a power consumption of3.1 mW at maximum frequency. With rail-to-rail square-wavesdriving waveforms, the passive switching quad negligiblycontributes to linearity degradation. Due to the wide IF-band-width required, the low input impedance of the trans-resistanceamplifier is realized with common-gate input devices. Theinput impedance is 50 while the input pole isset to 300 MHz to reject out-of band interferers. The load of thetrans-resistance amplifier is differential with the common-mode(CM) level set by PMOS current mirrors biased by a CM feed-back loop (not shown in the figure). The supply voltage is 1.2 Vand current consumption is 10 mA.

The MBOA-UWB standard does not specify any blockerstest. The analysis of the receiver linearity requirements, in a real-istic interferers scenario as reported in [29], suggests a receiverIIP3 higher than 9 dBm with blockers in the 5 GHz to 6 GHzband (such as IEEE802.11a and HiperLan2 or 5 GHz-ISM).Simulations provide a mixer IIP3 of 12 dBm. With 15 dB offixed LNA gain in front of the mixer, the input referred receiverIIP3 would be 3 dBm.

VI. EXPERIMENTAL RESULTS

The test chips have been realized in a 65 nm LP-CMOSprocess provided by STMicroelectronics. A die micrograph,with all the main building blocks highlighted, is shown inFig. 13. The complete chip draws 66 mA from 1.2 V supply.For testing, dies have been glued and bonded on PCB. Thedifferential RF input signal is provided by an Agilent signalsource and a broadband connectorized balun. Two 50 SMD


Fig. 13. Chip microphotograph.

resistors mounted on the PCB shunt the inputs of the demodu-lator to terminate the RF signals. The free run frequency of thering oscillator is digitally programmable between 3 GHz and5.6 GHz. The frequency locking range is 1.55 GHz, measureddriving the ring oscillator by an external signal source, whenthe free-run frequency is set to 4.3 GHz (e.g., in the middle ofthe tuning range).

Fig. 14 shows the measured conversion gain versus the RFinput frequency. From 3 GHz to 5 GHz, where the mixers workin fundamental mode, and in group 3, from 6.6 GHz to 8.1 GHz,where the mixers work in sub-harmonic mode, the conversiongain is 10 dB. A sudden decrease of 4 dB is observed in thelast group, attributed to the poor frequency response of PCB,bondwires and capacitance of the input pad. The measured IFbandwidth is 300 MHz and the equivalent input noise voltagespectral density is 2.3 nV/sqrt(Hz). No significant differencein equivalent input noise is observed between mixers operatedin fundamental or Sub-Harmonic modes. Out of band linearitytests have been performed according to [29]. With blockers at5.2 GHz and 5.8 GHz and the LO placed at 4.488 GHz (channel3 of group 1) the third order intermodulation product falls at anintermediate frequency of 112 MHz. Measured IIV3 is 1 dBV(11 dBm IIP3 on 50 ). Second order intermodulation test onfew samples, with interferers at 1.9 GHz and 5.2 GHz and theLO at 3.442 GHz (channel 1 of group 1), show an IIV2 higherthan 30 dBV (40 dBm IIP2 on 50 ).

Fig. 15 shows typical time-domain baseband quadratureoutputs after downconversion of an RF signal to 10 MHzintermediate frequency in fundamental (top) and sub-harmonic(bottom) modes. Phase errors, among several samples and fordifferent RF frequencies, is always below 2 .

Keeping low LO spur levels to avoid down-conversion ofundesired interferers, especially in the 5 GHz–6 GHz WLANband, is key. Fig. 16 shows the wideband spectrum at theoutput of the ring oscillator when it is locked to 3.960 GHz

Fig. 14. Measured conversion gain with the mixers operating in fundamentaland sub-harmonic modes.

Fig. 15. Time domain I&Q outputs at 10 MHz intermediate frequency.

by PLL2 while PLL1 and the external source, emulating thethird PLL, are 528 MHz apart on the two frequency sides. Nospurs are present in the 5 GHz–6 GHz WLAN range. Spurs attwice the frequency are very likely introduced by the secondharmonic distortion of the single-ended measurement buffer.The largest spurs, due to leakage of the two sides PLLs signals,are 43 dBc. Spurs very close to the synthesized frequency,which are below 50 dBc, are due to the reference signal ofthe PLL and its harmonics. No frequency push/pull effects areobserved between the two on-chip PLLs.

Phase noise measurements for the LO at 3.960 GHz fre-quency are shown in Fig. 17. The plot compares the phase noise


Fig. 16. Local Oscillator output spectrum when PLL2 locks the ring at 3.96GHz while PLL1 and the external PLL are 528 MHz apart.

Fig. 17. Phase Noise of the free running and injection locked ring oscillator at3.96 GHz carrier frequency.

at the output of the ring oscillator in free-running and when in-jection locked. When locked, the phase noise at 10 MHz offsetis reduced from 108 dBc/Hz to 128 dBc/Hz. The integratedphase noise, from 10 kHz to 100 MHz offset, is below .

A test of the demodulator settling time when the LO fre-quency hops between sub-channels in the same group is shownin Fig. 18. The LO frequency switches between 3.432 GHz and3.960 GHz while a constant frequency RF signal is downcon-verted to IF.

A settling time of the complete demodulator (synthesizer andmixers) of less than 6 ns has been measured. No significant dif-ference in settling time is observed between mixers operated infundamental or Sub-Harmonic modes.

Finally the performances of the complete demodulator aresummarized in Table I while Table II compares the frequencysynthesizer against alternative solutions for WiMedia UWB.The power consumptions, normalized to the number of coveredUWB bands, is calculated in the last column. The power dis-sipation reported for the presented realization includes also anestimate of the third (missing) PLL and the power consumedby the LO buffers driving the mixers. The proposed synthesizerdisplays the lowest power dissipation normalized to the numberof covered UWB channels.

Fig. 18. Demodulator settling time. The LO frequency is switched between3.432 GHz and 3.960 GHz while a fixed frequency RF signal is down-convertedto baseband.

TABLE IPERFORMANCE SUMMARY

VII. CONCLUSION

A quadrature demodulator based on mixers reconfigured be-tween fundamental and sub-harmonic operation modes has beenproposed to accomodate RF signals covering a wide frequencyband. The technique has been experimentally validated with testchips tailored to WiMedia UWB but can find applications alsoin other emerging wideband communications like software-de-fined and cognitive radios. A multi-stage ring oscillator injec-tion locked by multiplexed LC VCOs has been proposed to gen-erate the required fast hopping multiple LO phases. The realizedfrequency synthesizer displays minimum spur levels over a wideband, high spectral purity and low power dissipation. A com-parison with synthesizers in the literature demonstrates that theproposed technique for UWB demodulation leads to the lowestpower dissipation normalized to the number of covered chan-nels.


TABLE IICOMPARISON OF THE SYNTHESIZER PERFORMANCE AGAINST STATE OF THE ART

Area and power are calculated considering also the third PLL, not implemented on-chip. Power includes also buffers driving the mixers.

Fig. 19. Block diagram of the ring oscillator in Fig. 5 for calculation of the phase delay between consecutive output voltages.

APPENDIX

Fig. 19 shows the block diagram of the ring oscillator ofFig. 5. The differential pairs are represented by transconduc-tors driving the RC load impedances with time constant . Thelocking current is added to the feedback current from thefirst cell . The inversion stage in the feedback path in-troduces radians in the loop while each RC load introduces aphase shift between consecutive output voltages:

(A1)

A further phase shift is introduced in the loop by the vec-torial sum of and (Fig. 20) [21], [22]. The total loopphase must be zero (or an integer multiple of ). As a first steplet us consider the case of , i.e., the ring is oscillating infree run. In this case, from Fig. 20, and we have

(A2)

The free run frequency can be determined combining (A1)and (A2) and solving for :

(A3)

Fig. 20. Vectorial sum of the injected and feedback current of the ring oscil-lator.

When the ring is locked at the radian frequency ,and (A2) and (A3) can be rewritten as

(A4)

(A5)

Replacing and from (A5) and (A3) in (A4) and solvingfor leads to (1). Results predicted by Spectre RF simulationsand (1) are in good agreement over a large frequency range. A


Fig. 21. Comparison between calculated and simulated phase delay.

comparison between calculated and simulated phase delay be-tween consecutive output voltages in the ring oscillator designedin this work is shown in Fig. 21.

ACKNOWLEDGMENT

The authors thank STMicroelectronics for further support andin particular G.Betti, M.Bruccoleri, and F. Radice for fruitfuldiscussion.

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Andrea Mazzanti (S’01–M’06) received the Laureaand Ph.D. degrees in electrical engineering from Uni-versità di Modena and Reggio Emilia, Modena, Italy,in 2001 and 2005, respectively.

During the summer of 2003 he was with AgereSystems, Allentown, PA, on an internship. In 2005,he got a post-doctoral position from Università diPavia, Italy, working on CMOS RFICs for cell-phoneapplications. From 2006 to 2009, he was an AssistantProfessor at the Università di Modena and ReggioEmilia, Italy, teaching a course on advanced analog

IC design. In January 2010, he moved to the Faculty of Engineering of Univer-sità di Pavia. His main research interests cover device modelling and integratedcircuit design for high speed communications and millimeter-waves systems.In this field he has coauthored more than 60 conference and journal papers.Since 2008 he has served as a member of the technical program committee ofthe IEEE Custom Integrated Circuit Conference (CICC) and IEEE InternationalConference on IC Design and Technology (ICICDT).

Mohammad B. Vahidfar (S’05) received the B.S.and M.S. degrees in electrical engineering fromSharif University of Technology, Tehran, Iran, in2000 and 2002, respectively, and the Ph.D. degree inelectrical engineering from the University of Tehranin 2007.

From 1999 to 2002, he was with Emad Semicon-ductor as a senior analog designer developing CMOSchipsets for voiceband applications. He receivedthe Kharazmi Award on research and developmentin 2002. From 2004 to 2005, he worked on data

converters and delta-sigma DAC at Marsemai Co. From 2005 to 2007, he waswith Università di Pavia, Pavia, Italy, as a visiting student working on CMOSreconfigurable receivers. In 2007, he began a post-doctoral position withUniversità di Pavia, in cooperation with STMicroelectronics, Pavia, workingon UWB receivers and mmW circuits. Since January 2009, he has been withSiTune Corporation, San Jose, CA, working on highly integrated tuners forcable, mobile and satellite systems.

Marco Sosio was born in Tirano, Italy, in 1980. Hereceived the Laurea degree (summa cum laude) fromthe University of Pavia, Pavia, Italy, in 2005. Duringhis Laurea thesis, he studied high-dynamic-rangemixers. He received the Ph.D. degree in electricalengineering and computer science at the Universityof Pavia in February 2009.

His main research interests include analog and RFIC design for UWB communications and millimeter-wave applications.

Francesco Svelto (M’98) received the Laurea andPh.D. degrees in electrical engineering from the Uni-versità di Pavia, Italy, in 1991 and 1995, respectively.

During 1995–1997, he held an industry grant forresearch in RF CMOS. In 1997, he was appointedAssistant Professor at Università di Bergamo, and in2000, he joined Università di Pavia, where he is nowa Professor. His current interests are in the field ofRF and high-speed integrated circuits. Dr. Svelto hasbeen technical advisor of RFDomus Inc., a start-uphe co-founded in 2002 dedicated to highly integrated

GPS receivers. After merging with Glonav Inc. (Ireland), RFDomus has beenacquired by NXP Semiconductors in 2007. Presently he is the Director of a Sci-entific Laboratory, joint between Università di Pavia and STMicrolectronics,dedicated to research in Microelectronics, with emphasis to mm-wave systemsfor wireless communications, high-speed serial links and read-write channelsfor hard disk-drives.

Dr. Svelto is a member of the technical program committees of the IEEE In-ternational Solid-State Circuits Conference and has been a member of the IEEECustom Integrated Circuits Conference, Bipolar/BiCMOS Circuits TechnologyMeeting and the European Solid-State Circuits Conference. He served as Asso-ciate Editor of IEEE JOURNAL OF SOLID-STATE CIRCUITS (2003–2007), and asGuest Editor for a special issue on the same journal in March 2003. He was acorecipient of the IEEE JOURNAL OF SOLID-STATE CIRCUITS 2003 Best PaperAward.

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2104 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 10 ...ims.unipv.it/FIRB2006/pub/Mazzanti10a.pdf · The technique allows covering an RF bandwidth three times ... low-noise