20embedded system

7/24/2019 20embedded system

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EMBEDDED SOFTWARE

MEMORY DEVICE DRIVERS

G.MANASA

(14021D3614)

DEFINITION OF DEVICE DRIVERS:-

Most embeddedhardware requires some type of software initialization and management

The software that directly interfaces to hardware resources in the kernal is called a

DeviceDrivers

INTERFACE OF DEVICE DRIVERS:-

The main goal of device driver is to allow communication between

the operating system and the peripheral devices

It also provides a link between the kernel software and the user

software It!s important to achieve a sort of systematic way to do this

This makes the interface more recognizable for the user.

The driver has the responsibility of hiding the details of the hardware

from the operating system and" ultimately" from the user.


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CONCEPT OF DEVICE-DRIVERS:-

Device drivers are the software libraries that initialize the

hardware"and manage access to the hardware by higher layers of software

Device drivers are the liaison between the hardware and the operating

system" middleware" and application layers

Device drivers are typically considered either architecture specific or generic

# Device driver that is architecture specific manages the hardware that is

integrated into the master processor

$%ample :-

#rchitecture-specific drivers that initialize and enable components within a

master processor include on-chip memory" integrated memory

managers&MM's(" and floating point hardware

# device driver that is )enericmanages hardware that is located on the board

and not integrated onto the master processor

)eneric drivers include code that initializes and manages access to the

remaining ma*or components of the board" including board buses &I+," ,I"

,M,I#" etc(" off-chip memory &controllers" level-+. cache" /lash" etc("

and off-chip I01 &$thernet" 23-+4+" Display "Mouse" etc(


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/igure a shows a hardware block diagram of a M,567-based board" and

shows a systems diagram that includes e%amples of both M,567 processor-

specific device drivers" as well as generic device drivers

MEMORY DEVICE DRIVERS:-

#ll types of physical memory are two-dimensional arrays &matrices( made

up of cells addressed by a unique row and column" the master processor and

programmers view memory as a large one-dimensional array" commonly

referred to as the Memory Map

In the memory map" each cell of the array is a row of bytes &5 bits( and the

number of bytes per row depends on the width of the data bus &5-bit" 86-bit"

4+-bit" 69-bit"etc(

hen physical memory is referenced from the software;s point-of-view" it is

commonly referred to

as "logical memory and its most basic unit is the byte


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ADDRESS RANGE Accee! De"#ce PORT WIDT$

7%77777777 - 7%774///// /lash 21M =ank 8 4+ 4+

7%77977777 - 7%77>///// /lash 21M =ank + 4+

7%79777777 - 7%794///// D2#M 9 Mbyte &8Meg ? 4+-bit( 4+

7%7@777777 - 7%7@774/// M, Internal Memory Map 4+

7%7@877777 - 7%7@877774 =,32 - =oard ,ontrol A 3tatus2egister

4+

7%87777777 - 7%8>////// ,M,I# ,hannel 86

Table :-3#M


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In big endian mode bytes are accessed in the order of the highest

byte first" meaning that the

lowest byte is furthest to the right

The following pseudocode demonstrates implementation of various memory

management

routines on the M,567" specifically startup" disable" enable" and

writing0erasing functions in

reference to the architecture

These e%amples demonstrate how memory management can be implemented

on a more comple% architecture" and this in turn can serve as a guide to

understanding how to write memory management drivers on other processors

that are as comple%or less comple% than the M,567 architecture

configuring the MM'

INITIA%I&ING T$E MEMORY CONTRO%%ER AND CONNECTED

ROM'RAM :

The M,567 memory controller &shown in /igure 5-8@( is

responsibl for the control of up to eight memory

banks"interfacing to 32#M" $21M" flash $21M various

D2#M devices" and other peripherals &ie",M,I#(

Thus" in this e%ample of theM,567" on-board memory &/lash"

32#M" D2#M" etc( is initialized by initializing the memory

controller

The memory controller has two different types of subunits" the

general-purpose chip-select machine &),M( and the

userprogrammable machines &'Ms(" that e%ist to connect to

certain types of memory

The ),M is designed to interface to 32#M"$21M" /lash

$21M" and other peripherals&such as ,M,I#(" whereas the

'Ms are designed to interface to a wide variety of memory"

including D2#Ms

The pinouts of the M,567;s memory controller reflect the

different signals that connect these subunits to the various types

of memory /or every chip select &,3(" there is an associated

memory bank


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INTIA%I&ING T$E INTERNA% MEMORY MAP ON T$E MPC60:

The M,567;s internal memory map contains the architecture;s special purpose

registers&32s(" as well as dual-port 2#M" also referred to as parameter 2#M" that

contain the buffers of the various integrated components" such as $thernet or I+," for

e%ample 1n the M,567" it is simply a matter of configuring one of these 32s" the

Internal Memory Map2egister &IMM2( to contain the base address of the internal

memory map


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INITIA%I&ING T$E MM ON T$E MPC60 *

The M,567 uses the MM's to manage the board;s virtual memory

management scheme"

providing logical0effective to physical0real address translations" cache control

&instruction

MM' and instruction cache" data MM' and data cache(" and memory access

protections

The M,567 MM' &shown in /igure 5-+4a( allows support for a 9 )=

uniform &user( address

space that can be divided into pages of a variety of sizes" specifically 9 k="

86 k=" E8+ k=" o5 M=" that can be individually protected and mapped to

physical memory


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