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2056 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014 Simulation Study of the Trapping Properties of HfO 2 -Based Charge-Trap Memory Cells Francesco Driussi, Sabina Spiga, Alessio Lamperti, Gabriele Congedo, and Alberto Gambi Abstract— In this paper, the trapping properties of HfO 2 -based charge-trap cells have been extensively studied by means of a synergic use of material analysis, electrical characterization, and electrical and atomistic modeling. We assessed the impact of process conditions [i.e., postdeposition annealing (PDA)] on the material structure and the trapping behavior of the fabricated gate-stacks. Furthermore, we present reliable models for the HfO 2 structure and for the defects responsible for the electron trapping. We found that HfO 2 has a trap density comparable with that of SiN that depends on the PDA temperature. The HfO 2 traps are shallower in energy than SiN traps, but retention of memory cells is still sufficient, also because of a slightly larger electron affinity and a larger permittivity than SiN that allows thicker layers while preserving the equivalent oxide thickness of the gate-stack. Index Terms— Charge-trap (CT) memories, hafnium oxide, material analysis, modeling, trapping properties. I. I NTRODUCTION C HARGE-TRAP (CT) nonvolatile memory devices raised significant interest in the last decade since they appeared as promising candidates to extend floating gate (FG) tech- nology to sub-20-nm nodes, also thanks to the possibility to enable 3-D integration [1]–[3]. In particular, 3-D architectures allow for higher bit density by overlapping several memory layers or by vertical integration of the NAND string [3], extend- ing the scaling of the bit cost below the limits fixed by planar solutions. Furthermore, the easier and cost effective fabrication process of CT cells, combined with its compatibility with CMOS technology, makes them very attractive for embedded memories. A fundamental component of the CT cell structure is the trap rich layer, responsible for the charge trapping and hence of the memory effect [4]. Indeed, the trapping properties of the Manuscript received July 30, 2013; revised March 12, 2014; accepted April 2, 2014. Date of publication April 29, 2014; date of current version May 16, 2014. This work was supported in part by the EU FP7 GOSSAMER under Project 214431 through the IUNET Consortium and in part by the ISCRA-CINECA through the ATHLET Project HP10CU24TC. The review of this paper was arranged by Editor Y.-H. Shih. F. Driussi and A. Gambi are with the Department of Electrical, Management and Mechanical Engineering, University of Udine, Udine 33100, Italy (e-mail: [email protected]; [email protected]). S. Spiga and A. Lamperti are with the MDM Laboratory, Institute for Microelectronics and Microsystems–National Council of Research, Agrate Brianza 20864, Italy (e-mail: [email protected]; [email protected]). G. Congedo was with the MDM Laboratory, IMM-CNR, Agrate Bri- anza 20864, Italy. He is now with imec, Leuven 3001, Belgium (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2014.2316374 storage layer (typically made of silicon nitride, SiN) strongly impact the performance of the CT cells and many efforts have been made in the past to characterize and understand the physical processes involved in the trapping/detrapping of charge in the gate-stack of CT memories, with the aim to optimize the cell structure and materials [5]–[8]. In particular, the use of high-dielectric constant (high-k ) oxides allows to scale the equivalent oxide thickness (EOT) of the gate-stack without sacrificing the trapping efficiency [9]. Furthermore, high-k oxides are grown with atomic layer deposition (ALD) that is fully compatible with 3-D structure fabrication process. Finally, materials such as HfO 2 (k 16), not only demonstrated good trapping capabilities [10], [11], but are also largely used in scaled CMOS devices [1]. In this framework, the purpose of this paper is to assess the trapping properties of HfO 2 films exploited as trapping layers. In particular, we report a study of HfO 2 -based gate-stacks, that combines extensive material analysis, detailed electrical characterization together with electrical and atomistic simula- tions, with the aim to understand the physical nature of HfO 2 trapping mechanism and to investigate the dependence of this material on the design and fabrication process parameters. II. DEVICE FABRICATION AND MATERIAL ANALYSIS We integrated HfO 2 layers in TaN/Al 2 O 3 /HfO 2 /SiO 2 /Si (TAHOS) gate-stacks (device area is 8 × 10 4 cm 2 ) [11]. The tunnel oxide is a 4.5-nm thick thermally grown SiO 2 film, while the HfO 2 trapping layer, with a nominal thickness (t HfO 2 ) between 6 and 16 nm, and the Al 2 O 3 [16-nm thick as deposited and 14.5 nm after postdeposition annealing (PDA)] top oxide are deposited by ALD at 300 °C [10], [11]. The TaN top electrode was deposited by RF sputtering and patterned by optical lithography. A PDA was performed in N 2 atmosphere at 900 °C, 1030 °C, or 1100 °C for 60 s. The fabricated gate-stacks were characterized in terms of structural and chemical properties. Fig. 1 shows X-ray diffrac- tion (XRD), collected at fixed grazing incidence angle ω = in a XRD3000 instrument (Italstructure) equipped with Cu Kα X-ray source (wavelength 0.154 nm), a monochromator, and a curve position sensitive detector with angular resolution 0.029°. We used pseudo-Voigt functions for peak fitting after background subtraction. The XRD pattern in Fig. 1 shows that annealed films (with 16-nm HfO 2 ) exhibit the monoclinic crystalline HfO 2 phase, as clarified by the shown reference diffraction pattern from monoclinic HfO 2 powder [12], [13]. However, as we have pre- viously shown [11], the phase transition toward the monoclinic 0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

2056 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. … · 2014. 11. 24. · F. Driussi and A. Gambi are with the Department of Electrical, Management and Mechanical Engineering,

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Page 1: 2056 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. … · 2014. 11. 24. · F. Driussi and A. Gambi are with the Department of Electrical, Management and Mechanical Engineering,

2056 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014

Simulation Study of the Trapping Propertiesof HfO2-Based Charge-Trap Memory Cells

Francesco Driussi, Sabina Spiga, Alessio Lamperti, Gabriele Congedo, and Alberto Gambi

Abstract— In this paper, the trapping properties of HfO2-basedcharge-trap cells have been extensively studied by means of asynergic use of material analysis, electrical characterization, andelectrical and atomistic modeling. We assessed the impact ofprocess conditions [i.e., postdeposition annealing (PDA)] on thematerial structure and the trapping behavior of the fabricatedgate-stacks. Furthermore, we present reliable models for theHfO2 structure and for the defects responsible for the electrontrapping. We found that HfO2 has a trap density comparablewith that of SiN that depends on the PDA temperature. TheHfO2 traps are shallower in energy than SiN traps, but retentionof memory cells is still sufficient, also because of a slightly largerelectron affinity and a larger permittivity than SiN that allowsthicker layers while preserving the equivalent oxide thickness ofthe gate-stack.

Index Terms— Charge-trap (CT) memories, hafnium oxide,material analysis, modeling, trapping properties.

I. INTRODUCTION

CHARGE-TRAP (CT) nonvolatile memory devices raisedsignificant interest in the last decade since they appeared

as promising candidates to extend floating gate (FG) tech-nology to sub-20-nm nodes, also thanks to the possibility toenable 3-D integration [1]–[3]. In particular, 3-D architecturesallow for higher bit density by overlapping several memorylayers or by vertical integration of the NAND string [3], extend-ing the scaling of the bit cost below the limits fixed by planarsolutions. Furthermore, the easier and cost effective fabricationprocess of CT cells, combined with its compatibility withCMOS technology, makes them very attractive for embeddedmemories.

A fundamental component of the CT cell structure is thetrap rich layer, responsible for the charge trapping and henceof the memory effect [4]. Indeed, the trapping properties of the

Manuscript received July 30, 2013; revised March 12, 2014; acceptedApril 2, 2014. Date of publication April 29, 2014; date of current versionMay 16, 2014. This work was supported in part by the EU FP7 GOSSAMERunder Project 214431 through the IUNET Consortium and in part by theISCRA-CINECA through the ATHLET Project HP10CU24TC. The reviewof this paper was arranged by Editor Y.-H. Shih.

F. Driussi and A. Gambi are with the Department of Electrical, Managementand Mechanical Engineering, University of Udine, Udine 33100, Italy (e-mail:[email protected]; [email protected]).

S. Spiga and A. Lamperti are with the MDM Laboratory, Institutefor Microelectronics and Microsystems–National Council of Research,Agrate Brianza 20864, Italy (e-mail: [email protected];[email protected]).

G. Congedo was with the MDM Laboratory, IMM-CNR, Agrate Bri-anza 20864, Italy. He is now with imec, Leuven 3001, Belgium (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2014.2316374

storage layer (typically made of silicon nitride, SiN) stronglyimpact the performance of the CT cells and many effortshave been made in the past to characterize and understandthe physical processes involved in the trapping/detrapping ofcharge in the gate-stack of CT memories, with the aim tooptimize the cell structure and materials [5]–[8].

In particular, the use of high-dielectric constant (high-k)oxides allows to scale the equivalent oxide thickness (EOT)of the gate-stack without sacrificing the trapping efficiency [9].Furthermore, high-k oxides are grown with atomic layerdeposition (ALD) that is fully compatible with 3-D structurefabrication process. Finally, materials such as HfO2 (k � 16),not only demonstrated good trapping capabilities [10], [11],but are also largely used in scaled CMOS devices [1].

In this framework, the purpose of this paper is to assess thetrapping properties of HfO2 films exploited as trapping layers.In particular, we report a study of HfO2-based gate-stacks,that combines extensive material analysis, detailed electricalcharacterization together with electrical and atomistic simula-tions, with the aim to understand the physical nature of HfO2trapping mechanism and to investigate the dependence of thismaterial on the design and fabrication process parameters.

II. DEVICE FABRICATION AND MATERIAL ANALYSIS

We integrated HfO2 layers in TaN/Al2O3/HfO2/SiO2/Si(TAHOS) gate-stacks (device area is 8 × 10−4 cm2) [11].The tunnel oxide is a 4.5-nm thick thermally grown SiO2film, while the HfO2 trapping layer, with a nominal thickness(tHfO2) between 6 and 16 nm, and the Al2O3 [16-nm thick asdeposited and 14.5 nm after postdeposition annealing (PDA)]top oxide are deposited by ALD at 300 °C [10], [11]. The TaNtop electrode was deposited by RF sputtering and patterned byoptical lithography. A PDA was performed in N2 atmosphereat 900 °C, 1030 °C, or 1100 °C for 60 s.

The fabricated gate-stacks were characterized in terms ofstructural and chemical properties. Fig. 1 shows X-ray diffrac-tion (XRD), collected at fixed grazing incidence angle ω = 1°in a XRD3000 instrument (Italstructure) equipped with Cu KαX-ray source (wavelength 0.154 nm), a monochromator, anda curve position sensitive detector with angular resolution0.029°. We used pseudo-Voigt functions for peak fitting afterbackground subtraction.

The XRD pattern in Fig. 1 shows that annealed films (with16-nm HfO2) exhibit the monoclinic crystalline HfO2 phase,as clarified by the shown reference diffraction pattern frommonoclinic HfO2 powder [12], [13]. However, as we have pre-viously shown [11], the phase transition toward the monoclinic

0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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DRIUSSI et al.: SIMULATION STUDY OF THE TRAPPING PROPERTIES 2057

Fig. 1. XRD pattern of a representative annealed sample, showing monocliniccrystalline HfO2 phase. Inset: γ -Al2O3 crystalline phase is highlighted.

Fig. 2. (a) and (b) ToF-SIMS depth profiles of Al2O3(16)/HfO2(16)/SiO2(4.5)/Si structures (nominal thickness in nanometer) as deposited and afterannealing at 900 °C, 1030 °C, and 1100 °C: Al, 30Si, and HfO ion intensitiesare plotted. (c) Hf intensity ratio and (d) Si intensity ratio evolution forstructures integrating different tHfO2 as function of the annealing temperature.

HfO2 phase exists at increasing tHfO2 and upon annealing,accompanied by an improved degree of crystallization, assuch, the 6-nm thick HfO2 exhibits different crystallizationwith respect to the ticker layers [11]. We recall that the peakintensity may differ in our case with respect to the referencepowder diffraction pattern, as we are dealing with thin films,where preferential orientation may develop.

Further, XRD also gives evidence of Al2O3 crystallizationin its γ -phase upon annealing, as clearly seen by the presenceof the peak at ≈67°, resulting from the fitting of the XRDpattern, as shown in the inset of Fig. 1.

With respect to elemental diffusion and interface stability,we collected time of flight secondary ion mass spectrometry(ToF-SIMS) depth profiles using an ION-TOF IV instrumentin negative polarity, using 0.5-keV Cs+ for sputtering, 25-keVGa+ for analysis [14], and we normalized ion intensities to30Si intensity in the substrate. As shown in Fig. 2(a) and (b) for

a representative sample, Hf diffusion in Al2O3 plus Al and Sidiffusion in HfO2 onset at 1030 °C and are evident after1100 °C annealing. Remarkably, diffusion is limited to theregion close to the interfaces at 1030 °C and extends into thelayers at 1100 °C only.

To give an indication on the influence of element diffusionin affecting the interface, we calculated the ratio of HfOintensity after annealing over the HfO intensity in the as-deposited films (called Hf intensity ratio), at Al2O3/HfO2interface, identified by the quick linear increment of HfO2signal, which corresponds to a sputtering time of about 150 s,depending on HfO2 thickness [dashed vertical line at ≈150-ssputtering time in Fig. 2(a), as guide to the eyes] for sampleswith different tHfO2 and annealed at 900 °C, 1030 °C, or1100 °C.

Fig. 2(c) shows that Hf intensity ratio is quite similarto the as-deposited reference value for all films at 900 °C,indicating that the interface remains substantially unaltered.At higher temperatures, two behaviors can be seen: 1) thethicker HfO2 samples (16 nm) show only slight changes in theHf intensity ratio and 2) for devices integrating a thin HfO2,the Hf intensity ratio appreciably increases, especially after1100 °C annealing. As such, element diffusion takes place,with intermixing, thus destabilizing the interface, as seen con-sidering Al and Si intensity profile in Fig. 2(b). Remarkably,at 1030 °C such intermixing seems not so evident.

Furthermore, tHfO2 is effective in mediating the HfO2 andAl2O3 intermixing: the thinner the HfO2 layer is, the higherthe volume substantially interested by mixing with Al2O3is, as observed in Fig. 2(c). A possible explanation of suchobserved Al2O3/HfO2 interdiffusion may rely on the differentcrystallinity of thinner HfO2 films. Similarly, we calculatedthe Si intensity ratio [defined as for HfO2 intensity ratio,but considering 30Si intensity, Fig. 2(d)] close to HfO2/SiO2interface [dashed vertical line at ≈260-s sputtering time inFig. 2(b)]. No appreciable change of Si intensity ratio is seenas a function of HfO2 thickness and temperature, except forthe case of 6-nm HfO2 and above 1030 °C PDA, where Sidiffusion should be considered.

III. MODELING OF HfO2 TRAPPING LAYERS

With the aim to understand the trapping properties of thefabricated HfO2 layers and their dependence on the fabricationconditions, we made use of electrical and atomistic models tointerpret the experimental results.

A. Electrical Model

For the simulation of the electrical characteristics of TAHOSdevices, we used the numerical model described in detailsin [15]. The model is 1-D and calculates the electrostatics inthe vertical direction across the cell (from the gate to substrate)self-consistently with the in and out electron tunneling fluxesto the substrate. Fig. 3 shows the band alignment amongdifferent materials and the effective tunneling masses (m∗)that have been used for the simulation [16]. Band alignmentand m∗ for the Al2O3 layer have been validated also bycomparison between simulations and experiments of tunneling

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2058 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014

Fig. 3. Schematic energy band alignment of the TAHOS stack used in themodel. m∗ is the effective tunneling mass and m0 is the free electron mass.ET is the energy depth with respect to the CB bottom of HfO2 traps.

current (not shown) and are in agreement with the γ -phase ofAl2O3 evidenced by the XRD of Fig. 1.

Inside the HfO2 film, we assumed trapping mainly dueto a bulk effect [17]–[19] and the model accounts for thedrift-diffusion transport in the conduction band (CB) andthe Shockley-Read-Hall (SRH) generation/recombination, toallow the calculation of the trapped charge profile [20]. Themodel accounts also for the charge loss toward the gate, hence,in the simulations, trapped electrons can tunnel out of trapsthrough the Al2O3 film.

Concerning the SRH generation/recombination inside HfO2,Poole–Frenkel emission is considered, while the capture of anelectron traveling in the CB is modeled through the capturecoefficient CC , that allows to calculate the electron capture rate(RC , trapped electrons per second) from the concentration offree traps in HfO2

RC (x) = CC [NT − nT (x)] (1)

where NT is the trap density, nT is the trapped electron density,and x the position along the HfO2 thickness [15].

In [10], we showed that such capture process stronglydepends on the average energy (w) of electrons. In particular,the larger the w is, the lower the probability that the HfO2layer traps the electron traveling in the CB is. To model thiseffect, we assumed an empirical exponential dependence onw of the capture coefficient

CC (x) = C0 · exp {−r · [w(x) − w0]} (2)

where r is an empirical parameter, while C0 is the capturecoefficient for the electrons at the bottom of the CB and withaverage energy w0 [10].

The fabricated TAHOS stacks feature a thick SiO2 layerand hence Fowler–Nordheim tunneling takes place during pro-gramming [Fig. 4(a)]. This means that the injected electronsreach the HfO2 with high energy with respect to the bottomof the CB. In addition, w is larger for larger VG and thisstrongly reduces CC and the capability of the HfO2 traps tocapture the high-energetic injected electrons. However, whiletraveling in the CB, the electrons relax their energy becauseof scattering events [21] and we model this process with afirst-order energy balance expression, that considers an average

Fig. 4. (a) Energy band diagram of the TAHOS cell during programming atVG = 18 V (t = 100 μs). Injected electrons have high energy with respectto the CB minimum. (b) Indicative energy relaxation calculated with (3) (forconstant field conditions inside the HfO2 film, F = 5 MV/cm), while electronsare traveling in the CB of HfO2. (c) Simulated trapped charge distributionalong the trapping layer thickness for the 16-nm HfO2 cell programmed for1 ms at VG = 18 V. We set λ = 1.1 nm and r = 3.5 eV−1.

equilibrium velocity for the electrons [22], [23]

dw

dx= 3

5q F(x) − w − w0

λ(3)

where F(x) is the electric field at the position x inside thetrapping film, λ is an energy relaxation length that summa-rizes the effect of the different scattering events occurringin the CB of the HfO2 film, q is the elementary charge,and w0 is the average energy of an equilibrium distribution.In Fig. 4(b), we show the w evolution along the HfO2thickness for different λ values and for a constant field in thelayer.

The effect of the energy dependent trapping in HfO2 isshown in Fig. 4(c), where a typical profile of the trappedcharge is reported. Near the tunnel oxide, a very low-chargeconcentration (nT ) can be seen, while nT increases at thecenter of the trapping layer [24]. Near the top oxide thereis again a decrease of nT because of the few CB electronsreaching the last part of the layer and of the tunneling towardthe gate. It is worth noting that the part near the tunnel oxidethat shows very small nT do not essentially participate tothe trapping process [19]. Indeed, this part limits the trappingcapability of the layer and its impact is much larger in cellswith thin HfO2 [25]. This can be an important constraint in theviewpoint of the vertical scaling of the cell, since it can limitthe minimum physical thickness of gate-stacks. In this respect,using high-k materials (e.g., HfO2), it is possible to scale thecell EOT, while maintaining a trapping layer thickness thatensures good program efficiency [10].

We calibrated C0 = 5 × 108 cm−3 s−1 by comparingsimulations and experiments of the programming of CT cellswith thin tunnel oxide [15], because, in this case, programmingoccurs by direct tunneling. Hence, the electrons are essentiallyinjected at the bottom of the CB of the trapping layer and thetrapping is expected to be uniform along the layer thickness.Furthermore, we calibrated λ and r by comparing the modelwith programming experiments in FN conditions. In particular,by assuming λ = 1.1 nm and r = 3.5 eV−1, we obtained goodagreement between the model and the programming curves

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DRIUSSI et al.: SIMULATION STUDY OF THE TRAPPING PROPERTIES 2059

Fig. 5. (a) Measured (symbols) and simulated (dashed lines) program curvesof 16-nm HfO2 device (900 °C PDA) for different VG . (b) Measured programcurves of 6-nm HfO2 devices annealed at different temperatures.

of TAHOS and MANOS devices with different gate-stackcomposition [10], [11].

B. Atomistic Model for Defects in HfO2

To corroborate the results of the electrical simulation regard-ing the trapping properties of HfO2 layers, we made use ofdensity functional theory (DFT) calculations to explore thenature of the HfO2 traps. For the simulations, performedwith the SIESTA code [26], we adopted the spin-polarizedDFT in the generalized gradient approximation and thePerdew–Burke–Ernzerhof exchange–correlation functional, inagreement with previous works on HfO2 [27], [28]. The coreelectrons have been represented by means of Troullier–Martinpseudopotentials. The simulated super cell is of 96 atoms andwe used the DZP basis set with an energy shift of 50 meVfor each species and a mesh cutoff of 100 Eh . More detailson the simulation framework can be found in [8] and [29].In agreement with the results of XRD, we used the monoclinicstructure to simulate the HfO2.

Since the oxygen vacancies are generally indicated as thephysical origin of HfO2 traps, defects in the HfO2 structurehave been created by removing one of the threefold or fourfoldcoordinated O atoms from the super cell (i.e., creating struc-tures with 95 atoms) [27], [30]. To understand the electricalproperties of these defects, we calculated the total densityof states (DOS) for the HfO2 structure with O vacancies indifferent charge states [8].

IV. EXPERIMENTAL AND SIMULATION RESULTS

Programming and retention characteristics of the fabricatedTAHOS cells have been measured and studied by means ofthe electrical and atomistic models. In particular, the TAHOSoperation has been characterized as a function of the HfO2thickness and PDA temperature.

A. Program Characteristics

Fig. 5(a) shows measured (symbols) and simulated (dashedlines) typical programming curves of TAHOS with 16-nmthick HfO2 annealed at 900 °C. Fig. 5(b), instead, compares

Fig. 6. (a) Measured (solid) and simulated (dashed) program curves of 6-nmHfO2 device (900 °C PDA). (b) Charge distribution inside the HfO2 layerduring the simulation in panel (a) for NT = 4.2 × 1019 cm−3. Differentcolors correspond to different programming times, ranging from 1 μs to 1 s.

Fig. 7. (a)–(c) Measured (symbols) and simulated (lines) program curves of1030 °C PDA devices. (d) NT extracted from the fitting of the experimentalprogram curves of devices with different tHfO2 and PDA temperatures. Notethat, although NT is larger in the thinner HfO2, the reduced thickness andthe nonuniform trapping highlighted in Fig. 4(c) lead to smaller �VFG (c)with respect to devices with thicker HfO2 (a, b).

the programming curves of 6-nm HfO2 samples annealed atdifferent PDA temperatures. The modeling approach describedin Section III-A allowed us to reproduce well the experimentalprogramming characteristics of all the TAHOS featuring dif-ferent tHfO2 and exposed to different PDAs [Figs. 5(a), 6(a),and 7(a)–(c)] [10], [11].

To reproduce the program curves, we used the trap density(NT ) as a fitting parameter [Fig. 6(a)]. Indeed, the slightflattening of the curves seen for large flatband voltage shifts(�VFB), that is more pronounced in the samples with thethinnest HfO2 [6 nm, Fig. 5(b)], is due to the saturationof the number of available traps in the trapping layer [11].This is clearly shown by the trapped charge profiles (nT )shown in Fig. 6(b): for the longer programming times (t),nT saturates at the trap density value NT , thus reducing theprogramming speed. This effect allowed us to extract the trapconcentration of the fabricated HfO2 films, namely, we fittedthe program experiments at large gate voltages (VG ) of all theavailable samples [Fig. 7(a)–(c)], thus obtaining the completecharacterization of the trap density as a function of tHfO2

and PDA temperature. We remark that, in the simulationsof Figs. 6 and 7, we did not change any model parameterexcept for NT . In Fig. 7(d), we have reported the extracted

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2060 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014

Fig. 8. Measured (black lines) and simulated (red symbols) programcharacteristics of 6-nm HfO2 device (1100 °C PDA). (a) Trap density is usedas fitting parameter. (b) Tunneling mass in Al2O3 is used as fitting para-meter. In this second case, we estimated NT = 1020 cm−3, a value inagreement with the trend with PDA temperature.

NT values for different HfO2 thickness and for the samplesannealed at 900 °C and 1030 °C. In the case of 900 °C PDA,all the HfO2 films have the same trap density (NT = 4.2 ×1019 cm−3 [24]), irrespective of tHfO2. This result is consistentwith the findings of ToF-SIMS analysis. Fig. 2 highlightedthat diffusion in HfO2 film is quite limited, evidencing agood stability of the material, hence similar trap densities areexpected for different tHfO2.

For 1030 °C PDA, instead, NT increases as tHfO2 decreases[Fig. 7(d)]. This reflects the larger �VFB in 6-nm cellsannealed at 1030 °C with respect to 900 °C PDA devices[Fig. 5(b)]. The PDA at T ≥ 1030 ◦C enhances Al diffusioninside the HfO2 [Fig. 2(a)], that is even larger in the thinnestlayers, thus inducing a thickness dependent Al diffusion [11].This Al incorporation could affect the formation of oxygenvacancies [31], which are considered the responsible forcharge trapping [30]. Hence, the NT dependence on tHfO2

could be related to this diffusion phenomena enhanced by1030 °C PDA in thin films.

It is also worth to note that the good agreement betweenthe model and experiments validates the physical picture ofa trapping in HfO2 mainly contributed by a bulk effect inboth 900 °C and 1030 °C PDA cells. However, it is notpossible to exclude that the increased overall trap density inthin films (1030 °C PDA) could also be partly related to alarger contribution of the interfaces, where additional trapscould be created during the diffusion phenomena [32], [33].

Fig. 5(b) shows that the cells annealed at 1100 °C exhibitan even larger flattening of the experimental curves at long t(black line), which is not due to the saturation of the availableHfO2 traps only. Indeed, Fig. 8(a) shows that good agreementbetween the model and the experiment cannot be achievedby varying NT only. At low t , high NT (larger than for1030 °C PDA) would be needed to match the experimen-tal curve [Fig. 8(a), red squares]. Instead, to reproduce theflattening of the program curve at long t , low NT wouldbe necessary (red diamonds). Better agreement is found bykeeping a large NT value (in the order of 1020 cm−3 [34], [35],hence preserving the NT trend on PDA temperature), whilemimicking the effect of a leaky top dielectric by reducing the

Fig. 9. Measured (symbols) and simulated (lines) retention characteristic of10-nm HfO2 device (900 °C PDA) at different temperatures.

Fig. 10. �VFB loss after 105 s during retention test at 200 °C in the differentsamples. Cells that underwent 1100 °C PDA show degraded retention.

tunneling mass (m∗) of the Al2O3 layer. This enhances thecharge loss through the Al2O3 by increasing the out-tunnelingof electrons trapped in the HfO2 bandgap and the loss of thecharge traveling in the HfO2 CB. These results suggest thatthe Al2O3 layer of 1100 °C PDA devices is more leaky thanin samples annealed at lower temperatures and the programspeed reduction is due to substantial charge loss toward thegate [4]. The leakage is possibly caused by a trap assistedtunneling (TAT) current through the top oxide stemming fromthe Hf and Si diffusion into the Al2O3, as showed in Fig. 2for the 1100 °C PDA. This picture is also supported bythe poor retention of the 1100 °C PDA cells discussed inSection IV-B.

B. Retention Characteristics

Retention curves from the programmed state have beenmeasured at various temperatures up to 2 × 106 s starting froma �VFB of about 5.5 V. Fig. 9 shows typical retention curvesof cells with 10-nm HfO2 devices exposed to 900 °C PDA(symbols), while Fig. 10 shows the �VFB loss during retentiontests at 200 °C of the different fabricated gate-stacks. Theretention characteristics of TAHOS stacks improve for largertHfO2. Furthermore, while no or slight difference is observedin the retention of devices annealed at 900 °C or 1030 °C, thePDA at 1100 °C leads to a significant retention degradationof TAHOS stack for all tHfO2 . These results corroborate thefindings of material analysis that show 1030 °C PDA is still notcritical for the gate-stack integrity. For the 1100 °C samples,

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Fig. 11. Arrhenius plot of retention times obtained from the experiments ofFig. 9 (solid lines) and simulations (dashed lines). Experimental retentiontimes are extracted for different target �VFB. Simulations consider twodifferent ET values.

Fig. 12. Simulated DOS and corresponding energy levels showing theelectron states for neutral (D0) and negatively (D−) charged defects inducedby the vacancy of fourfold (a, b) and threefold (c, d) coordinated O atoms,which are believed to be the dominant traps in HfO2. (b) and (d) Chargingof defects is done by adding one electron to the neutral state. Note that inboth D0 and D−, the energy states identified by the peaks in the DOS in thecentral part of the bandgap lie below the Fermi level (dashed line) and, hence,are filled by two electrons. In the D− states, shallower energy states appearin the bandgap and are filled by the added electron, indicating its trapping.ET indicates the trap depth of the two defects. (e) Fourfold and threefoldcoordinated O atoms in monoclinic HfO2.

instead, their poor retention confirms the hypothesis of largeTAT through the top oxide put in evidence by the study of theprogram characteristics in Section IV-A.

Following the approach used to study SiN traps in [8]and [15], we compare experimental retention tests (Fig. 9,symbols) with simulations (lines) performed by assumingdifferent trap energy depths (ET , see Fig. 3), to extract theelectrical characteristics of HfO2 traps. The Arrhenius plotsof measured (solid lines) and simulated (dashed) retentiontimes in Fig. 11 shows that the best agreement (i.e., sameactivation energy) between the model and experiments is foundfor ET = 0.5 eV, which is smaller than that for SiN traps [8].

C. Atomistic Simulations of HfO2 Traps

To confirm the latter result on the trap energy depth, weperformed DFT simulations. Fig. 12 shows the total DOS forthe monoclinic HfO2 with O vacancies calculated in differentcharge states. In this figure, a smearing Gaussian functionwith 0.15-eV width has been convoluted with the DFT results.In neutral conditions [Fig. 12(a) and (c)], both the vacancies of

Fig. 13. (a) Comparison between measured (symbols) and simulated (lines)retention curves for different assumed HfO2 EA and trap depths. The deviceis the 10-nm HfO2 cell (900 °C PDA). (b) Measured (symbols) and simulated(lines) current–voltage characteristics of a gate-stack with 2.1-nm SiO2 and4.2-nm HfO2. The simulations consider different HfO2 EA. At low gatevoltage (VG ) the experiments show a tail due to TAT that have not beenincluded in the simulations.

fourfold (e, O-IV) and threefold (e, O-III) coordinated O atomsshow energy states in the central part of the bandgap. However,they lie below the Fermi level (dashed line) and they are filledby electrons, hence the electrons injected from the substrateduring programming cannot be trapped there [30], [36]. Whencharging the defects [Fig. 12(b) and (d)] with the addition of anelectron to the simulated structure (95 atoms), all the electronstates change their energy [5], [8] and new states appearin the upper part of the bandgap. These are essentially thestates that trap the electrons injected during programming and,hence, responsible of the memory effect of the TAHOS stack.Therefore, these states govern the retention of the TAHOScells [5], [8].

As shown in Fig. 12(b) and (d), the energy depth of thestates responsible for trapping depends on the type of defectand in particular we found ET � 0.6 eV for O-IV trapsand ET � 0.2 eV for O-III traps. In this respect, O-IIIdefects have too shallow states to ensure good retention andhence the important defect in the memory operation of TAHOSare the O-IV vacancies [30], [36]. This picture is confirmedby the fairly good agreement between the ET values extractedby the electrical model in Fig. 11, by the DFT simulations andby experimental work in [37].

In Fig. 3, the energy level of trapped electrons, and hencethe energy barriers seen by these latters, are defined by bothET (referred to the CB bottom) and the HfO2 electron affinity(EA) value. To further verify the extracted ET value, weinvestigated the impact of the EA value assumed in the modelon the tunneling currents responsible for the charge loss.Fig. 13(a) shows the comparison between the experimentalretention curves and the model, when assuming different EAand ET values. In particular, the measurement (symbols)cannot be reproduced by changing EA only (green line).Instead, when compensating the EA variation with a differentET value, it is possible to obtain retention times similar to themeasured ones. However, the simulated curve is steeper thanthe experiment (blue line). The assumed EA value directlyimpacts the slope of the simulated characteristics and the bestagreement with the experiments is found for EA = 2.2 eV(thus assuming also ET = 0.5 eV, red line).

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2062 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014

To confirm this result, we extracted the EA value alsoby an independent technique. We compared the experimental[Fig. 13(b), symbols] and simulated (lines) current–voltagecharacteristics of a gate-stack composed by a 2.1-nm SiO2layer and a 4.2-nm HfO2 film, both of which were fabricatedin similar process conditions with respect to TAHOS stacks.We used a stack with a thin HfO2 and without Al2O3 toobtain measurable current values and to avoid trapping effectsin the device. The simulations have been performed with themodel of [38], using EA as a fitting parameter. We extractedalso in this case EA = 2.2 eV. This value is slightly largerthan for reference SiN [15] and it is in agreement with theliterature [16], [27].

V. CONCLUSION

The TAHOS stacks for memory applications have beenfabricated. During processing, the cells underwent PDA atdifferent temperatures. The use of extensive device charac-terization, including material analysis and electrical measure-ments, and of advanced modeling techniques, as physics-basedelectrical and DFT models, allowed us to assess the physicaland electrical characteristics of the fabricated HfO2 trappinglayers. In particular, the trapping properties and the electricaloperation of the TAHOS stacks have been understood asa function of the HfO2 thickness and PDA temperature.

We showed that elemental diffusion through the gate-stackis enhanced by the PDA temperature and it has a larger impacton cells with thin HfO2 layers. On one hand, this diffusion canincrease the trap density of HfO2 films, but, on the other handcan degrade the interfaces (between the different layers) andthe top oxide, leading to TAT leakage that reduces the programefficiency and the retention of the cell. In this respect, weshowed that 1030 °C PDA is the best compromise to ensuregood HfO2 trapping properties while preserving the insulatingproperties of the Al2O3 top layer.

We made use of the information provided by the structuraland chemical analysis to obtain reliable models for the HfO2traps. The comparison with electrical measurements allowedus to identify the origin of the electron trapping. In particular,the vacancies of fourfold coordinated O atoms in the HfO2structure are the responsible for the memory effect, inducingan electron trapping at an energy depth of 0.5–0.6 eV withrespect the CB bottom. Furthermore, the simulation studyallowed us to assess the material parameters, such as the EA,for reliable, and consistent modeling of HfO2.

Although the identified HfO2 traps are shallower withrespect to those of standard SiN, HfO2 can ensure sufficienttrapping capabilities for memory devices (Fig. 10), also in theviewpoint of a slightly larger EA and a larger permittivity thanSiN, that allows to integrate thicker layers while preserving theEOT of the gate-stack [11].

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Francesco Driussi received the Ph.D. degree inelectronic engineering from the University of Udine,Udine, Italy, in 2004.

He is currently a Research Associate with the Uni-versity of Udine. He has co-authored more than 60publications. His current research interests includenonvolatile memories, including the characterizationand modeling of charge trap cells, characterizationand modeling of MOSFET devices and grapheme-based devices.

Sabina Spiga received the Ph.D. degree in materialscience from the University of Milano, Milano,Italy.

She is currently a Researcher with LaboratorioMDM, IMM–CNR, Agrate Brianza, Italy, and is incharge of the development of materials and emergingconcepts for nonvolatile memory devices and neuro-morphic computation.

Alessio Lamperti received the M.Sc. and Ph.D.degrees from Politecnico di Milano, Italy.

He is a Research Engineer with Laboratorio MDM,IMM–CNR, Agrate Brianza, Italy. He mainly usessecondary ions mass spectrometry, and X-ray reflec-tivity and diffraction. His current research interestsinclude the structural and physicochemical charac-terization of nanoscaled metal and dielectric films,multilayers for nanoelectronics and spintronics, andtheir thermal stability in CMOS process integration.

Gabriele Congedo received the M.S. degree inmaterials engineering from University of Salento(Lecce, Italy) and the Ph.D. degree in fabrication andcharacterization of high-k dielectrics/metal gates forTANOS charge trapping memories from the MDMLaboratory, CNR–IMM, Agrate Brianza, Italy, in2007 and 2011, respectively.

He joined imec, Leuven, Belgium, in 2012, wherehe is a Post-Doctoral Researcher, involved in elec-trical evaluation of 3-D SONOS Flash memories.

Alberto Gambi received the Ph.D. degree in indus-trial chemistry from the University of Bologna,Bologna, Italy, in 1971.

He was Professor at University of Venezia. He iscurrently a Full Professor of Physical Chemistry atUniversity of Udine. His current research interestsinclude the study of molecular properties both the-oretically and experimentally.