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2019 16th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE) Mexico City, Mexico. September 11-13, 2019
Comparison of Two Internal Miller CompensationTechniques for LDO Regulators
F. Montalvo-GaliciaElectronics Department
INAOETonantzintla, Puebla, Mexico
G. Diaz-ArangoElectronics Department
INAOETonantzintla, Puebla, Mexico
gerardo [email protected]
C. Ventura-ArizmendiElectronics Department
INAOETonantzintla, Puebla, Mexico
B. CalvoGroup of Electronic Design (I3A)
Universidad de ZaragozaZaragoza, Spain
M.T. Sanz-PascualElectronics Department
INAOETonantzintla, Puebla, Mexico
Abstract—Internal frequency compensation is required toachieve stable operation of fully integrated Low Dropout (LDO)regulators without relying on an external µF capacitor at theoutput node. This paper evaluates the performance of two Miller-based frequency compensation strategies: current buffer LDO(CB-LDO) and Basic Miller LDO (BM-LDO), both using a two-stage LDO core. Parameters such as overshoot, undershoot, set-tling time, power consumption and dropout voltage are measuredand compared for 1.8V regulated output LDOs, verifying theimpact of the compensation technique on the time response ofthe regulators.
Index Terms—frequency compensation, low dropout regulator,fully integrated LDO
I. INTRODUCTION
Low Dropout (LDO) regulators are widely used in powermanagement systems because of their low voltage ripple andfast transient response. The resistance of the output elementin the LDO regulator is modulated in order to provide therequired current load. This may result in stability problems,as the pole located at the output node is dynamic and dependson the current demanded by the load, which reduces the phasemargin of the loop gain [1].
To be able to integrate LDO regulators without any kindof external compensation it is necessary to implement aninternal compensation that ensures stability under all loadconditions. This may be accomplished by using pole splittechniques based on the Miller effect as reported in [1], [2],where the compensation network consists of a current bufferas a differentiator that sets the dominant pole at an internalnode. Other Miller compensation techniques for multistageamplifiers can also be used, as proposed in [3] at the costof an increasing in complexity and area consumption.
The goal of this paper is to compare two different Millercompensation techniques applied to an LDO regulator con-sisting of a 2-stage error amplifier, a pass transistor and a
feedback network. The first regulator [4]uses a current mirrorto increase the Miller effect, as proposed in [2], whereasthe second regulator [5] uses the Miller compensation of theerror amplifier to compensate the whole topology. Both LDOregulators were designed in a 0.18µm CMOS technology toprovide an output voltage of 1.8V . The paper is divided asfollows: Section II shows a brief discussion of the frequencycompensation techniques in LDOs. Section III presents the ac-tual implementation of the integrated regulators. Experimentalresults are shown in Section IV, and a comparison of bothimplementations is made. Finally, Section V summarizes theconclusions of this work.
II. FREQUENCY COMPENSATION IN LDO REGULATORS
The basic topology of an LDO regulator consists of an erroramplifier (EA), a pass element, typically a power transistor,and a feedback network made up by a resistive arrangement.The feedback network (Rf1 and Rf2 in Fig. 1) sets the outputvoltage of the regulator according to the following equation:
Vout =
[(Rf2
Rf1
)+ 1
]Vref (1)
The main issue of the basic topology, if a fully integratedsolution is desired, is stability, due to the dynamic poles undervariable current load , as already mentioned. By using theMiller effect, a dominant pole can be settled at an internalnode, typically at the output of the EA [6], [7]. The capacitanceeffect in Miller compensation can be further amplified by acurrent amplifier, as proposed in [2]. This compensation splitsthe output and the internal poles making the regulator stablewithout the use of any external devices and resulting in a fullyintegrated solution. Another solution, proposed in [5], consistsin using the own internal compensation network of the EA toset the dominant pole of the regulator at the output of the firststage of the EA.
For the sake of comparison, these different internal com-pensation techniques were applied to the same LDO regulator978-1-7281-4840-3/19/$31.00 ©2019 IEEE
2019 16th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE) Mexico City, Mexico. September 11-13, 2019
−
+
Error amplifier
A1 A2Vref
Rf2
Rf1
Load
SupplyPower
PassElement
CB-Comp.BM-Comp.
Vout
VOEA
VX
Fig. 1. LDO regulator configuration
configuration, as shown in Fig. 1, where CB-comp and BM-comp represent the Current Buffer and Basic Miller compen-sation network, respectively.
The current buffer compensated LDO regulator (CB-LDO)[4] uses the compensation network shown in Fig. 2(a). Thecapacitance Cc1 is amplified by the gain of the currentamplifier,so the effective capacitance is Ceff = ACc1 andthe resulting poles and zero are located at:
p1 = 1R2C2+(Ceff+C3)Req+gmpR2R3Ceff
(2)
p2 = − gmpCeff
(Ceff + C3)C2(3)
z = − 1
rACeff(4)
where R2 and C2 are the output resistance and capacitance ofthe error amplifier, C3 and R3 are the equivalent capacitanceand resistance at the output node respectively, gmp is thetransconductance of the pass transistor and rA is the equivalentoutput resistance of the compensation block.
According to equations (2), (3) and (4), a pole-zero can-cellation can be achieved by choosing an appropriate valuefor the gain of the current amplifier, but there is a trade-off between power consumption and the gain of the currentamplifier. For the current amplifier an improved Wilson currentmirror with 30dB gain and a Miller capacitor CC1 = 1.5pFfor the compensation block were used.
The compensation network of the basic Miller compensatedLDO regulator (BM-LDO) of [5] is shown in Fig. 2(b) wherethe Miller compensation of the EA is used to compensate thewhole regulator. The regulator has the following pole and zerolocations:
p1 =1
gm6R1R2Cc2 + CgdR2R3gmp + C3R3(5)
p2 =gm6R1R2Cc2+CgdR2R3gmp+C3R3
Cc2R1R2(C3R3gm6+CgdR3gm6+CgdR3gmp+C1+C2)(6)
p3 =C3R3gm6 + CgdR3gm6 + CgdR3gmp + C1 + C2
R3 (C1CgdR2gmp + C1C3 + C2C3 + C3Cgd)(7)
Powersupply
Powersupply
Ibias
CC1
Vout
VOEA
1:1
40:1
MA1MA2
MA3MA4
MA5MA6
(a)
CC2RZ
VOEAVX
(b)
Fig. 2. Compensation networks: a) CB-LDO and b) BM-LDO
TABLE IMAIN PARAMETERS OF THE EAS
Parameter CB-LDO BM-LDOVoltage supply range [V ] 2.1− 3.3 1.9− 3.3
Open loop gain [dB] 60 95Gain bandwidth product (GBW) 2.5MHz 436kHz
Phase margin [deg] 90 84Quiescent current (Iq) [µA] 16.4 55
z =1
Cc
(1
gm6−Rz
) (8)
where gm6 is the transconductance of the second stage ofthe EA, and R1 and C1 are the equivalent output resistanceand capacitance of the first stage of the EA, respectively. C2
includes the gate capacitance of the pass transistor, which is inthe order of 30pF . Finally, Cgd is the gate-drain capacitanceof the pass transistor.
Due to the high gate capacitance of the pass transistor,the compensation network in the CB-LDO contributes bothto compensate the regulator and to improve the time response,as it drains current from the gate node. In contrast, the BM-LDO ensures stability of the regulator, but requires additionalcircuitry in order to improve the time response.
III. INTEGRATED LDO REGULATORS
The LDO configuration in Fig. 1 consists of a two-stageMiller which was designed to operate for the whole inputoperating voltage with high gain in order to improve theprecision of the regulator. The main characteristics of theEA used in each regulator are summarized in Table I for theminimum input voltage.
To get a stable solution for the BM-LDO, and accordingto equations (5) to (8), a high gain second stage is needed
2019 16th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE) Mexico City, Mexico. September 11-13, 2019
Powersupply
Powersupply
Vout
VOEA
Vref1
Vref2
MaMb
Mc
MdMe
Mf
Fig. 3. Time response enhancement circuit for BM-LDO regulator
to split the poles and a pole-zero cancellation can be imple-mented by using Rz , thus improving the frequency responseof the regulator. The capacitor and resistor values used in thecompensation network were CC = 4pF and Rz = 13kΩ.This compensation ensures stability of the BM-LDO regulator,but the time response was not appropriate, so a circuit wasimplemented to reduce undershoot/overshoot. The circuit isshown in Fig. 3. It provides more current to charge anddischarge the gate capacitance of the pass transistor accordingto the output voltage behavior, keeping the circuit in off statewhen the output voltage is at the desired value.
As for the CB-LDO regulator, the current amplifier con-figuration, as previously mentioned, is an improved Wilsoncurrent. Because the required effective compensation capaci-tance to properly compensate the CB-LDO regulator is 60pF ,a compensation capacitance of 1.5pF can be used in combina-tion with the current amplifier consuming a quiescent currentof 21µA. It splits the poles at the output node and at theoutput of the EA, making the last one the dominant pole ofthe system to reach stability.
The integration of both LDO regulators in a CMOS 0.18µmtechnology was carried out after the design and simulationwere finished. The layout is shown in Fig. 4 for both regu-lators. The silicon areas without pads for the CB-LDO andBM-LDO were 0.17mm2 and 0.105mm2, respectively.
IV. COMPARISON OF EXPERIMENTAL RESULTS
Both regulators were designed and fabricated in the same0.18µm CMOS technology to provide an output voltage of1.8V with a maximum current load of 50mA.
The transfer characteristic of both regulators is shown inFig. 5. The dropout voltage is 525mV for the CB-LDO and100mV for the BM-LDO, i.e., the minimum input voltagewas 2.35V and 1.9V , respectively. As for the time response,the CB-LDO and BM-LDO regulators were tested with aload capacitance of 100pF , with a current load step between
(a)
BM-LDO
(b)
Fig. 4. LDO regulators layout: a) CB-LDO and b) BM-LDO
Voltage
0
0.5
1
1.5
2
2.5
3
3.5
Voltage0 0.5 1 1.5 2 2.5 3 3.5
BM-LDOCB-LDOSupply Voltage
Fig. 5. Transfer characteristic of the LDO regulators
2019 16th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE) Mexico City, Mexico. September 11-13, 2019
00 24.2 48.4 72.7 96.9 121.2 145.4 169.6 193.9 218.10
0.51
1.52
2.53
3.54
Vo u
t [V]
T ime μs[ ]
(a)
V out
[V]
012345
Time [μs]-20 0 20 40 60 80 100
(b)
Fig. 6. Time response @ Vin = 3.3V and CL = 100pF : a) CB-LDOregulator and b) BM-LDO regulator
TABLE IICOMPARISON OF RESULTS
Parameter CB-LDO BM-LDOOutput voltage [V ] 1.8 1.8Input Voltage [V ] 2.2− 3.3 1.9− 3.3
Maximum current load [mA] 50 50Dropout voltage [mV ] 525 100
Line Regulation [mV/V ] 90.31 18.18Load Regulation [mV/mA] 1.36 0.04
Compensation capacitance [pF ] ≤ 5 6Settling time [µs] 21.85 5.2
Quiescent current [µA] 100 260Load capacitance [pF ] 100 100
Area without pads [mm2] 0.17 0.105FOM [ns] 2.18 1.62
the minimum and maximum values (full transient load). Theresults are shown in Fig. 6. Both regulators show a highovershoot value, increasing the settling time.
In the CB-LDO regulator the current amplifier in the com-pensation network sinks the current from the output node ofthe error amplifier, thus improving the response under currentload transitions from minimum to maximum by turning on thepass transistor. In contrast, for a transition from maximum tominimum, where the pass transistor needs to be turned off,there is no additional current to charge the gate capacitance,thus requiring a higher time interval to reach the desired outputvoltage.
For the BM-LDO regulator the output voltage is maintainedat the desired value by using voltage comparators that sink andprovide current to the gate of the pass transistors to turn it onand off, as shown in Fig. 3, at a cost of an increase in thepower consumption.
A summary of the main experimental parameters is shownin Table II. FOM = tsettling × IQ
Iload× CC
CLis used as a figure
of merit.The CB-LDO regulator shows lower power and silicon area
consumption, and higher capability to provide current to theload. However, its ability to handle load capacitance is reducedbecause of the compensation technique. The BM-LDO regu-lator shows better time response and can be used for highercapacitive loads, at the cost of higher power consumption. Thisis due to the fact that a time response enhancement circuit, aswell as an over-current protection circuit were added to thetopology, consuming about a fifth part of the overall power.Furthermore, the BM-LDO regulator shows lower dropoutand better line and load regulation. This higher accuracy isachieved thanks to the higher gain of the EA.
V. CONCLUSIONS
Two different internal compensation strategies for LDOregulators were compared in this paper, in terms of transientresponse, power consumption and dropout voltage. Althoughinternal compensation causes higher output voltage ripple, itcan be reduced by increasing the current available to chargeand discharge the gate capacitance of the pass transistor, thusimproving the settling time of the regulator.
For the compensation technique in CB-LDO, it should bothsource and sink current to charge and discharge the gate capac-itance of the pass transistor in order to avoid long transients.On the other hand, if a simple compensation network is used,such as in BM-LDO, poor time response is expected if noadditional circuitry is used to improve it. This sets a trade-offbetween transient response and power consumption because,according to the results, a reduction in power consumptionpenalizes the capacity to handle the gate capacitance of thepower transistor.
ACKNOWLEDGMENT
This work was supported by CONACYT 486300 DoctorateGrant and Research Projects CONACYT CB-2015-257985,TEC2015-65750-R (MINECO/FEDER, UE)
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