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TABLE OF CONTENTSGeneral Chair’s Message 2Executive Committee 3-6Senior Committee 6-8Advisory Committee 9SOI Technical Committee 9SubVt Technical Committee 103D Technical Committee 10Conference-at-a-Glance 11Technical Program Schedule 12-24Short Courses 25-26Fundamentals Classes 27-29Additional Agenda Information 30Hotel Policies and Reservations 31Area and Activities 32Airport and Transportation 33Conference Registration 34Registration Form 35Plenary Speakers 36-37Speakers & Instructors 38-49
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OCTOBER 5-8, 2015 • DOUBLETREE BY HILTON • ROHNERT PARK, CALIFORNIA
2015 IEEE S3S CONFERENCE IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE
41st ANNUAL CONFERENCE and 21st ANNUAL SHORT COURSE PROGRAM
SPONSORED BY Institute of Electrical and Electronics Engineers, Inc.
Electron Devices Society
Now in its third year, the 2015 IEEE S3S Con-ference has evolved into the premier venue for sharing the latest and most important
findings in the areas of process integration, ad-vanced materials and materials processing, and de-vice and circuit design for SOI, 3D and low-voltage microelectronics.
World-class leading experts in their fields will come to this year’s S3S Conference to present, dis-cuss and debate the most recent breakthroughs in their research.
IEEE S3S Conference, formerly known as the IEEE SOI Conference, is an amalgam of the original conference and the Subthreshold Microelectronics Conference and the Monolithic Three-Dimensional Integration Conference.
We offer Short Courses on SOI applications to RF, High Performance, Low Power CMOS and the Internet of Things. In order to bring everyone up to speed in the rapidly changing field of Three Dimen-sional Integration we will also feature a short course on this exciting and emerging topic.
This year we will have two Plenary Sessions on two separate days which will feature speakers representing some of the most influential forces in their industries. Chief Technology Officers and Senior VP’s from major corporations and research organizations will present their visions of the future of their fields at the Plenary Session.
Authors and invited researchers of the highest caliber from all over the world will present their re-search in two parallel sessions, one on SOI and the other one on Subthreshold Microelectronics.
We have Hot Topic Sessions on Ultra-Low Power and 3D with showcase presentations on the most up-to-date progress in these fields.
Wednesday afternoon will be the time to brush up on new topics at the Fundamentals Course. This year we offer one Fundamentals course on Ul-tra-Low Power Logic and Memory Devices and an-other Fundamentals course entitled Logic Devices for 28nm Node and Beyond where experts will pres-ent their view on FinFETs, FDSOI and Radiation Ef-fects.
The interactive Poster Session is a great place to meet new colleagues and learn and exchange in-sights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and in-fluential experts in your field.
As the late afternoon turns to evening join our popular Rump Session. The Rump Session has historically provided a venue where audience and panelists engage in heated technical discussions. The goal is to explore new ideas and opinions about key topics that have a major impact on the forward progress of our fields of interest. As always the Rump Session will feature well-known people from academia and industry. This year we will dis-cuss and debate, while attempting to answer the question… What Does IoT mean for Si Technology?
Take time to visit the local attractions of Sonoma County. Sonoma is well known for out-door recreation, spas, golf, night life, shopping, culi-nary activities, arts and music and wineries.
It is truly my pleasure to serve as the General Chair of the 2015 Conference.
—Bruce Doris
GENERAL CHAIR’S MESSAGE
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General ChairBruce Doris, IBM [email protected]
Bruce Doris started in the field of semiconductor device research at Sematech and the Advanced Prod-ucts Research and Development Lab-oratory at Motorola while studying applied physics and electrical engi-neering at the University of Texas at Austin. He moved to IBM Microelec-tronics after obtaining his PhD where he held various positions in Device Integration, Design and Characteri-zation. Soon after joining IBM Bruce decided to focus his attention on ad-vanced devices and joined the Explor-atory Device Group in IBM research where he made progress in the area of Local Mechanical Stress for Channel Mobility Enhancement and advanced device architectures including FDSOI, FinFETs. In 2007 he established the Device Integration Group at the Al-bany Nano Technology Center and went on to create the Pathfinding Al-liance to deliver performance boost-ers and advanced device options for IBM and partners. He has authored or co-authored over 100 papers and holds well over 300 US patents. Today Bruce’s research interests include ra-diation effects in advanced devices, alternate channel materials for FDSOI and Fin-FETs and devices architec-tures for beyond the 7nm node
Technical ChairOlivier Faynot, [email protected]
Olivier Faynot received the MSc and PhD degrees from the Institut National Polytechnique de Grenoble, France in 1991 and 1995, respectively. His doc-toral research was related to the char-acterization and modeling of deep submicron Fully Depleted SOI devices fabricated on ultrathin SIMOX wafers.
He joined LETI (CEA-Grenoble, France) in 1995, working on simu-lation and modeling of deep submi-cron fully and partially depleted SOI devices. His main activity was the development of a dedicated Partially Depleted SOI SPICE model, called LETISOI. From 2000 to 2002, he was involved in the development of a sub 0.1µm partially depleted technology. From 2003 to 2007, he was leading the development of advanced single and multiple-gate Fully Depleted SOI technologies with High K and Metal gate. From 2008 to 2010, he managed the innovative devices laboratory at LETI, focussed on advanced CMOS device integration. Since 2011, he is responsible for the Microelectronic component division at LETI, dealing with CMOS technologies, advanced Memories and 3D integration for com-puting.
SOI Division Technical ChairFred Allibert, [email protected]
Dr. Allibert received his MS degree from the National Institute for Applied Sciences (INSA, Lyon, France) in 1997 and his PhD from Grenoble Polytech-nic’s Institute (INPG) in 2003, focus-ing on the electrical characterization of Unibond wafers and the study of advanced device architectures such as planar double-gate and 4-gate tran-sistors. He was a visiting scientist at KAIST (Taejon, Korea) in 1998 and joined Soitec in 1999. As an R&D sci-entist, he implemented SOI specific electrical measurement techniques (for thin films, multi-layers, high-resis-tivity) and supported the development of products and technologies targeting various applications, including FD-SOI, RF, imagers, and high-mobility materials. As Soitec’s assignee at the Albany Nanotech Center, from 2011 to 2015, his focus was on substrate technologies for advanced nodes, ex-ploring the benefits of different sub-strate materials and configurations for various device architectures.
In July 2015, he joined Soitec’s cor-porate R&D. His current focus is on RF-SOI substrates and Material-De-vice interactions. He has authored or co-authored over 50 papers and holds about 15 patents.
EXECUTIVE COMMITTEE
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SubVt Division Technical ChairMostafa Emam, [email protected]
Mostafa Emam is the founder and CEO of Incize, a start-up providing innovative characterization and mod-eling services of state-of-the-art semi-conductor devices and materials for the design of digital, analog/RF and harsh environment applications. He received the MSc degree from the In-stitute National Polytechnique, Tou-louse, France, in 2005 and the PhD degree in engineering sciences from the Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, in 2010. His doctoral thesis was entitled “Wide band and noise characteriza-tion of various MOSFETs for optimized use in RF circuits.” He is active in the fields of characterization and model-ing of SOI devices in dc, RF, large-sig-nal, and high-frequency noise, for harsh-environment applications and under mechanical stress conditions, as well as the design and simulation of RF SOI circuits.
Dr. Emam is author and co-author of 40 scientific articles and a reviewer for several IEEE journals. He is co-au-thor of a chapter entitled: “SOI CMOS for radio frequency and analogue pplications” in the “Handbook of Sil-icon-on-Insulator (SOI) Technology” (Woodhead Publishing, April 2014) and the author of the “RF Character-ization of Semiconductor Devices” (Springer, 2016).
3D Division Technical Chair,Monolithic 3D Integration Short Course Co-ChairZvi Or-Bach, MonolithIC [email protected]
Zvi Or-Bach is the founder of Mono-lithIC 3D™Inc., Top Embedded Inno-vator-Silicon by Embedded Computing Design Magazine and finalist of the “Best of Semicon West 2011” for its monolithic 3D-IC breakthrough. Or-Bach was also a finalist of the EE Times Innovator of the Year Award in 2011 and 2012 for his pioneering work on the monolithic 3D-IC. Or-Bach has ex-tensive management experience includ-ing being CEO for over 20 years, being in charge of R&D, sales, marketing, business development and other cor-porate functions. Or-Bach has been an active board member for over 20 years and is now Chairman of the Board for Zeno Semiconductors and VisuMenu. Or-Bach has a history of innovative de-velopment in fast-turn ASICs for over 20 years. His vision led to the invention of the first Structured ASIC architecture, the first single via programmable array, and the first laser-based system for one-day Gate Array customization. In 2005, Or-Bach won the EETimes Innovator of the Year Award and was selected by EE Times to be part of the “Disruptors–The people, products and technologies that are changing the way we live, work and play.” Prior to MonolithIC 3D, Or-Bach founded eASIC in 1999 and served as the company’s CEO for six years. eASIC was funded by leading investors Vinod Khosla and KPCB in three successive rounds. Under Or-Bach’s leadership, eASIC won the prestigious EETimes’
2005 ACE Award for Ultimate Product of the year in the Logic and Program-mable Logic category. Earlier, Or-Bach founded Chip Express in 1989 (recently acquired by Gigoptix) and served as the company’s president and CEO for almost 10 years, bringing the com-pany to $40M revenue, and to industry recognition for four consecutive years as a high-tech Fast 50 Company that served over 1000 ASIC designs, includ-ing many one-day prototypes and one-week production delivery. Zvi Or-Bach received his BSc degree (1975) cum laude in electrical engineering from the Technion – Israel Institute of Technol-ogy, and MSc (1979) with distinction in computer science, from the Weizmann Institute, Israel. He holds over 150 is-sued patents, primarily in the field of 3D integrated circuits and semi-custom chip architectures.
Secretary and TreasurerSteven Vitale, MIT Lincoln [email protected]
Steven Vitale is Senior Technical Staff in the Chemical, Microsystem, and Na-noscale Technologies Group at MIT Lincoln Laboratory. He received his BS in chemical engineering from Johns Hopkins University and his PhD in chemical engineering from MIT. He has been researching semiconductor device fabrication and process integration for 14 years.
At MIT Lincoln Laboratory, Steven’s current research includes development of a fully-depleted silicon-on insulator (FDSOI) ultra-low-power microelec-tronics technology for energy starved systems such as space-based systems,
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wearable computing, and biomedical devices. He is also studying novel elec-tronic devices based on diamond and 2D transition metal dichalcogenides. Prior to joining Lincoln Laboratory, Steven worked at Texas Instruments developing advanced gate etch pro-cesses for the 90nm through 45nm nodes, including research into transis-tor performance improvements through reduced source/drain silicon loss and reduced gate line edge roughness. He has published 25 refereed journal arti-cles and holds seven patents related to semiconductor processing.
In 2011 and 2012 Steven was the general chair of the IEEE Subthreshold Microelectronics Conference. He is cur-rently Secretary of the Plasma Science and Technology Division of the AVS.
Local Arrangements Chair Bich-Yen Nguyen, [email protected]
Bich-Yen Nguyen joined Soitec as a Senior Fellow supporting the tech-nology development of new micro-electronic devices and applications. Bich-Yen is also responsible for the strategic microelectronic technology. Prior to joining Soitec, Bich-Yen was a senior manager at Freescale Semicon-ductor and a Freescale/Motorola Dan Noble Fellow.
Bich-Yen has been recognized for her leadership and research in de-veloping Freescale/Motorola’s CMOS technology for advanced integrated circuit products. She also was instru-mental in transferring process tech-nology to production since 1980. Her honors and awards include recipient
of Dan Noble Fellow in 2001, the highest technical award in Motorola, Master of Innovation Award in 2003. In 2004, she received the 1st National Award “Women in Technology Life-time Achievement Award.” She holds over 130 worldwide patents and has authored more than 150 technical papers on IC process, integration and device technologies.
Publicity and Development Co-ChairMeishoku MasaharaNational Institute of [email protected]
Meishoku Masahara received the BS, MS, and PhD degrees in electrical engineering from the School of Sci-ence and Engineering, Waseda Uni-versity, Tokyo, Japan, in 1990, 1992, and 1995, respectively. From 1994 to 1996, he was a research associate with Waseda University. From 1996 to 1998, he was a researcher with CREST, Japan Science and Technol-ogy Corporation, and was with the Research Center for Nanodevices and Systems, Hiroshima University, Hiro-shima, Japan. From 1998 to 2000, he was a visiting lecturer in the Kagami Memorial Laboratory for Materials Sci-ence and Technology, Waseda Uni-versity. He joined the Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan, in 2001. Since then, he has been engaged in the research and devel-opment of ultrathin vertical channel multi-gate MOSFETs including vertical DG MOSFET and FinFET. He is now
a director of research planning office, Department of Electronics and Man-ufacturing. From July 2005 to June 2006, he was a visiting researcher at IMEC. From April 2009, he has been a visiting professor of Meiji University.
He has published over 100 re-search papers in archival journals and refereed international conferences on these subjects. Dr. Masahara serves on the Technical Program Committee of the Symposium on VLSI Technol-ogy, SSDM, IEDM, ESSDERC, MNC, SOI Conference. He is a member of the IEEE Electron Devices Society, the Institute of Electrical Engineering of Japan, and the Japan Society of Ap-plied Physics.
Publicity and Development Co-ChairMike Fritze, [email protected]
Dr. Fritze joined the Potomac Institute for Policy Studies in April of 2015 as a Senior Fellow. He leads PIPS efforts in the area of US Government Microelec-tronics policy with a current focus on Trusted electronics issues. He also con-tributes his experience to helping Road-map US Government Microelectronics R&D efforts for the future. He currently performs strategic planning for DMEA and develops projects related to USG microelectronics issues.
Dr. Fritze was the Director of the Disruptive Electronics Division at the USC Information Sciences Institute (2010-2015). He also held a Research Professor appointment in the USC Ming Hsieh Department of Electrical Engi-neering (Electrophysics). His research
Secretary/Treasurer, continued
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interests at ISI included Trusted Elec-tronics, CMOS Reliability & Robustness, Low power 3DIC enabled electronics and Rad-hard electronics. He was a Pro-gram Manager at the DARPA Microsys-tems Technology Office (MTO) from 2006-2010. While at DARPA, Dr. Fri-tze was responsible for Programs in the areas of 3D Integrated Circuits (3DIC), Steep-Subthreshold-slope Transistors (STEEP), Radiation Hardening by De-sign (RHBD), Carbon Electronics for RF Applications (CERA), Silicon-based RF (TEAM), Ultra-low power Digital (ESE), Highly regular designs (GRATE) and Leading edge foundry access (LEAP).
Prior to joining DARPA, Dr. Fritze was a staff member from 1995-2006 at
MIT Lincoln Laboratory in Lexington, Massachusetts, where he worked on ful-ly-depleted silicon on insulator (FDSOI) technology development with an em-phasis on novel devices. Particular interests included highly scaled, tunnel-ing-based, and ultra-low power devices. Dr. Fritze also worked in the area of sil-icon-based integrated optics. Another research interest at Lincoln Laboratory was in the area of resolution-enhanced optical lithography and nanofabrication with particular emphasis on low volume technological solutions.
Dr. Fritze received a PhD in Phys-ics from Brown University in 1994, working in the area of compound semiconductor quantum well physics.
He received a BS in Physics in 1984 from Lehigh University. Dr. Fritze is an elected member of Tau Beta Pi and Sigma Xi. He is a recipient of the Office of the Secretary of Defense Medal for Exceptional Public Service awarded in 2010. He is a Senior Member of the IEEE and is active on the program commit-tees of the EIPBN (3Beams, for which he served as Program Chair in 2012), GOMAC and IEEE S3S conferences. Dr. Fritze has published over 75 papers and articles in professional journals and holds several US Patents.
Conference ManagerJoyce Lloyd, [email protected]
Monolithic 3D Integration Short Course Co-ChairPaul Franzon, North Carolina [email protected]
Paul D. Franzon is currently a distin-guished professor of electrical and computer engineering at North Car-olina State University. He earned his PhD from the University of Ade-laide, Adelaide, Australia. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and three companies he co-founded, Communica, LightSpin Technologies and Polymer Braille, Inc.
His current interests center on the technology and design of complex mi-crosystems incorporating VLSI, MEMS, advanced packaging and nano-elec-tronics. He has led several major ef-
forts and published over 300 papers in these areas.
In 1993 he received an NSF Young Investigators Award, in 2001 was se-lected to join the NCSU Academy of Outstanding Teachers, in 2003, se-lected as a distinguished alumni pro-fessor, received the Alcoa Research Award in 2005, and the Board of Governors Teaching Award in 2014. He served with the Australian Army Reserve for 13 years as an infantry soldier and officer. He is a Fellow of the IEEE.
SOI Devices Fundamentals Class ChairJoao Antonio MartinoUniversity of Sao [email protected]
Joao Antonio Martino received the MS and PhD degrees in microelectronics from the University of Sao Paulo in 1984 and 1988 respectively and a post-doc in SOI devices at Imec/Belgium in 1994. He has been with the University of Sao Paulo since 1992 where he be-came a professor in 2005 and head of SOI CMOS research group since 1990. He is senior member and distinguished lecturer of Electron Devices Society EDS/IEEE since 2008. The current re-search topics are UTBB SOI and FinFET electrical characterization/modeling and Tunnel-FET devices.
SENIOR COMMITTEE
Publicity and Development Co-Chair, cont’d
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SubVtFundamentals Class ChairAlex Fish, Bar Ilan [email protected]
Alexander Fish received the BSc de-gree in Electrical Engineering from the Technion, Israel Institute of Technol-ogy, Haifa, Israel, in 1999. He com-pleted his MSc in 2002 and his PhD (summa cum laude) in 2006, respec-tively, at Ben-Gurion University in Is-rael. He was a postdoctoral fellow in the ATIPS laboratory at the University of Calgary (Canada) from 2006-2008. In 2008 he joined the Ben-Gurion University in Israel, as a faculty mem-ber in the Electrical and Computer Engineering Department. There he founded the Low Power Circuits and Systems (LPC&S) laboratory, special-izing in low power circuits and sys-tems. In July 2011 he was appointed as a head of the VLSI Systems Center at BGU. In October 2012 Prof. Fish joined the Bar-Ilan University, Fac-ulty of Engineering as an Associate Professor and the head of the nano-electronics track. Prof. Fish also leads new Emerging Nanoscaled Integrated Circuits and Systems (ENICS) Labs.
Prof. Fish’s research interests in-clude development of secured hard-ware, ultra-low power embedded memory arrays, CMOS image sensors and high speed and energy efficient design techniques. He has authored over 100 scientific papers in journals and conferences, including IEEE Jour-nal of Solid State Circuits, IEEE Trans-actions on Electron Devices, IEEE Transactions on Circuits and Systems and many others. He also submitted 23 patent applications. Prof. Fish has
published two book chapters. He was a co-author of papers that won the Best Paper Finalist awards at IEEE ISCAS and ICECS conferences.
Prof. Fish serves as an Editor in Chief for the MDPI Journal of Low Power Electronics and Applications (JLPEA) and as an Associate Editor for the IEEE Sensors, IEEE Access, Elseiver Microelectronics and Integration, the VLSI Journals. He also served as a chair of different tracks of various IEEE conferences. He was a co-organizer of many special sessions at IEEE confer-ences, including IEEE ISCAS, IEEE Sen-sors and IEEEI conferences. Prof. Fish is a member of Sensory, VLSI Systems and Applications and Bio-medical Systems Technical Committees of IEEE Circuits and Systems Society.
3D Multimedia ChairJin-Woo Han, [email protected]
SOI Multimedia ChairLaurent Grenouillet, [email protected]
Laurent Grenouillet received the En-gineer degree in physics in 1998 from the Institut National des Sciences Ap-pliquées (INSA) in Lyon, France, and the PhD degree in Electronic devices in 2001 for his work on the optical spectroscopy of diluted nitrides grown on GaAs substrates.
After a post-doctoral position in the field of Molecular Beam Epi-taxy, he joined CEA-Leti in 2002 and worked on GaAs-based VCSELs emit-ting in the 1.1-1.3µm range and single photon sources with quantum dots.
In 2006, he joined the Silicon Photonics group where he developed CMOS compatible hybrid III-V on sil-icon lasers.
In 2009, he joined IBM Alliance in Albany as a Leti assignee to contribute to the development of FDSOI technol-ogy. Within Albany state-of-the-art facilities, he extensively worked on device integration to improve perfor-mance of FDSOI devices (28nm and 14nm node).
Back in France at CEA-Leti in 2013, he focused on the performance boosters for the 10nm node FDSOI technology, and joined the Memory Laboratory to explore OxRAM memo-ries and how those non-volatile mem-ories can be integrated with FDSOI transistors.
Laurent Grenouillet authored or co-authored over 80 papers (confer-ences and journals) and has filed over 35 patents.
SubVt Multimedia ChairMichelly De SouzaCentro Universitário da [email protected]
Michelly de Souza (S’05–M’08-SM’15) received the Electrical Engineering de-gree from Centro Universitário da FEI in 2002, and the MSc and PhD de-grees in 2005 and 2008, respectively, in Microelectronics from University of São Paulo, Brazil. From September 2007 to February 2008 she was with Laboratoire de Microélectronique from Université Catholique de Lou-vain (UCL), Belgium, working in the fabrication and electrical character-ization of analog circuits with novel
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Silicon-On-Insulator (SOI) transistors. She is currently an Associate Professor with Centro Universitário da FEI. Her current interests are the fabrication, electrical characterization, simulation and modeling of SOI MOS devices, for low-power and high analog per-formance.
Rump and Poster ChairAli KhakifiroozCypress [email protected]
Ali Khakifirooz received his BSc and MSc degrees from the University of Tehran in 1997 and 1999, respec-tively and his PhD from MIT in 2007, all in electrical engineering. In 2008 he joined IBM Research at Albany Nanotech. As the lead device engineer of the ETSOI project, he defined the main elements of the 14/22nm FDSOI technology, including performance demonstration, strain engineering, and multi-Vt strategy. Subsequently, he was a key member of the IBM pathfinding team and made signifi-cant contributions to the early defini-
tion of 7nm node technology. In 2014 he joined Spansion, now Cypress Semiconductor, where he is a Senior Member of Technical Staff working on flash memory, including 3D NAND and 40/28nm embedded flash. He is an author of four book chapters, has authored or co-authored more than 75 technical papers, and holds more than 260 issued US patents. He was named an IBM Master Inventor and an IEEE Senior Member in 2011.
Ultra-Low Power Hot Topics ChairNobuyuki SugiiHitachi, [email protected]
Nobuyuki Sugii (IEEE M’08, SM’15) received the BS, MS, and PhD degrees in applied chemistry from the Uni-versity of Tokyo in 1986, 1988, and 1995, respectively. He joined the Cen-tral Research Laboratory, Hitachi, Ltd. in 1988 where he had engaged in re-search and development of oxide su-perconducting materials and devices until 1996. He had been a research
scientist in the Superconductivity Re-search Laboratory, International Su-perconductivity Technology Center, from 1991 to 1994. Since 1996, he has been working for Hitachi, on the research and development of SiGe materials, CMOS devices including SOI and strained-silicon, and cur-rently, on sensing electronic systems. He had been a research group leader of ultra-low voltage device project that focuses on R&D of SOTB (FDSOI with thin buried oxide) in the Low-power Electronics Device Association & Proj-ect (LEAP), from 2011 to 2015. Cur-rently, he is a member of the program committees of VLSI Technology, IEEE S3S Conference and SSDM (Solid State Devices and Materials Conference). From 2004 to 2015, he served as a vis-iting professor for the Tokyo Institute of Technology.
Dr. Sugii is a fellow of the Japan Society of Applied Physics and a se-nior member of the IEEE Electron De-vices Society.
SubVT Multimedia Chair, cont’d
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Fred Allibert, [email protected]
Mike Alles, Vanderbilt [email protected]
Ibrahim Ban, [email protected]
Gary Bronner, [email protected]
Chang-Lee ChenMIT Lincoln [email protected]
Kangguo Cheng, [email protected]
Yuh-Yue ChenRichWare Technology [email protected]
Bruce Doris, IBM [email protected]
Olivier Faynot, [email protected]
Philippe Flatresse, [email protected]
Samuel Fung, [email protected]
Laurent Grenouillet, [email protected]
Michel Haond, [email protected]
Toshiro Hiramoto, University of [email protected]
Ru Huang, Peking [email protected]
Keiji Ikeda, GNC-AIST/[email protected]
Ali KhakifiroozCypress [email protected]
Jong-Ho LeeSeoul National [email protected]
Joao Antonio MartinoUniversity of Sao [email protected]
Meishoku MasaharaNational Institute of [email protected]
Carlos Mazure, [email protected]
Bich-Yen Nguyen, [email protected]
Les Palkuti, DTRA/[email protected]
Mario Pelella, ON [email protected]
Shom Ponoth, [email protected]
Changhwan Shin, University of [email protected]
Stanley (S.C.) Song, [email protected]
Nobuyuki Sugii, Hitachi, [email protected]
Steven Vitale, MIT Lincoln [email protected]
Geng Wang, [email protected]
Yang Du, [email protected]
Toshiro Hiramoto, University of [email protected]
Les Palkuti, DTRA/[email protected]
Mario Pelella, ON [email protected]
ADVISORY COMMITTEE
SOI TECHNICAL COMMITTEE
PAGE 9
Jon Ahlbin, Missile Defense [email protected]
Amara Amara, [email protected]
David BolCatholic University of [email protected]
Dennis Buss, Texas [email protected]
Ben CalhounUniversity of [email protected]
Lew Cohn, [email protected]; [email protected]
Yang Du, [email protected]
Alex Fish, Bar Ilan [email protected]
Paul Franzon, North Carolina [email protected]
Mike Fritze, [email protected]
Pascale Gouker, MIT Lincoln [email protected]
Sumeet Gupta, Penn [email protected]
David Hansquine, [email protected]
Adrian IonescuEcole Polytechnique Federale de [email protected]
Lauri Koskinen, University of [email protected]
Les Palkuti, [email protected]
Dan Radack, [email protected]
Mingoo Seok, Columbia [email protected]
Makoto Takamiya, University of [email protected]
Steven Vitale, MIT Lincoln [email protected]
David WentzloffUniversity of [email protected]
SUBVT TECHNICAL COMMITTEE
3D TECHNICAL COMMITTEE
Mukta Farooq, [email protected]
Eugene Fitzgerald, [email protected]
Paul Franzon, North Carolina [email protected]
Jin-Woo Han, [email protected]
Subu Iyer, [email protected]
Arifur Rahman, [email protected]
Thomas Uhrmann, [email protected]
Maud Vinet, [email protected]
Philip Wong, [email protected]
Takao Yonehara, Applied [email protected]
PAGE 10
CONFERENCE AT-A-GLANCE
MONDAY, OCTOBER 5
7:00am Continental Breakfast
8:00am Short Course 1: SOI Applications Short Course 2: Monolithic 3D Integration
12:00pm Short Course Lunch
1:00pm SC1: Applications (cont’d) SC2: Monolithic 3D Integrations (cont’d)
6:00pm Welcome ReceptionAll short course and conference attendees welcome
TUESDAY, OCTOBER 6
7:00am Continental Breakfast
8:00am Conference Opening
8:20am Session 1 Plenary Talks
10:20am Break
10:40am Session 2a Materials Session 2b IoT
12:00pm Lunch (on own)
1:00pm Session 3 Joint Hot Topic Session Ultra-Low Power 2:40pm Break
3:00pm Session 4 3D - Invited Monolithic 3D Alternative Technologies
5:30pm Session 5 Joint Poster Session
WEDNESDAY, OCTOBER 7
7:00am Continental Breakfast
8:00am Session 6a Advanced Device Architecture Session 6b Digital Session 6c Invited Talks on M3DI
10:00am Break
10:20am Session 7a High Frequency Session 7b Energy Harvesting Session 7c Selected Talks on M3DI
12:00pm Lunch and Free Time (on own)
1:00pm F1: Logic Devices for 28nm and Beyond F2: Low-Voltage Logic and Memory Circuits and Power Management
6:00pm Cookout
8:00pm Evening Panel Discussion What Does IoT Mean for Si Technology?
THURSDAY, OCTOBER 8
7:00am Continental Breakfast
8:00am Session 8 Plenary Talks
10:00am Break
10:20am Session 9a Advanced Processes & Characterization Session 9b Memory
12:00pm Lunch (on own)
1:00pm Session 10a Power Management Session 10b Analog
2:40pm Break
3:00pm Session 11 Joint Late News
5:00pm Conference Closing
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TECHNICAL PROGRAM SCHEDULE
TUESDAY, OCTOBER 6
7:00am Continental Breakfast
7:45am Conference Opening
SESSION 1 Plenary Session Chairs: Fred Allibert, Soitec • Mostafa Emam, Incize • Zvi Or-Bach, MonolithIC 3D
8:20am 1.1 New Game Changing Product Applications Enabled by SOI Gary Patton; Global Foundries (Invited Speaker)
9:00am 1.2 The Past and Future of Extreme Low Power (xLP) SoC Transistor, embedded memory and backend technology Geoffrey Yeap; Qualcomm Technologies (Invited Speaker)
9:40am 1.3 Sustaining the Silicon Revolution: From 3-D Transistors to 3-D Integration Tsu-Jae King Liu (Invited Speaker) T.-J. King Liu, P. Zheng, D. Connelly, K. Kato; Department of Electrical Engineering and Computer Sciences, University of California at Berkeley
10:20am Break
SESSION 2a Materials Chair: Sorin Cristoloveanu, IMEP-INP Grenoble MINATEC
10:40am 2a.1 Engineered Substrates for Moore and More than Moore’s Law Christophe Maleville; Soitec (Invited Speaker)
11:20am 2a.2 300 mm InGaAsOI substrate fabrication using the Smart Cut™ technology S. Sollier1,2, J. Widiez1,2, G. Gaudin4, F. Mazen1,2, T. Baron1,3, M. Martin1,3, MC. Roure1,2, P. Besson1,2, C. Morales1,2, E. Beche1,2, F. Fournel1,2, S. Favier1,2, S. Favier1,2, A. Salaun1,2, P. Gergaud1,2, M. Cordeau1,2, C. Veytizou4, L. Ecarnot4, D. Delprat4, I. Radu4 and T. Signamarcheix1,2;
1Univerisity Grenoble Alpes, Grenoble France, 2CEA-Leti, Minatec Campus, Grenoble, France, 3University Grenoble Alpes, CNRS, LTM, Grenoble France, 4SOITEC Parc Technologique des Fontaines, Bernin, France
Session 2a continued
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11:40am 2a.3 Systematic evaluation of SOI Buried Oxide Reliability for Partially Depleted and Fully Depleted Applications
W. Schwarzenbach, C. Malaquin, F. Allibert, G. Besnard, B.-Y. Nguyen; SOITEC, Parc Technologies de Fontaines, Bernin, France
SESSION 2b IoT Chair: Chang-Lee Chen, MIT Lincoln Laboratory
10:40am 2b.1 Low Voltage Devices and Circuits for Energy-Starved Systems Steven Vitale, MIT Lincoln Laboratory (Invited Speaker)
11:20am 2b.2 A 23 nW CMOS Ultra-Low Power Temperature Sensor Operational from 0.2 V D. A. Kamakshi1, A. Shrivastava2, and B. H. Calhoun1;
1Department of Electrical Engineering, University of Virginia, Charlottesville, Virginia, USA, 2Psikick Inc., Charlottesville, Virginia, USA
11:40am 2b.3 Robust Subthreshold Level Conversion J. Lin, L.A. Soares and S. Vitale; MIT Lincoln Laboratory, Lexington, MA, USA
12:00pm Lunch (on own)
SESSION 3 Joint Hot Topics: Ultra Low Power Chair: Nobuyuki Sugii, Hitachi, Ltd.
1:00pm 3.1 Can We Connect Trillions of IoT sensors in a Sustainable Way? – A Technology/Circuit Perspective David Bol (Invited Speaker) D. Bol, G. de Streel, D. Flandre; ICTEAM Institute, Université catholique de Louvain, Louvain-la-Neuve, Belgium
1:40pm 3.2 IoT and the Cloud: A Hacked Personality and an Empty Battery Headache or an Intuitive Environment to Make our Lves Easier? Harmke de Groot; imec and Holst Centre (Invited Speaker)
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2:00pm 3.3 Challenge of MTJ-Based Nonvolatile Logic-in-Memory Architecture for Ultra Low-Power and Highly Dependable VLSI Computing
Masanori Natsui; Tohoku University (Invited Speaker) M. Natsui1,2,3, D. Suzuki4, A. Mochizuki1, N. Onizawa4, S. Ikeda2,3, T. Endoh2,3,5 and H.
Ohno2,3,6; 1Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku
University, Japan, 2Center for Spintronics Integrated Systems, Tohoku University, Japan, 3Center for Innovative Integrated Electronic Systems, Tohoku University, Japan, 4Frontier Research Institute for Interdisciplinary Science, Tohoku University, Japan, 5Graduate School of Engineering, Tohoku University, Sendai, Japan, 6Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, Japan
2:20pm 3.4 Enhanced Low Voltage Digital & Analog Mixed-Signal Performance with 28nm FDSOI Technology Franck Arnaud; STMicroelectronics (Invited Speaker)
2:40pm Break
SESSION 4 3D - Invited Monolithic 3D Alternative Technologies Chair: Zvi Or-Bach, MonolithIC 3D
\3:00pm 4.1 Invited Talk TBA Fabien Clermidy; CEA-Leti (Invited Speaker)
3:30pm 4.2 Invited Talk TBA Yang Du; Qualcomm (Invited Speaker)
4:00pm 4.3 Logic/Memory Hybrid 3D Sequentially Integrated Circuit Using Low Thermal Budget Laser Process Chi-Chao Yang; National Nano Device Laboratories (Invited Speaker)
4:30pm 4.4 Invited Talk TBA Subhasish Mitra; Stanford University (Invited Speaker)
5:00pm 4.5 Monolithic Three Dimensional Integration for Memory Scaling and Processing in Memory Subramanian Iyer; UCLA, Electrical Engineering Department (Invited Speaker)
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SESSION 5 Joint Poster Session Chair: Ali Khakifirooz, Cypress Semiconductor
5:30 -7:30pm Authors are available at their posters to answer questions and for discussion.
5.1 Nanowire FET Design for 7-nm SOI-CMOS Technology I. Jain1, A. K. Bansal1, A. Dixit1, T. B. Hook2; 1Department of Electrical Engineering, Indian Institute of Technology Delhi, Hauz Khas, New
Delhi, 2IBM Research, Albany, New York, USA
5.2 Analog Performance Improvement of Self-Cascode Structures Composed by UTBB Transistors Using Back Gate Bias
R. T. Doria1, R. Trevisoli1, M. de Souza1, M. A. Pavanello1, D. Flandre2; 1Electrical Engineering Department Centro Universitário da FEI, São Bernardo do Campo, Brazil,
2ICTEAM Institute Université Catholique de Louvain Louvain-la-Neuve, Belgium
5.3 CMOS-Compatible FDSOI Bipolar-Enhanced Tunneling FET P. Zhang1, J. Wan2, A. Zaslavsky1 and S. Cristoloveanu1; 1Department of Physics and School of Engineering, Brown University, Providence, RI, USA,
2IMEP-LAHC, INP-Grenoble/Minatec, Grenoble, France
5.4 Silicon-on-Ferroelectric-Insulator – A Comparative Analysis of the Partially and Fully Depleted Devices A. D. Es-Sakhi and M. H. Chowdhury; Computer Science and Electrical Engineering, University of Missouri Kansas City,
Kansas City MO, USA
5.5 Low Voltage Ripple Carry Adder with Low-Granularity Dynamic Forward Back-Biasing in 28 nm UTBB FD-SOI R. Taco1, I. Levi2, M. Lanuzza1 and A. Fish2; 1Department of Computer Science Modeling, Electronics and System Engineering, University of
Calabria, Rende, Italy, 2Department of Electrical Engineering, Bar-Ilan University, Ramat-Gan, Israel
5.6 Minimum-Energy Point Design in FDSOI Regular-Vt L. Koskinen1, M. Hiienkari1, M. Trunquist2, P. Flatresse3; 1University of Turku Technology Research Center, Turku, Finland, 2Aalto University Department
of Micro and Nanosystems, Espoo, Finland, 3STMicroelectronics
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Joint Poster Session cont’d.
5.7 Analysis of Deeply Scaled Multi-Gate Devices with Design Centering across Multiple Voltage Regimes S. Chen, X. Lin, A. Shafaei, Y. Wang, M. Pedram; Department of Electrical Engineering, University of Southern California, Los Angeles, CA, USA
5.8 Monolithic 3D Layout using 2D EDA for Embedded Memory-Rich Designs I. Pletea1, Z. Wurman2, Z. Or-Bach2, V. Sontea3; 13D-EDA SRL, Iasi, Romania, 2MonolithIC 3D Inc., San Jose, CA, USA, 3Technical University of
Moldova Chisnau, Moldova 5.9 Preliminary Steps Towards Implementing Intimate 3D-IC Stacking with Layer Transfer and
Atomic Bonding Methods M. Current1, W. Lukaszek2, Shari Farrens3, T. Fong4; 1Current Scientific, San Jose, CA, 2Wafer Charging Monitors, Woodside, CA, 3Hidden Glenn
Consulting, Boise, ID, 4Silicon Genesis, San Jose, CA
WEDNESDAY, OCTOBER 7
7:00am Continental Breakfast
SESSION 6a Advanced Device Architecture Chair: Nadine Colaert, imec
8:00am 6a.1 Opportunities and Challenges of Nanowire-based CMOS Sylvain Barraud; CEA-Leti (Invited Speaker)
8:40am 6a.2 Performance Trade-offs in FinFET and Gate-All-Around Device Architectures for 7nm-node and Beyond S.-D. Kim1, M. Guillorn1, I. Lauer1, P Oldiges2, T. Hook2 and M-H. Na1; 1IBM Research, Hopewell Junction, NY, 2IBM Research, Essex Junction, VT
9:00am 6a.3 Quasi-Static Analytical Model for the Dynamic Operation of Triple-Gate Junctionless Nanowire Transistors R. Trevisoli, R. T. Doria, M. de Souza and M. A. Pavanello; Electrical Engineering Department Centro Universitário da FEI, São Bernado do Campo, Brazil
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Session 6a cont’d.
9:20am 6a.4 Transconductance Hump in Vertical Gate-All-Around Tunnel-FETs F. S. Neves1, P.G.D. Agopian1, J.A. Martino1, B. Cretu2, A. Vandooren3, R. Rooyackers3,
E. Simoen3, A. Thean3, and C. Claeys3,4; 1University of Sao Paulo, Sao Paulo, Brazil, 2ENSICAEN, Caen, France, 3imec, Leuven, Belgium,
4KU Leuven, Belgium
9:40am 6a.5 Comparative Simulation Study on MoS2 FET and CMOS Transistor M. Zhang, P.-Y. Chien, J.C.S. Woo; Department of Electrical Engineering, University of California, Los Angeles, USA
SESSION 6b Digital Chair: David Bol, Université catholique de Louvain
8:00am 6b.1 CMOS Reliability Challenges and the Low Power Domain Chetan Prasad; Intel Corporation (Invited Speaker)
8:40am 6b.2 A Soft Error Tolerant 4T Gain-Cell Featuring a Parity Column for Ultra-Low Power Applications R. Giterman1, A. Teman2, L. Atias1 and A. Fish1; 1Faculty of Electrical Engineering, Bar-Ilan University, Ramat Gan, Israel, 2Institute of Electrical
Engineering, EPFL, Lausanne, VD, Switzerland
9:00am 6b.3 Impact of Technology and Voltage Scaling on LEON3 Processor Performance and Energy X. Lin, A. Shafaei, S. Chen, T. Cui and M. Pedram; Department of Electrical Engineering, University of Southern California, Los Angeles, CA USA
9:20am 6b.4 Subthreshold Capable, Asynchronous FPGA in a 14nm SOI Process B. Degnan and J. Hasler; The Georgia Institute of Technology, USA
9:40am 6b.5 A 300nW Near-Threshold 187.5 – 500 kHz Programmable Clock Generator for Ultra-Low Power SoCs
M. Faisal1,2, N. E. Roberts1,3 and D.D. Wentzloff1; 1University of Michigan, 2Movellus Circuits, Inc., 3PsiKick Inc., Ann Arbor, MI, USA
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SESSION 6C Invited Talks on M3DI Chair: Zvi Or-Bach, MonolithIC 3D
8:00am 6c.1 Vacuum as New Element of Transistor Jin-Woo Han; Center for Nanotechnology, NASA Ames Research Center (Invited Speaker) 8:40am 6c.2 Heterogeneous Integration Enabled by Advanced Wafer Bonding Thomas Uhrmann; EVGroup (EVG) (Invited Speaker) 9:20am 6c.3 Ultra‐thin Chips for Flexible Electronics and 3D Ics Joachin Burghartz; Institute for Microelectronics Stuttgart (Invited Speaker)
10:00am Break
SESSION 7a High Frequency Chair: Emmanuel Augendre, CEA- Leti
10:20am 7a.1 GlobalFoundries 22FDX-rfaTM Fully-Depleted Independent Multi-Gate Technology for Highly-Integrated RF Thomas G. McKay; GlobalFoundries (Invited Speaker)
11:00am 7a.2 Switch Branch in Trap-Rich RFSOI with 84 dBm Off-State IP3 T.G. McKay1, P.R. Verma2, S. Zhang2, J. S. Wong2, J. Brunner3; 1Globalfoundries, Santa Clara, CA, USA, 2Globalfoundries, Singapore, 3Kaelus, Inc.,
Centennial, CO, USA
11:20am 7a.3 Comparative Study of Parasitic Elements on RF FoM in 28 nm FD SOI and Bulk Technologies B. Kazemi Esfeh1, V. Kilchytska1, N. Planes2, M. Haond2, D. Fandre1, J.-P. Raskin1; 1ICTEAM, Université catholique de Louvain, Louvain-la-Neuve, Belgium, 2STMicroelectronics,
Crolles, France
11:40am 7a.4 SiGe-on-Insulator Symmetric Lateral Bipolar Transistors J.-B. Yau, J. Cai, J. Yoon, C. D’emic, K.K. Chan, T.H. Ning, S.U. Engelmann, D.-G. Park, R.T. Mo; IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY, USA
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SESSION 7b Energy Harvesting Chair: Dennis Buss, Texas Instruments
10:20am 7b.1 Frictionless Wearable Technology: The Key to Unleashing the Power of Wearable Sensors for Health and Lifestyles
Chris Van Hoof; imec (Invited Speaker)
11:00am 7b.2 Extending the Bandwidth of Piezo-Electric Energy Harvesting through the use of Bias Flip S. Zhao1, A. Paidimarri2, N. Ickes2, M. Araghchini2, J. Lang2, J. Ma1, Y. Ramadass3, D. Buss3; 1Tianjin University School of Electronic Information Engineering, Tianjin, P.R. China, 2Massachusetts Institute of Technology, EECS Department, Cambridge, MA, USA, 3Texas Instruments, Inc., Dallas, TX, USA
11:20am 7b.3 Optimization of Gate Controlled Diode in Rectenna for High Efficiency RF Energy Harvesting S. O’uchi, Y.X. Liu, Y. Ishikawa, J. Tsukada, T. Nakagawa, W. Mizubayashi, S. Migita, N. Morita,
H. Ota, H. Koike, K. Endo, and T. Matsukawa; Division of Electrical Engineering, Kanazawa Institute of Technology, Ohgigaoka, Nonoichi, Ishikawa, Japan
11:40am 7b.4 0.8-V Rail-to-Rail Operational Amplifier with Near-Vtͭ Gain-Boosting Stage Fabricated in FinFET Technology for IoT Sensor Nodes S.-I. O’uchi, Y. Liu, T. Nakagawa, W. Mizubayashi, S. Migita, N. Morita, H. Ota, Y. Ishikawa,
J. Tsukada, H. Koike, M. Masahara, K. Endo, and T. Matsukawa; Nanoelectronics Research Institute National Institute of Advanced Industrial Science and
Technology (AIST), Tsukuba, Ibaraki, Japan
SESSION 7c Selected Papers on M3DI Chair: Olivier Faynot, CEA-Leti
10:20am 7c.1 Modified ELTRAN® - A Game Changer for Monolithic 3D Z. Or-Bach, B. Cronquist, Z. Wurman, I. Beinglass and A.K. Henning; MonolithIC 3D Inc., San Jose, CA, USA
11:00am 7c.2 Power, Performance, and Cost Comparisons of Monolithic 3D ICs and TSV-based 3D ICs D.K. Nayak1, S. Banna1, S.K. Samal2 and S.K. Lim2; 1Technology Research GLOBALFOUNDRIES, Santa Clara, CA, USA, 2School of Electrical and
Computer Engineering Georgia Institute of Technology, Atlanta, GA, USA
11:20am 7c.3 Guidelines on 3DVLSI Design Regarding the Intermediate BEOL Process Influence A. Ayers1,2,3, O. Rozeau1, B. Borot2, L. Fesquet3, G. Cibrario1, P. Batude1, M. Vinet1; 1CEA-Leti, Minatec campus, Grenoble, France, 2STMicroelectronics, Crolles, France, 3Université
Grenoble-Alpes / TIMA & CNRS / TIMA, Grenoble Institute of Technology, Grenoble, France
11:40am 7c.4 Improving Performance in Near-Threshold Circuits Using 3D IC Technology S.K. Samal1, Y. Li2, G.Q. Chen2 and K. Lim1; 1School of ECE, Georgia Institute of Technology, Atlanta, GA, USA, 2Advanced Micro Devices,
Beijing, China
12:00pm Lunch and Free Time (on own)
Optional Fundamentals Classes
1:00-5:00pm • Logic Devices for 28nm and Beyond
• Low-Voltage Logic and Memory Circuits and Power Management
6:00pm Cookout
Evening Panel Discussion
8:00pm What Does IoT Mean for Si Technology? Panelists Include: Christophe Chevallier, Director of Memory Design, Ambiq Micro Stanley S. C. Song, Qualcomm Technologies, Inc. Ali Niknejad, University of California, Berkeley Norikatsu Takaura, Hitachi
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THURSDAY, OCTOBER 8
7:00am Continental Breakfast
SESSION 8 Plenary Talk II Chairs: Mostafa Emam, Incize • Fred Allibert, Soitec
8:00am 8.1 Needs and Benefits of SOI Integration and Die Stacking for Power Management Applications Hans Stork; ON Semiconductor (Invited Speaker)
8:40am 8.2 Advanced Channel Materials for the Semiconductor Industry Nadine Collaert; imec (Invited Speaker)
SESSION 9a Advanced Processes & Characterization Chair: J. A. Martino, University of São Paulo
8:00am 9a.1 Special Characterization Techniques for Advanced FDSOI Process Sorin Cristoloveanu, IMEP – INP Grenoble MINATEC (invited speaker)
8:40am 9a.2 Impact of Source/Drain Silicon Cap on FDSOI SiGe pMOSFET Performance E. Augendre1, S. Maitrejean1, B. De Salvo1, L. Grenouillet1, R. Wacquez1, M. Vinet1, O. Faynot1,
P. Morin2, N. Loubet2, Q. Liu2, F. Chafik2, S. Pilorget2, B. Lherron2, H. Kothari2, Y. Mignot2, Y. Escarabajal2, F. Allibert3, K. Cheng4, B. Doris4;
1CEA-Leti, 2STMicroelectronics, 3SOITEC, 4IBM
9:00am 9a.3 Experimental study on Quantum Mechanical Effect for Insensitivity of Threshold Voltage against Temperature Variation in Strained SOI MOSFETs
C.-H. Jeon1,2, B.-H. Lee1,2, B.C. Jang1, S.-Y. Choi1 and Y.-K. Choi1; 1Department of Electrical Engineering, Korea Advanced Institute of Science and Technology,
Daejeon, Republic of Korea, 2Semiconductor R&D Center, Samsung Electronics, Hwasung-City, Gyeonggi-Do, Republic of Korea
9:20am 9a.4 Full Front and Back Split C-V Characterization of CMOS Devices from 14nm Node FDSOI Technology B. Mohamad1,2, G. Ghibaudo2, C. Leroux1, E. Josse3, G. Reimbold1; 1CEA-Leti, MINATEC Campus, Grenoble, France, 2University Grenoble Alpes, IMEP-LAHC, MINATEC/INPG, Grenoble, France, 3STMicroelectronics, France
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9:40am 9a.5 Impact of Supercoupling Effect on Mobility Enhancement in UTBB SOI MOSFETs in Dynamic Threshold Mode
K. R. A. Sasaki1,2, C. Navarro1, M. Bawedin1, F. Andrieu3, J. A. Martino2 and S. Cristoloveanu1; 1IMEP-LAHC, Grenoble-INP, Minatec, Grenoble, France, 2LSI/PSI/USP, University of São Paulo,
São Paulo, Brazil, 3CEA-LETI Minatec, Grenoble, France
10:00am Break
SESSION 9b Memory Chair: Yang Du, Qualcom
10:20am 9b.1 Low Power Design: Ramping to Production Christophe Chevallier; Ambiq Micro (Invited Speaker)
10:40am 9b.2 0.5-V 350-ps 28-nm FD-SOI SRAM Array with Dynamic Power-Supply 5T Cell K. Itoh, K. A. Shaik and A. Amara; Institut supérieur d’électronique de Paris (ISEP), Issy-les-Moulineaux, France
11:00am 9b.3 A 1kb Single-sided Rear 6T Sub-threshold SRAM in 180 nm with 530 Hz Frequency 3.1 nA Dynamic Current and 2.4 nA Leakage at 0.27 V
M. Pons, T.-C. Le, C. Arm, D. Séverac, S. Emery, C. Piguet; CSEM Centre Suisse d’Électronique et de Microtechnique, SA, Switzerland
11:20am 9b.4 Design Insights for Reliable Energy Efficient OxRAM-based Flip-flop in 28nm FD-SOI N. Jovanovic1, E. Vianello1, O. Thomas1, B. Nikolic2, L. Naviner3; 1CEA-LETI MINATEC Campus, Grenoble, 2UC-Berkeley, BWRC, 3Telecom Paris Tech
11:40am 9b.5 10nm Gate-Length Junctionless Gate-All-Around (JL-GAA) FETs Based 8T SRAM Design Under Process Variation Using a Cross-Layer Simulation
L. Wang, A. Shafaei, S. Chen, Y. Wang, S. Nazarian and M. Pedram; Department of Electrical Engineering, University of Southern California, Los Angeles, CA, USA
12:00pm Lunch (on own)
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SESSION 10a Power Management Chair: Philippe Flatresse, STMicroelectronics
3:00pm 10a.1 High Voltage SOI Technology Piet Wessels; NXP (Invited Speaker)
3:20pm 10a.2 ESD Protection Design with Latchup-Free Immunity in 120V SOI Process Y.-J. Huang1, M.-D. Ker1, Y.-J. Huang2, C.-C. Tsai2, Y.-N. Jou2, and G.-L. Lin2; 1Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, 2Vanguard
International Semiconductor Corporation, Hsinchu, Taiwan
3:40pm 10a.3 Key Parameters of BiMOS ESD Protection Device for UTBB FDSOI Advanced Technology S. Athanasiou1,2, S. Cristoloveanu2, P. Galy1; 1STMicroelectronics, Crolles, France, 2IMEP-LAHC, Grenoble, France
4:00pm 10a.4 A -1.8V to 0.9V Body Bias, 60 GOPS/W 4-Core Cluster in Low-Power 28nm UTBB FD-SOI Technology D. Rossi1, A. Pullini2, M. Gautschi2, I. Loi1, F.K. Gurkaynak2, P. Flatresse3, L. Benini1,2; 1University of Bologna, Bologna, Italy, 2ETHZ, Zurich, Switzerland, 3STMicroelectronics, Crolles,
France
4:20pm 10a.5 The Missing XDXMOS Found! - A SOTB Circuit Acceleration Technique Using Front and Back Gate Interaction
H. Koike and T. Sekigawa; Electroinformatics Group, Nanoelectronics RI, National Institute of AIST, Japan
SESSION 10b Analog Chair: Lauri Koskinen, University of Turku
3:00pm 10b.1 Negative Capacitance in Ferroelectric Materials and Implications for Steep Transistor Sayeef Salahuddi; UC Berkeley (Invited Speaker)
3:20pm 10b.2 A ∆VT 0.2V to 1V 0.01mm2 9.7nW Voltage Reference in 65nm LP/GP CMOS G. de Streel1, J. De Vos2 and D. Bol1; 1ICTEAM Institute, Université catholique de Louvain, Louvain-la-Neuve, Belgium, 2e-peas, Belgium
3:40pm 10b.3 Towards Ultra-Low-Voltage Wideband Noise-Cancelling LNAs in 28nm FDSOI G. de Streel1, D. Flandre1, C. Dehollain2 and D. Bol1; 1ICTEAM Institute, Université catholique de Louvain-la-Neuve, Belgium,
2RFIC, Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland
4:00pm 10b.4 Advantages of Subthreshold Operation of Asymmetric Self-Cascode SOI Transistors Aiming at Analog Circuit Applications
M. de Souza1, D. Flandre2 and M. A. Pavanello1; 1Electrical Engineering Department Centro Universitário da FEI, São Bernardo do Campo, Brazil,
2Université Catholique de Louvain: ICTEAM Institute, Louvain-la-Neuve, Belgium
4:20pm 10b.5 A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs Y. Huang1, A. Shrivastava2 and B. H. Calhoun1;
1University of Virginia, Charlottesville, VA, 2PsiKick Inc., Charlottesville, VA
SESSION 11 Joint Late News Chairs: Bruce Doris, IBM • Olivier Faynot, CEA-Leti
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SHORT COURSES
MONDAY, OCTOBER 5 • 8:00am
The technical sessions are preceded by two different, one-day short courses on Monday, October 5th. Short course attendees will receive course materials for both short courses and have the freedom to move between the two courses. Continental breakfast and lunch are also included.
SESSION ONE: An Introduction to SOI Applications; From Low to Smart Power Applications
The number of mobile subscribers worldwide reached 95.5% of the world’s population in 2014 and is ex-pected to reach 9.3B by 2019. Although our behavior
as consumers is constantly redefining the requirements for what we know as the Internet-of-Things (IoT) today, IoT will continue to introduce numerous opportunities for the indus-try. This fast growing trend is driving end markets towards satisfying stringent demands of mobile connected users. In order to support such growth; low cost, low power, more integration, small form factor and fast time to market remain as key enabling requirements. This short course will discuss the role of SOI engineered substrates in addressing the chal-lenges and needs for ultra-low power to high power SOI applications, including:• FDSOI for digital applications providing attractive power/ performance/cost benefits with added functionality address-ing ultra- low power cost sensitive IoT applications• High resistivity SOI for RF applications providing high per-formance integrated solutions addressing the rapid adop-tion of wireless standards and the escalating demand for data bandwidth • SOI for emerging Si based Photonics applications enabling data centers to meet the demands of cloud computing and big data applications.
Considering the role of cars, smart homes and smart cities in the overall IoT ecosystem, and the continued strive for better reliability and better global efficiency; the short
course will also cover the role power SOI plays in providing better performance and higher reliability for automotive and other consumer and industrial smart power applications.
An Introduction to SOI Applications: from Low to Smart PowerMariam Sadaka; Soitec (instructor)
CMOS SOI Technology for High Performance ComputingTerry Hook and Paul Chang; IBM (instructor)
Designs of Ultra-Low-Power and Ultra-Low-Leakage 65nm-SOTB LSI for IoT ApplicationsKoichiro Ishibashi; University of Electro-Communications, Tokyo (instructor)Review of RF SOI Technology: A 10 year Economic Success Story Now Looking Forward to 5GFred Gianesello; STMicroelectronics (instructor)
Design Considerations for Space ApplicationsTony Amort; Boeing Corporation (instructor)
SOI Nanoelectromechanical Systems (NEMS) VLSI for ‘More Than Moore’ ApplicationsPhilip Feng; Case School of Engineering, Case Western Reserve University (instructor)
SOI APPLICATIONS
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MONOLITHIC 3D INTEGRATION
Technological Approaches to CMOS IntegrationZvi Or-Bach; Monolithic 3D (instructor)
3DIC with High Density Face to Face ProcessesPaul Franzon; NCSU (instructor)
CEA-Leti Monolithic 3D TechnologyOlivier Faynot; CEA-Leti (instructor)
3D VLSI Design – CAD and EDAYang Du, Samadi Kambiz; Qualcomm (instructor)
Case Studies for Monolithic 3DZvi Or-Bach; Monolithic 3D (instructor)
Monolithic RRAMMatt Marinella; Sandia Labs (instructor)
FUNDAMENTALS CLASSES
WEDNESDAY, OCTOBER 7Both SOI and SubVT Fundamentals Classes run concurrently and those who purchase the Fundamentals Classes may move freely between the two classes. The Fundamentals Classes run from 1:00 am to 5:00 pm.
Logic Devices for 28nm and Beyond
1:35pm Bulk Planar Devices at 28nm & Transition to Fully Depleted SOI Thierry Poiroux; CEA-Leti (instructor)
• Challenges of 28nm technology node: requirements for 28nm node; main challenges in process integration; challenges of conventional bulk device architecture.
• Transition to fully depleted SOI technology: process integration specificities; device electrostatic control; back bias effect and double gate operation; multiple threshold voltage offer; FDSOI transistor key advantages.
2:20pm Planar FDSOI Devices Today and Next Generations Benefits for Performance and Low Power Applications Philippe Flatresse; STMicroelectronics (instructor) STMicroelectronics has developed a full design platform leveraging on body biasing considered as the
key solution to provide best-in class SOCs to the market. The talk will describe the capability of body biasing, showing it is not only well suited for performance boosting but also for power optimization and compensation. Body biasing implementation techniques will be shared and their benefits per market segment.
3:05pm FinFETs Benefits for Ultimate Shrinking and SOI vs Bulk FinFETs Terry Hook; IBM (instructor) We will review FinFETs past, present, and future and discuss our perception of ultimate scaling limits .
Although FinFETs were first introduced into mainstream technology at the 22nm node, they had been studied for at least 15 years prior to that. While to many in the industry FinFETs are still very new, we are already looking ahead to see when they run out of steam. Today we have FinFETs realized at the 14nm node and the 10nm node, and rumors of 7nm. What might FinFETs look like at these various nodes, and can we see through a glass darkly to 5nm? If not FinFETs, then what are other likely device options for continued scaling? There are a number of candidates on everyone’s short list, such as nanowires, vertical fets and three-dimensional integration. What role might SOI play in the future of advanced devices?
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3:50pm 2D and 3D SOI MOSFET in a Harsh Environment Michael Alles; Vanderbilt’s Institute for Space and Defense Electronics (instructor)
We will review FinFETs past, present, and future and discuss our perception of ultimate scaling limits. Although FinFETs were first introduced into mainstream technology at the 22nm node, they had been studied for at least 15 years prior to that. While to many in the industry FinFETs are still very new, we are already looking ahead to see when they run out of steam. Today we have FinFETs realized at the 14nm node and the 10nm node, and rumors of 7nm. What might FinFETs look like at these various nodes, and can we see through a glass darkly to 5nm? If not FinFETs, then what are other likely device options for continued scaling? There are a number of candidates on everyone’s short list, such as nanowires, vertical fets and three-dimensional integration. What role might SOI play in the future of advanced devices?
Low Voltage Logic and Memory Circuits and Power Management
Section 1 Low-voltage Logic and Memory Circuits and Power Management Pascal Meinerzhagen; Intel Circuit Research Lab (instructor) With the onset of wearable computing devices and the Internet of Things (IoT), there is an increasing
demand for low-power computing and on-chip storage, as well as efficient power delivery. The first part of this fundamental class, targeted at beginner- and intermediate-level digital designers, reviews circuit techniques to achieve low power consumption in both logic and memory circuits, while ensuring robust operation. Topics include:
• Applications requiring low power consumption • Power consumption in digital circuits: active, leakage • Concept of minimum-energy point (MEP), motivation for near-Vt operation • Examples of near-threshold computing (NTC), including Intel’s experimental Claremont processor • Voltage & frequency guard-band reduction techniques (such as Razor), detecting and correcting timing errors • Failure mechanisms in 6T SRAM for low-voltage operation • Low-voltage SRAM bitcells and assist techniques • Alternative low-voltage (including sub-Vt) memories: standard-cell based memories • Resilient register file (RF) with double-sampling read path
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Section 2 Analog and Digital Integrated Power Management Circuits Joseph Shor; Bar Ilan University, Israel (instructor)
Recently, there has been a trend to integrate power management circuits on die in order to save power and cost. This tutorial will survey recent work in Integrated Power Management Circuits. It is intended for the beginner/intermediate analog and digital designers who wish to enhance their knowledge in power management circuits. Topics include:
• Low voltage Bandgap reference voltages and current references • Low Drop Out regulators (LDO), both for digital and analog supplies • Integrated Switching, inductor-based voltage regulators • Charge-Sharing Regulators • Thermal Sensors and thermal management • Analog design in leading edge processes
Welcome Reception, Monday, 6:00pmou are cordially invited to join us as we kick off our 2015 Conference. Join your fellow attendees, presenters and in-structors for our kick-off event. It’s a great way to meet up with old friends and make some new ones. There will be good company and good conversations - all that’s missing is you!
Poster Session and Reception, Tuesday, 5:30pmJoin us for hors d’oeuvres and drinks as authors present their posters. Authors will be available at their posters to answer questions and discuss their works during the Poster Session, 5:30pm to 7:30pm, Tuesday. Posters without pre-senting authors will be on display for the remainder of the conference.
Hospitality Suite • Tuesday thru ThursdayThis year we will have for our member’s convenience a hospitality suite located in the hotel. This will be a loca-tion that everyone will have access to during conference hours. Think of it as a place where you can get away from conference proper. Sit down in comfortable surroundings and enjoy a conversation with colleagues. Have a light re-freshment and just get away from things for a few minutes.
Cookout, Wednesday, 6:00pmOur conference would not be complete without our cook-out. Combining great food and pleasant company is all part of what makes our conference so special. The cook-out is another great way to network and meet your fellow attendees. Relax and enjoy yourself and prepare for the Evening Panel Discussion, which will follow immediately.
Evening Panel/Rump Session ● Wednesday, 8:00pm
What does IoT mean for Si Technology?Chair: Ali Khakifirooz, Cypress SemiconductorGartner’s 2014 Emerging Technologies Hype Cycle puts Internet of Things at the Peak of Inflated Expectations. Not only many online forums are inflated with debates
on IoT-related topics, but more importantly virtually all semiconductor companies made announcement pertain-ing their plans to address this potentially massive market. With the internet of people reaching a plateau, IoT is con-sidered by many as a new wave for the continued growth of the semiconductor industry. However, apart from vague discussions related to the system cost or long battery-life requirements, little is discussed on the implications of IoT on wafer manufacturing and chip design. The fact that legacy CMOS technologies in fully amortized fabs are ad-vertised as the solution to IoT market to lower the leakage current at the same time that leading edge technologies, mainly 28nm, are being tweaked to lower the cost and ac-tive power, is a testimony to the existence of a wide range of opinion regarding IoT requirement. This is in part due to the extremely wide range of complexity that one can imagine for IoT: from a simple egg-counter in the fridge to a system that understands human emotions. A smartphone plus its user can be viewed as a smart IoT node where the user provides a very wide range of computing capa-bility. However, this smart computing power is beyond the capability of many classical IoT nodes being discussed today. The ultimate application of IoT can be unlocked once such level of smartness is implemented either on the server side or better yet at each node.
At the 2015 edition of IEEE S3S Conference we are fortunate to have a diverse panel of experts to cover “What does IoT mean for Si technology” at the Rump Session. The open atmosphere of the session and the participation of an audience that drives the semiconductor technology in R&D, manufacturing, and design as well as academia provide a unique opportunity for debate.
The panelists for this year’s Rump Session are:Christophe Chevallier, Ambiq Micro Stanley S. C. Song, Qualcomm Technologies Inc.Ali Niknejad, UC BerkeleyNorikatsu Takaura, Hitachi
ADDITIONAL INFORMATION AND AGENDA
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Enjoy a warm welcome and homelike surroundings at the Double-Tree by Hilton Hotel Sonoma Wine Country hotel. Ideally located in the heart of Sonoma County, the hotel is near Santa Rosa and
Petaluma and less than an hour’s drive from Napa and San Francisco. Experience Sonoma County’s world renowned wineries, exquisite
dining and picturesque countryside and enjoy popular attractions such as Armstrong Redwoods and the Safari West Wildlife Reserve.
Looking for a bite to eat? The Bacchus Restaurant offers fine din-ing in a casual atmosphere. Open from 6:30am to 10:00pm daily. The restaurant is located adjacent to our conference space. Looking for
something to quickly start your day, Starbucks has a coffee bar that is open during the morning hours. Stop by between 6:30am and 11:00am for light snacks or that quick fix of caffeine. Need to take that call in your room? In-room dining is also an option between 6:00am and 11:00pm daily. Want to get out and stretch your legs for lunch? Not a problem, there are quick eateries within a 10-minute walk of the hotel.
HOTEL RATES • The DoubleTree by Hilton Sonoma Wine Country is pleased to offer the special, discounted rate of $138 plus tax and tourism (+14.1% occupancy tax) per night single/double occupancy for conference attend-ees. This rate will be good from Saturday, October 3rd, 2015 thru Thursday, October 8th, 2015 (allows for Friday morning check out).Please note: extending past Thursday may be possible, but due to the US Columbus Day Holiday on Monday, October 5th, we expect the holiday weekend to sell out quickly. Please contact the hotel directly for pricing and availability. A major credit card or deposit is needed when you make a reservation to guarantee your room.
All hotel reservations must be made by 5:00pm PST, September 18th, 2015. After this time, reservations will only be accepted if space is available. We highly recommend you make your reservations early. This year, we are running up against a holiday weekend, so rooms in the area are at a premium. Once our block closes, those rooms will be released to the public.
If you have a problem making a reservation, please contact the Conference Manager for assistance. [email protected]
STUDENT RATES • We have a few rooms available for students at a discounted rate. First priority will go to those students who are presenting papers. Please contact [email protected] for assistance.
GOVERNMENT RATE ROOMS • We have a limited number of government rate rooms for this year’s conference. They will be on a first come, first serve basis and are at the rate of $121 (14.1% occupancy tax). You will be required to show a valid US Government ID when you check in. If you qualify for this rate, please use this Government Rate link.CHECK-IN/CHECK-OUT TIMES • Check-in time is 3:00pm and check-out time is 12:00pm. Guests are per-mitted to check in early or check out later subject to room availability.HOW TO MAKE A RESERVATION
• VIA INTERNET A dedicated web page has been created for conference attendees to book their sleeping rooms. At-tendees are able to make, modify and cancel hotel reserva-tions online. Reservations are now open and may be made here: ONLINE HOTEL RESERVATIONS
• VIA TELEPHONE +1 707 584 5466 tell them you will be attending the IEEE International S3S Conference.
CONFERENCE HOTEL DOUBLETREE BY HILTON
SONOMA WINE COUNTRY
One Doubletree Drive, Rohnert Park, CA 94928+1 707-584-5466
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WEDNESDAY AFTERNOON • If you do not plan to attend the optional Fundamentals Class your Wednesday afternoon is free until the 6:00pm cookout. Take some time and visit the area. There are plenty of things to see and do.
Some Area Highlights • The DoubleTree Hotel Sonoma Wine Country puts you in the middle of California’s pre-mier wine country with easy access to:• Hundreds of well-known wineries• Bodega Bay on the Sonoma Coast• Historical sites and missions• The Armstrong Redwood Forest• Numerous golf courses, shops and restaurants• Family attractions like Charles Schulz Museum (creator of the Peanuts gang) • The Safari West Wildlife Preserve• For more detailed information on the area visit the Sonoma County Website
Just 60 Minutes to San Francisco often called “Everybody’s Favorite City,” for its scenic beauty, cultural attractions, di-verse communities, and world-class cuisine. This 49 square miles city is very walk-able and dotted with landmarks like the Golden Gate Bridge, cable cars, Alcatraz and the larg-est Chinatown in the United States. A stroll through the City can lead from Union Square to North Beach to Fisherman’s Wharf, each with intriguing neighborhoods. Views of the Pacific Ocean and San Francisco Bay are often laced with fog, creating a romantic mood in this most European of American cities.WEATHER • The Sonoma Valley like most of northern Cal-ifornia has temperate weather all year round with tempera-tures seldom above 75°F degrees (21°C) or below 40°F (5°C). A sweater or lightweight top layer are recommended when venturing outside in the evenings. The area does get rain, but October usually only sees about 1 to 2 inches. So be aware, an umbrella may be necessary.
AREA AND ACTIVITIES
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AIRPORT �������������������������������The nearest international airport is San Francisco International Airport (SFO). This is the largest airport and has the most options for both international and domestic travel. There is no bus service
.............................................. Charles M. Schulz Sonoma County Airport (STS) is the local regional airport serviced by Alaska Airlines (they partner with several domestic and international carriers). Pricing for STS can be quite high. Please price out your options before making any decisions. There is no shuttle service to the hotel.
RENTAL CARS ���������������������The San Francisco International Airport offers representation from all the major car rental companies. For a complete listing and contact information please see SFO Rental Cars.
.............................................. Sonoma County Airport offers a more limited selection of car rental companies from which to choose. For a complete listing and contact information please see STS Rental Cars.
SHUTTLE SERVICE �������������The Sonoma County Airport Express operates a shuttle between SFO, and Sonoma County Airport and drops off directly at our hotel (DoubleTree by Hilton Sonoma Wine Country).
Schedules and fares can be located on their website. We suggest talking directly with Airport Express for complete details and to make arrangements.
Super Shuttle - Available at San Francisco airports offers direct service to the DoubleTree. Roundtrip pricing is estimated at around $175.00.
PARKING AT THE DoubleTree by Hilton Sonoma Wine Country Self-Parking is FREE at the DoubleTree, however, there is no valet service at the facility.
AIRPORT AND TRANSPORTATION
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ON-SITE CONFERENCE REGISTRATION SCHEDULE
Sunday, October 4, 2015 6:00pm – 8:00pm
Monday, October 5, 2015 7:00am – 5:00pm
Tuesday, October 6, 2015 7:00am – 5:00pm
Wednesday, October 7, 2015 7:00am – 12:00pm
Thursday, October 8, 2015 7:00am – 12:00pm
TO PAY BY CREDIT CARD To pay by credit card please use our ONLINE registration form. We accept Visa, Mas-terCard and American Express. You will need to have the card with you when regis-tering as you need to provide the security code when you enter your card information. The 3-digit security code for Visa and MasterCard is located on the back of the card. The 4 digit code for American Express is located on the front of the card.
TO PAY BY CHECK Complete the registration form and mail it with your check to: IEEE S3S Conference, 6930 De Celis Place, #36, Van Nuys, CA 91406
Please make the check payable to 2015 IEEE S3S Conference. All checks must be drawn on a US bank and in US funds only. Registration forms received without pay-ment will not be honored.
BANK - WIRE TRANSFERS While payment may be made via bank transfer (by wiring funds), it is discouraged and there is an additional $25 fee per transfer to cover handling costs. If a bank transfer is necessary, please contact the conference manager at [email protected] for further instruc-tions and the appropriate account numbers.
REGISTERING VIA PHONE Registration by telephone is not available.
CANCELLATIONS Cancellation requests must be made in writing to the conference manager. Refund re-quests received by September 20, 2015 will receive a refund of registration fees less a $50 processing fee. All refunds will be processed after the conference.
QUESTIONS If you have any questions or concerns, please contact the conference manager at [email protected] or call (818) 795-3768.
CONFERENCE REGISTRATION
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Mail check payable to 2015 IEEE S3S Conferenceand mail along with this completed form to:
2015 IEEE S3S CONFERENCE6930 De Celis Place #36, Van Nuys, CA 91406
Please complete the following for credit card payment only: Charge registration fees to my:
o American Express o MasterCard o VISA Card
CARD NUMBER
EXP. DATE SECURITY CODE
NAME AS IT APPEARS ON CREDIT CARD (PLEASE PRINT)
CARDHOLDER’S SIGNATURE
NAME TO APPEAR ON BADGE
*LAST NAME, FIRST NAME, MIDDLE INITIAL
*COMPANY OR AGENCY
FOR STUDENT REGISTRATION, please give school attending & graduation year
*PREFERRED MAILING ADDRESS *MAIL STOP
*CITY/STATE/ZIP/COUNTRY
* TELEPHONE NUMBER *FAX NUMBER
*E-MAIL ADDRESS
IEEE MEMBER NUMBERDo you have any special needs or dietary restrictions? if yes - please let us know so we can make proper arrangements:
* As you want it to appear on the Conference List of Attendees
Payment must accompany registration. Registrations without payment will not be accepted. Wire transfers must be approved in advance and are subject to a $25 fee. No telephone registrations available.
For additional information, please contact conference manager: Joyce Lloyd, 6930 De Celis Place # 36, Van Nuys, CA 91406
Telephone: 818-795-3768 • Fax: 818-855-8392 [email protected]
REGISTRATION FEESAdvance registration fees apply to completed forms and payment received by September 11, 2015
Conference By Sept. 11th After Sept. 11thIEEE Member o $550 o $600 $_________IEEE Member/Student o $275 o $325 $_________Non Member o $700 o $750 $_________Non Member/Student o $350 o $400 $_________
Short Course Tutorial IEEE Member o $400 o $450 $_________IEEE Member/Student o $125 o $150 $_________Non Member o $450 o $500 $_________Non Member/Student o $175 o $200 $_________
Fundamentals Class Before or after Sept. 11thIEEE Member o $200 $_________IEEE Member/Student o $75 $_________Non Member o $250 $_________Non Member/Student o $100 $_________ Total Registration Fees $_________Short Course and Fundamental Class admission may be purchased without a full membership. Contact [email protected] with any questions.
We welcome guests at our cookout (The cookout is included in registration. Below is for guest purchases only.)
Guest Cookout Wednesday _______ @ $80 ea. = $___________ Total Additional Fees $__________
TOTAL ENCLOSED $__________
REGISTRATION Print this page for mail or fax Click this tab to register online
2015 SOI-3DI-SUBTHRESHOLD
MICROELECTRONICS TECHNOLOGY
UNIFIED CONFERENCE
OCTOBER 5-8, 2015 • DOUBLETREE BY HILTON HOTEL • ROHNERT PARK, CALIFORNIA
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NADINE COLLAERTimec
Nadine Collaert re-ceived the MS and PhD degrees in elec-trical engineering from the ESAT Department, Catholic University Leuven, Leuven, Bel-gium, in 1995 and
2000, respectively, where her PhD thesis was related to the modeling and characterization of a new transistor concept, the vertical Si/SiGe hetero-junction MOSFET.
Since then, she has been involved in the theory, design, and technology of FinFET-based multigate devices, emerg-ing memory devices, and transducers for biomedical applications and the integration and characterization of bio-compatible materials e.g. carbon-based materials. Since February 2012 she is working as program manager of the imec LOGIC program, focusing on high mobility channels, TFET and nanowires.
She has authored or coauthored more than 200 papers in international journals and conference proceedings. She has been a member of the CDT committee of the IEDM conference and she is still a member of the Pro-gram Committees of the international conferences ESSDERC and ULIS/EU-ROSOI.
TSU-JAE KING LIUUniversity of California, Berkeley
Tsu-Jae King Liu re-ceived the BS, MS, and PhD degrees in Electrical Engineering from Stanford Uni-versity. From 1992 to 1996 she was a Member of Research
Staff at the Xerox Palo Alto Research Center (Palo Alto, CA). In August 1996 she joined the faculty of the Universi-ty of California, Berkeley, where she is currently the TSMC Distinguished Pro-fessor in Microelectronics, and Chair of the Department of Electrical Engineer-ing and Computer Sciences.
Dr. Liu’s research awards include the DARPA Significant Technical Achieve-ment Award (2000) for development of the FinFET, the IEEE Kiyo Tomiya-su Award (2010) for contributions to nanoscale MOS transistors, memory devices, and MEMs devices, the Intel Outstanding Researcher in Nanotech-nology Award (2012), and the Semi-conductor Industry Association Out-standing Research Award (2014). She has authored or co-authored close to 500 publications and holds over 90 US patents, and is a Fellow of the IEEE. Her research activities are presently in ad-vanced materials, process technology and devices for energy-efficient elec-tronics.
GARY PATTONGLOBALFOUNDRIES
Dr. Gary Patton joined G L O B A L F O U N D -RIES’ Senior Leader-ship Team in July 2015 as the Chief Technolo-gy Officer and head of worldwide Research and Development. He
is responsible for GLOBALFOUNDRIES’ semiconductor technology R&D road-map, operations, and execution.
Prior to joining GLOBALFOUNDRIES, Dr. Patton was the Vice President of IBM’s Semiconductor Research and De-velopment Center – a position that he held for eight years. During that time, he was responsible for IBM’s semiconductor R&D roadmap, operations, execution, and technology development alliances, with primary locations in East Fishkill, New York, Burlington, Vermont, Albany Nanotech Research Center in Albany, New York, and Bangalore, India. He was also a member of the select IBM Corpo-rate Growth & Transformation Team.
Dr. Patton is a well-recognized indus-try leader in semiconductor technology R&D with over 30 years of semiconduc-tor experience. During his career at IBM, he has held a broad set of executive and management positions in IBM’s Micro-electronics, Storage Technology, and Re-search Divisions, including positions in technology and product development, manufacturing, and business line man-agement.
PLENARY SPEAKERS
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Dr. Patton received his BS degree in electrical engineering from UCLA and his MS and PhD degrees in electrical engineering from Stanford University. He is a Fellow of the IEEE and a member of the IEEE Nishizawa Medal Awards Committee. He has co-authored over 70 technical papers and given numer-ous invited keynote and panel talks at major industry forums on technology and industry issues.
HANS STORKON Semiconductor
Dr. Hans Stork is Se-nior Vice President and Chief Technolo-gy Officer (CTO) at ON Semiconductor. He oversees the de-velopment of wafer process technolo-
gies, modeling and design kits, intel-lectual property (IP) libraries, as well as packaging technologies and assembly support.
Prior to joining ON Semiconductor, Dr. Stork was Group Vice President and CTO of the Silicon Systems Group at Applied Materials. From 2001 to
2007 he was Senior Vice President and the CTO of Texas Instruments. Be-fore that, Dr. Stork was various R&D and management positions at Hewlett Packard Laboratories and at IBM’s T.J. Watson Research Center.
Dr. Stork serves on the supervisory board of ASML, is a member of the Scientific Advisory board at IMEC, and has previously served on the boards of Sematech and the SRC. He is also a longstanding member of the SIA Tech-nology Strategy Committee.
He authored more than 100 cited pa-pers and holds eleven US patents. He was elected IEEE Fellow in 1994, and served on several IEEE sponsored con-ference program committees. He currently chairs the IEEE A. Grove Tech-nical Field Award committee and is vice-chair of the Technical Field Awards council.
Dr. Stork was born in Soest, The Netherlands, and received the Inge-nieur degree in electrical engineering (EE) from Delft University of Technolo-gy, Delft, The Netherlands, and holds a PhD in EE from Stanford University.
GEOFFREY YEAPQualcomm
Dr. Geoffrey Yeap is a Vice President of Engineering at Qual-comm Technologies Inc. in charge of sil-icon technology & foundry engineering and foundry IP/de-
sign enablement. He has more than 20 years of semiconductor experience working at Qualcomm, Motorola and Advanced Micro Devices on micropro-cessor and mobile SoC silicon technol-ogy development and manufacturing, as well as design/technology co-opti-mization.He earned his PhD in Electrical and Computer engineering specializing in microelectronics from the University of Texas at Austin. He holds more than 30 patents and has published more than 70 refereed journal and conference papers.
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Patton, cont’d.
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MIKE ALLESFundamentals Class InstructorVanderbilt University
Michael L. Alles received BSEE, MSEE, and PhD degrees from Vanderbilt Uni-versity. He spent one year with Harris Semiconductor as a design engineer, ten years with Ibis Technology Corpo-ration in product development and program management, and two years as a Business Unit Director for Silva-co International. He joined Vanderbilt University’s Institute for Space and De-fense Electronics (ISDE) in 2003, and is currently a Research Professor in the Electrical Engineering Department and the Program Manager for Commercial Systems with ISDE, where he works in the area of radiation effects in micro-electronics.
Dr. Alles has a strong background in semiconductor technology, including manufacturing and metrology, comput-er-aided design tools for semiconduc-tor fabrication processes, devices, and integrated circuit design, and expertise in modeling and simulation of radia-tion effects in semiconductor devices and circuits. He has served on the SIA ITRS starting materials working group, serving as chairman of the SOI mate-rials group for the 2001 revision, and has been a reviewer for Transactions on Nuclear Science several times. He cur-rently serves on the IEEE International SOI Conference technical committee. Mike is the author or co-author of ap-proximately 100 technical/trade publi-cations and co-inventor on two patents.
Dr. Alles’ present research focus is in the application of advanced and emerging semiconductor technologies in radiation environments.
TONY AMORTShort Course InstructorBoeing Corporation
Tony Amort has been working in the Boeing Solid State Electronics Develop-ment organization for 15 years. During that time he has principally worked on development of radiation hardened mi-croelectronics. Since 2006 he has been the senior project engineer responsible for the development of radiation hard-ened by design (RHBD) technology, for semiconductor processes from the 0.25 µm node down to 14 nm.
FRANCK ARNAUDHot Topics SpeakerSTMicroelectronics
Franck Arnaud joined STMicroelec-tronics in 1995 after his graduation for a Master degree in the field of Electron-ics from the Superior School of Electric-ity (Sup’Elec Paris).
He started the ramp-up of 0.35um CMOS technology as FEOL and device engineer.
In 2008, he spent two and half years in Fishkill area working in ISDA semi-con-ductor alliance led by IBM as 32/28nm device manager. He then moved back to Crolles site in France in 2010 where he took the responsibility of the 28nm program development for both bulk and FDSOI technologies as director.
SYLVAIN BARRAUDInvited SpeakerCEA-LETI
Sylvain Barraud received the PhD de-gree from the Paris-Sud University, Or-say, France, in 2001. From 1998 to 2001, he worked at Institut d’Electronique Fondamentale (IEF), Orsay, France, on modeling and simulation of electron transport in field-effect transistors using Monte-Carlo method.
He joined the French Atomic Energy Commission Laboratory (CEA-LETI), Grenoble, as a research staff member in 2001. From 2001 to 2009, he was engaged in the physics and modeling of transport in advanced MOSFET de-vices. Since 2010, his research activity is focused on innovative device integra-tion. He has been involved in several in-dustrial, European and national projects.
His current research interests include the device physics, the fabrication and characterization of nanowire-based devices including tri-gate, omega-gate, stacked-gate-all-around nanowire MOS-FETs and single electron nanodevices. He has authored or co-authored about 120 papers published in international journals and conferences.
DAVID BOLHot Topics SpeakerUCL, Belgium
David Bol received the PhD degree in Engineering Science from UCL in 2008 in the field of ultra-low power digital nanoelectronics. In 2005, he was a vis-iting PhD student at the CNM, Sevilla,
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Spain, and in 2009, a postdoctoral re-searcher at intoPIX, Louvain-la-Neuve, Belgium. In 2010, he was a visiting post-doc researcher at the UC Berkeley Lab for Manufacturing and Sustainability, Berkeley, CA. In 2015, he participated to the creation of e-peas semiconduc-tors, Liège, Belgium.
Prof. Bol is currently leading with Prof. Denis Flandre the Electronic Circuits and Systems (ECS) research group focused on ultra-low-power cir-cuits and systems, technology/circuit interaction, mixed-signal SoC design, variability mitigation, compact model-ing, design automation, nano-CMOS technologies and green semiconduc-tor manufacturing. He has authored more than 70 papers and conference contributions and holds three patents. He (co-)received three Best Paper/Poster/Design Awards in IEEE confer-ences (ICCD 2008, SOI Conf. 2008, FTFC 2014). He serves as a reviewer for various IEEE journals/conferences and presented several keynotes in interna-tional conferences.
JOACHIM BURGHARTZInvited Speaker Institute for Microelectronics Stuttgart (IMS Chips)
Joachim N. Burghartz was born in Aachen, Germany, in 1956. He re-ceived the MS (Dipl. Ing.) degree from the RWTH Aachen, Germany, in 1982 and the PhD (Dr.-Ing.) degree from the University of Stuttgart, Germany, in 1987, both in electrical engineering.
Between 1982 and 1987 he was a member of the research team on sen-
sors with integrated signal conversion, particularly magnetic field sensors, at Universität Stuttgart.
From 1987 until 1998 he worked at the IBM Thomas J. Watson lab in York-town Heights, NY, on selective silicon epitaxial, Si and SiGe high-speed tran-sistor designs and integration process-ing as well as in CMOS technology. Fol-lowing this, he expanded his research into the development of passive com-ponents, especially integrated high-per-formance silicon coils.
From 1998 until 2005, he was Full Professor at TU Delft and headed the High-Frequency Technology and Com-ponents (HiTeC) research team. He concentrated his research on Silicon HF technology with a focus spanning from work on materials to design on circuit components.
In addition, from March 2001 until August 2005, he served as Scientific Director at TU Delft´s Institute of Mi-croelectronics and Submicron Technol-ogy (DIMES).
Since October 2005, Prof. Dr. Burghartz has been Director and Chair-man of the Board at Instituts für Mikro-elektronik Stuttgart (IMS) as well as be-ing Full Professor at Universität Stuttgart.
He has also been heading the Insti-tut für Nano- und Mikroelektronische Systeme (INES) at Universität Stuttgart since March 1, 2006.
August 18, 2013, marked his launch as Manager of the IMS Mikro-Nano Produkte GmbH.
In recognition of his academic achievements he has been awarded prizes, such as the IEEE Electron Devic-es Society´s J. J. Ebers Award 2014, the
Landesforschungspreis Baden-Würt-temberg 2009 and the ISSCC Jack Rap-er Award 2008. He is an IEEE Fellow and was Vice President of the IEEE Elec-tron Devices Society between 2009 and 2013 as well as having been As-sociate Editor of the IEEE Transactions on Electron Devices between 2001 and 2006. He was a Member of the Executive and Technical Committees at the BCTM (General Chairman 2000), IEDM, ESSDERC, ISICDG, VLSI-TSA, DCIS and SBMICRO symposia. His list of publications include 91 papers (peer review) in journals, 244 publications for symposia, three books, four book chapters and 16 patents (patent fami-lies). A particular highlight is the tech-nical book he edited commemorating the 60/35th anniversary of the IEEE Electron Devices Society “Guide to State-of-the-Art Electron Devices” (Wi-ley&Sons Publishers) which was award-ed the 2013 PROSE Award as best tech-nical book of the year in engineering & technology.
PAUL CHANGShort Course InstructorIBM
Paul Chang received his BS, MS and PhD degrees in Electrical Engineering from UC-Berkeley, studying organic thin film transistors during his grad-uate studies. He joined IBM’s Semi-conductor Research & Development Center in 2005, working in logic device path-finding and ultimately focusing on FET variability in IBM’s 65nm and 45nm HP SOI technologies. In 2008 he joined the 22nm HP SOI technology
Bol, cont’d.
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as lead device engineer, working from technology definition and path-finding all the way through to the manufactur-ing ramp for IBM’s POWER8 and Z13 Mainframe microprocessors.
CHRISTOPHE CHEVALLIERInvited SpeakerRump Session PanelistAmbiq Micro
Christophe Chevallier is director of memory design at Ambiq Micro, a start-up using near Vt design to pro-duce ultra low power microcontrollers.He developed high density non volatile memory solutions with Rambus and Uni-ty Semiconductor, which he co-found-ed. He designed one of the world’s first low voltage NOR Flash at Catalyst Semi-conductor, and later help start Micron Technology’s Flash business.
Mr. Chevallier holds over 200 pat-ents. He graduated from Ecole Cen-trale de Marseille, France, and has an MS in Electrical Engineering from Stan-ford University
FABIEN CLERMIDYInvited SpeakerCEA-LETI
Fabien Clermidy obtained his master’s degree in 1994, his PhD in Engineering Science from INPG, Grenoble in 1999 and his supervisor degree from INPG in 2011.
Fabien is currently director of the dig-ital design laboratory at CEA-LETI work-ing on multi-core architectures and design with a focus on emerging tech-nologies. In this position, he managed the team demonstrating the best per-forming low-voltage DSP developed in
FDSOI technology and demonstrated at ISSCC in 2014. The team is also im-plied in the development of new archi-tectures using emerging technologies such as 3D TSV, 3D monolithic integra-tion (CoolCube LETI’s technology) and emerging memories such as RRAM.
Fabien has published two books, more than 70 journal and conferences papers and is author or co-author of 15 patents.
SORIN CRISTOLOVEANUInvited SpeakerCNRS
Sorin Cristoloveanu received the PhD (1976) in Electronics and the French Doctorat ès-Sciences in Physics (1981) from Grenoble Polytechnic Institute, France. He is currently Director of Re-search CNRS. He also worked at JPL (Pasadena), Motorola (Phoenix), and the Universities of Maryland, Florida, Vanderbilt, Western Australia, and Kyungpook (World Class University project). He served as the director of the LPCS Laboratory and the Center for Advanced Projects in Microelectronics, initial seed of Minatec center. He au-thored more than 1,000 technical jour-nal papers and communications at in-ternational conferences (including 160 invited contributions). He is the author or the editor of 28 books, and he has or-ganized 25 international conferences. His expertise is in the area of the elec-trical characterization and modeling of semiconductor materials and devices, with special interest for silicon-on-in-sulator structures. He has supervised more than 80 PhD completions. With his students, he has received 13 Best
Paper Awards, an Academy of Science Award (1995), and the Electronics Divi-sion Award of the Electrochemical Soci-ety (2002). He is a Fellow of IEEE, a Fel-low of the Electrochemical Society, and Editor of Solid-State Electronics.
HARMKE DE GROOTHot Topics Speakerimec and Holst Centre
Harmke de Groot is Senior Director at imec and Holst Centre for Perceptive Systems. These heterogeneous con-nected systems use their own sensors as well as information from the cloud to build a view of the world surround-ing them and in such a way realize a natural and intuitive experience for the end-user. Her team is internationally rec-ognized for their work in the field of sen-sor networks, high speed networks and sensors. Imec contributes to the ‘Inter-net of Things’ revolution by developing innovative algorithms, network, radio, dsp and sensor solutions for person cen-tric, infrastructure centric and vehicle centric Perceptive Systems, realizing that the traditional borders between these applications domains are quickly fading. Together with a wide range of in-dustrial and academic partners this R&D program addresses the challenges of limited autonomy, functionality, interop-erability, ease of use, data fusion and security to enable a wide range of new applications and a truly intuitive user ex-perience.
Before joining imec in 2008 she was group program manager at the Europe-an Microsoft Innovation Center (EMIC) in Aachen, Germany, an applied re-search center. She started her industrial
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career at Philips (now NXP) in the area of communication systems and other net-worked embedded devices. De Groot is (co-)author of more than 60 publica-tions and a book on embedded system design. Harmke De Groot received a Master of Science in Electrical and Elec-tronics Engineering from the University of Technology Eindhoven in 1997 and an Master of Business Administration from TIAS Business school in 2013.
YANG DUInvited SpeakerShort Course Instructor Qualcomm
Dr. Yang Du is currently with Qual-comm Research where he leads a team in advanced semiconductor research. His research interests include emerging semiconductor technology and devices, predictive device and circuit modeling, novel VLSI circuit design and architec-ture, next generation 3D-IC. His recent research focus is on emerging 3D-VLSI circuit, architecture and system integra-tion, design automation, advanced ther-mal modeling and thermal aware design methodologies.
Yang received his PhD from Columbia University in 1994. Since then, he held various engineering positions in Analog Devices, Motorola and Qualcomm. He is the author/coauthor of over 50 pat-ents/patent publications and numerous conference/journal papers in VLSI tech-nology, SPICE modeling, IC design and design automation. He has served in the technical program committee of Sub-threshold Microelectronics Conference since 2011 and in the Advisory Commit-tee of IEEE S3S Conference since 2013.
OLIVIER FAYNOTShort Course InstructorCEA-LETI
Olivier Faynot received the MSc and PhD degrees from the Institut Nation-al Polytechnique de Grenoble, France in 1991 and 1995, respectively. His doctoral research was related to the characterization and modeling of deep submicron Fully Depleted SOI devices fabricated on ultrathin SIMOX wafers.
He joined LETI (CEA-Grenoble, France) in 1995, working on simulation and modeling of deep submicron fully and partially depleted SOI devices. His main activity was the development of a dedicated Partially Depleted SOI SPICE model, called LETISOI. From 2000 to 2002, he was involved in the develop-ment of a sub 0.1µm partially depleted technology. From 2003 to 2007, he was leading the development of ad-vanced single and multiple-gate Fully Depleted SOI technologies with High K and Metal gate. From 2008 to 2010, he managed the innovative devices lab-oratory at LETI, focused on advanced CMOS device integration. Since 2011, he is responsible of the Microelectron-ic component division at LETI, dealing with CMOS technologies, advanced Memories and 3D integration for com-puting.
He is author and co-author of more than 300 scientific publications in jour-nals and international conferences. Since 2001, Dr. Faynot was successive-ly in the committees of the main inter-national conferences like International Electron Device Meeting (IEDM), the symposium on VLSI Technology, the IEEE International SOI conference, the
EUROSOI network, the Solid State De-vice and Materials (SSDM) conference and the International S3S conference.
PHILIP FENGShort Course InstructorCase School of Engineering, Case Western Reserve University
Philip Feng does research on nanoscale devices and systems in EECS at Case School of Engineering, Case Western Reserve University. Prior to joining Case, Dr. Feng was at the Kavli Nano-science Institute, California Institute of Technology (Caltech), where he served as a Staff Scientist and a Co-Principal Investigator from 2007 to 2010. He re-ceived his Ph.D. from Caltech in 2007 for developing ultra high frequency (UHF) nano-electro-mechanical sys-tems (NEMS) with low-noise technolo-gies for real-time single-molecule sens-ing. His recent awards include an NSF CAREER Award, 3 Best Paper Awards (with his advisees, at IEEE NEMS 2013, IEEE Int. Freq. Control Symp. 2014, and AVS Int. Symp. 2014) out of 7 nominat-ed Best Paper Finalists, a Glennan Fel-lowship, and an Innovative Incentive Award. Feng was one of the 81 young engineers selected to participate in the National Academy of Engineering (NAE)’s 2013 U.S. Frontier of Engineer-ing (USFOE) Symposium. Subsequent-ly, he received the NAE’s Grainger Foundation Frontiers of Engineering Award in 2014. He also received the Case School of Engineering Graduate Teaching Award (2014), and the Case School of Engineering Research Award (2015). He has over 80 peer-reviewed papers and 5 issued patents; and his pa-
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pers have over 2500 citations in recent years. He is a Senior Member of IEEE, a member of AVS, APS, and MRS
PHILIPPE FLATRESSEFundamentals Class InstructorDesign Architect, STMicroelectronics
Philippe Flatresse received MS degree in Electrical Engineering in 1995 and PhD degree in Microelectronics in 1999 from Grenoble institute of technology.
In 2000, he joined STMicroelectron-ics Central R&D to deploy the SOI dig-ital design within the company. He has developed the first SOI standard cells and SRAM libraries as well as IOs in-cluding innovative ESD solutions. He has also invented several dedicated CAD tools and low power digital design techniques such as power switches. Thanks to this work, he has pioneered the SOI technology and demonstrated its key advantages for low power high performance digital applications. As a design architect, his current research activities are the exploration, develop-ment and implementation of ultra-low power platforms able to work in an energy-efficient way on an ultra-wide range of operating points targeting high-growth application areas. His main objective is to explore the energy ef-ficiency limits of parallel computing on multi-cores systems for ultra-low power processing by combining UTBB FD-SOI technology, advanced power management techniques, hardware ac-celerators and software infrastructure. His current role in ST is in the specifica-tion of the appropriate design solutions and technology variants for CMOS products in the following applications
area: multimedia processors, consum-er products, servers & routers, gaming, low power microcontrollers.
His expertise covers bulk and SOI technologies, high performance ener-gy efficient designs, design of libraries and IPs and silicon qualification. He has authored or co-authored more than 50 technical papers, and has filed more than ten patents in advanced CMOS technologies.
PAUL FRANZONShort Course InstructorNCSU
Paul D. Franzon is currently a distin-guished professor of electrical and computer engineering at North Caroli-na State University. He earned his PhD from the University of Adelaide, Ade-laide, Australia. He has also worked at AT&T Bell Laboratories, DSTO Austra-lia, Australia Telecom and three com-panies he co-founded, Communica, LightSpin Technologies and Polymer Braille Inc. His current interests center on the technology and design of com-plex microsystems incorporating VLSI, MEMS, advanced packaging and na-no-electronics. He has led several ma-jor efforts and published over 300 pa-pers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a distinguished alum-ni professor, received the Alcoa Re-search Award in 2005, and the Board of Governors Teaching Award in 2014. He served with the Australian Army Re-serve for 13 years as an infantry soldier and officer. He is a Fellow of the IEEE.
FRED GIANESELLOShort Course InstructorSTMicroelectronics
Fred Gianesello received the BS and MS degree in electronics engineering from Institut National Polytechnique de Grenoble (Grenoble, France) in 2003 and the PhD degrees in electrical engineering from the Joseph Fourier University (Grenoble, France) in 2006.
Dr Gianesello has authored and co-authored more than 125 refereed journal and conference technical ar-ticles. He has served on the TPC for the International SOI Conference from 2009 up to 2011 and he is currently serving as reviewer for several confer-ences or journals.
Dr Gianesello is currently work-ing for STMicroelecetronics in Crolles (France) as RF Technical leader where he leads the team responsible for the development of electromagnetic de-vices (inductor, balun, transmission line, antenna) integrated on advanced RF CMOS/BiCMOS/SOI (down to 14 nm), Silicon Photonics and advanced packaging technologies (3D Integra-tion, FOWLP).
JIN-WOO HANInvited SpeakerCenter for Nanotechnology
Dr. Jin-Woo Han is a Research Scientist in the Center for Nanotechnology at NASA Ames Research Center in Mof-fett Field, CA. He received his PhD in Electrical Engineering from KAIST in South Korea. His research interests in-clude development of novel electronic devices and sensors. He has received many awards for his work including IEEE
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Electron Device Society Early Career Award, NASA Ames Honor Award, and Outstanding Engineering Achievement Award from the Engineers Council.
TERRY HOOKShort Course InstructorFundamentals Class InstructorIBM
Terence Hook has been with IBM since 1980, after receiving his ScB from Brown University. He earned his PhD in EE from Yale University in 1986, pursu-ing various aspects of tunneling and in-terface characteristics in silicon dioxide systems under the tutelage of Prof. T-P. Ma. While at IBM he has worked on technology integration and device de-sign for bipolar, BiCMOS, and CMOS technologies from two micrometer to down to the leading-edge current envi-ronment in the 5nm range. In addition to transistor architecture, some of his particular special interests have includ-ed process-induced charging and tran-sistor variability. He has authored many conference and journal papers and book chapters and holds some 60 or so patents. He is currently a Senior Tech-nical Staff Member in IBM Research at Albany Nanotech in Albany, New York, although he continues to make his home in Vermont.
KOICHIRO ISHIBASHIShort Course InstructorUniversity of Electro-Communications, Tokyo
Koichiro Ishibashi has been a professor at the University of Electro-Communi-cations, Tokyo, Japan since 2011. He has served as guest professor at Ho Chi
Minh City University of Science and Ho Chi Minh City University of Technology since 2012.
He received PhD degree from To-kyo Institute of Technology in 1985. He joined Central Research Laborato-ry, Hitachi Ltd. in 1985, where he had investigated low power technologies for Super H microprocessors, called SH3, SH4, and SH5 as well as high density 256kbit, 1Mbit and 4Mbit SRAMs. From 2001 to 2004, he led the low power design development department in STARC (Semiconductor Technology Academic Research Cen-ter), where low power technologies of logic, memory, and analog circuits for SOC were investigated. From 2004 to 2011, he was in Renesas Electronics where he developed low power IPs mainly for mobile phone SOCs as a de-partment manager
He has presented more than 190 academic papers at international con-ferences including ISSCC, IEDM invited papers, and J. of Solid State Circuits. He was awarded R&D 100 for the develop-ment of SH4 Series Microprocessor in 1999, and The Takeda Techno-Entre-preneurship Award 2001 for the re-search on Low Power Circuit Technol-ogy of Micro-controllers.
His current interests are design technology of low power LSI, and IoT applications using the low power LSIs. They include low power design tech-nology using SOTB devices, MEMS devices for RF applications, and energy harvesting sensor networks.
He is a member of IEICE and a Fel-low of IEEE.
SUBRAMANIAN IYERInvited SpeakerHenry Samueli School of Engineering and Applied Science, University ofCalifornia at Los Angeles
Subramanian S. Iyer (Subu) is Distin-guished Chancellor’s Professor in the Electrical Engineering Department at the University of California at Los An-geles. He obtained his BTech from IIT-Bombay, and PhD from UCLA and joined the IBM T.J. Watson Research Center at Yorktown Heights, NY and later moved to the IBM Systems and Technology Group at Hopewell Junc-tion, NY where he was appointed IBM Fellow and was until recently Director of the Systems Scaling Technology De-partment.
His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, elec-trical Fuses, embedded DRAM and 45nm technology used at IBM and IBM’s development partners. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. He has published over 250 papers and holds over 70 patents.
His current technical interests and work lie in the area of advanced pack-aging and 3-dimensional integration for system-level scaling, as well as the long-term semiconductor and packaging roadmap for logic, memory and other devices as well as counterfeit preven-tion. He has received several outstand-ing technical achievements and corpo-rate awards at IBM and was elected a member of the IBM Academy of Tech-nology as well as a Master Inventor.
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He is an IEEE Fellow and a Distin-guished Lecturer of the IEEE EDS as well as a member of its Board of Gover-nors. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Dan-iel Noble Medal for emerging technol-ogies in 2012. He also studies Sanskrit in his spare time.
SAMADI KAMBIZShort Course InstructorQualcomm
CHRISTOPHE MALEVILLEInvited SpeakerDigital Electronics BU, SoitecChristophe Maleville has been Senior Vice President of Soitec’s Digital BU since 2010. He joined Soitec in 1993 and was a driving force behind the company’s joint research activities with CEA-Leti. For several years, he led new SOI process development, oversaw SOI technology transfer from R&D to production, and managed customer certifications. He also served as Vice President, SOI Products Platform at Soitec, working closely with key cus-tomers worldwide. He has authored or co-authored more than 30 papers and also holds some 30 patents. He has a PhD in microelectronics from the Greno-ble Institute of Technology and obtained an Executive MBA from INSEAD.
MATT MARINELLAShort Course InstructorSandia Labs
Matthew J. Marinella is a Principal Member of the Technical Staff at San-dia National Laboratories in Albuquer-que, NM, where he leads a device re-
search program in resistive memories (ReRAM) for advanced computing and radiation hardened applications. He also is involved with research in GaN and SiC high power electronic devices. Prior to Sandia, Dr. Marinella worked as a CMOS Device Technology Develop-ment Engineer at Microchip Technolo-gy in Tempe, AZ. His research interests include emerging memory and logic devices, novel architectures employ-ing these devices, nanotechnology, and wide-bandgap power devices. He is also Chair of Emerging Memory De-vices for the International Technology Roadmap for Semiconductors (ITRS).
Dr. Marinella has authored or co-au-thored over three dozen journal and conference publications, two book chapters, one book, chaired and or-ganized conferences sessions, and has given invited talks in the areas of emerging memory devices and archi-tectures and advanced power devices. He received his PhD in Electrical Engi-neering from Arizona State University under Prof. Dieter Schroder.
THOMAS G. MCKAYInvited SpeakerGLOBALFOUNDRIES
Tom McKay is an IC designer, architect and technologist with over 25 years’ experience in wireless design and inno-vation. In 1999, Tom co-founded Zee-vo and led RF development on the first single-chip 2.4 GHz 180 nm CMOS Bluetooth RF SoC, shipping in volume to tier 1 customers; Zeevo was ac-quired by Broadcom in 2005. As Prin-cipal Engineer with RF Micro Devices (now Qorvo), Tom invented compact,
frequency agile RF filters with Q’s over 200, demonstrated in 90 nm CMOS in 2007. He also drove RFSOI devel-opment from a design perspective for cellular front-ends, now widely utilized in smart phone antenna switches and tuners. In 2009 Tom joined MStar (now part of MediaTek), where he patented and developed multi-mode, multi-band cellular CMOS receiver techniques. Tom has held positions of Senior Man-ager at Samsung Semiconductor, Staff Scientist at WJ Communications and Sr. Principal Engineer at MStar. As RF Inno-vation Manager at GLOBALFOUND-RIES, Tom now leads RF path-finding ef-forts focused on the synergy between circuit design and GLOBALFOUND-RIES process technologies to address new market needs through early-phase hardware demonstrators.
Tom holds an MSEE from the Univer-sity of Wisconsin-Madison, is a Senior Member of the IEEE and inventor on 13 US patents.
PASCAL MEINERZHAGENFundamentals Class InstructorIntel Corporation
Pascal Meinerzhagen is a senior research scientist at Intel Labs, Intel Corporation, Hillsboro, OR, USA, and a visiting lec-turer at the Bar-Ilan University in Israel. In 2014, he was a post-doctoral fellow and a lecturer at the Bar-Ilan Universi-ty, Ramat-Gan, Israel, where he estab-lished the Advanced Digital VLSI Design course. He received the PhD, MSc, and BSc degrees, all in electrical engineer-ing, from EPFL, Lausanne, Switzerland, in 2014, 2008, and 2006, respectively. He also received a joint MSc degree in
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micro- and nanotechnologies for inte-grated systems from Grenoble INP, Po-litecnico di Torino, and EPFL, in 2008.
His current research interests are broad, ranging from energy-efficient and error-resilient circuits and systems in high-performance FinFET CMOS tech-nologies, to power delivery and power management techniques, to convention-al and emerging memory circuits, to ul-tra-low power VLSI.
He has authored/co-authored two in-vited book chapters, 27 peer-reviewed journal articles and international con-ference papers, and holds four pending patents. Dr. Meinerzhagen is a reviewer for 16 international journals and confer-ences, including IEEE TCAS-I & II, IEEE JETCAS, and the IEEE Symposia on VLSI Technology and Circuits. He has re-ceived an Intel PhD fellowship and two best paper nominations.
SUBHASISH MITRAInvited SpeakerStanford University
Professor Subhasish Mitra directs the Robust Systems Group in the Depart-ment of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineer-ing. Before joining Stanford, he was a Principal Engineer at Intel.
Prof. Mitra’s research interests in-clude robust systems, VLSI design, CAD, validation and test, emerging nanotechnologies, and emerging neu-roscience applications. His X-Compact technique for test compression has been key to cost-effective manufac-turing and high-quality testing of a vast
majority of electronic systems, includ-ing numerous Intel products. X-Com-pact and its derivatives have been im-plemented in widely-used commercial Electronic Design Automation tools. His work on carbon nanotube imper-fection-immune digital VLSI, jointly with his students and collaborators, re-sulted in the demonstration of the first carbon nanotube computer, and it was featured on the cover of NATURE. The NSF presented this work as a Research Highlight to the US Congress, and it also was highlighted as “an important, scientific breakthrough” by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Pub-lic Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide.
Prof. Mitra’s honors include the Pres-idential Early Career Award for Sci-entists and Engineers from the White House, the highest US honor for ear-ly-career outstanding scientists and engineers, ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automa-tion, “a test of time honor” for an out-standing technical contribution, and the Intel Achievement Award, Intel’s highest corporate honor. He and his students published several award-win-ning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Con-ference, IEEE International Test Confer-ence, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology.
Prof. Mitra has served on numerous conference committees and journal ed-itorial boards. He served on DARPA’s Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.
MASANORI NATSUIInvited SpeakerInstitute of Electrical Communication, Tohoku University
Masanori Natsui (M’02) received BE de-gree in Electronic Engineering, and the MS and PhD degrees in Information Sci-ences from Tohoku University, Japan, in 2000, 2002 and 2005, respectively. He is currently an Associate Professor of the Research Institute of Electrical Com-munication, Tohoku University.
His research interest includes auto-mated circuit design technique, non-volatile-based circuit architecture and its application, design of high speed low-power integrated circuits based on multiple-valued current-mode circuit technology, and brain-like optimization algorithms and its hardware implemen-tation. He received the IEEE Sendai Section Student Award in 2003, the Excellent Paper Award of IEICE, Japan, in 2010, and Kenneth C. Smith Early Career Award for Microelectronics Re-search in 2012.
ALI NIKNEJADRump Session PanelistUniversity of California, Berkeley
Ali M. Niknejad received the BSEE de-gree from the University of California, Los Angeles, in 1994, and his Master’s and PhD degrees in electrical engineer-ing from the University of California,
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Berkeley, in 1997 and 2000. He is cur-rently a professor in the EECS depart-ment at UC Berkeley and faculty direc-tor of the Berkeley Wireless Research Center (BWRC) and the BSIM Research Group. Prof.
Niknejad is the recipient of the 2012 ASEE Frederick Emmons Terman Award for his textbook on electromagnetics and RF integrated circuits. He is also the co-recipient of the 2013 Jack Kilby Award for Outstanding Student Paper for his work on an efficient Quadra-ture Digital Spatial Modulator at 60 GHz and the 2010 Jack Kilby Award for Outstanding Student Paper for his work on a 90 GHz pulser with 30 GHz of bandwidth for medical imaging, and the co-recipient of the Outstanding Technology Directions Paper at ISSCC 2004 for co-developing a modeling ap-proach for devices up to 65 GHz. He is a co-founder of HMicro and
inventor of the REACH™ technology, which has the potential to deliver ro-bust wireless solutions to the health-care industry. His research interests lie within the area of wireless and broad-band communications and biomedical imaging. His focus areas of his research include analog, RF, mixed-signal, mm-wave circuits, device physics and com-pact modeling, and numerical tech-niques in electromagnetics.
ZVI OR-BACHShort Course InstructorMonolithIC 3D
Zvi Or-Bach is the founder of Mono-lithIC 3D™Inc., Top Embedded Inno-vator-Silicon by Embedded Computing Design Magazine and finalist of the
“Best of Semicon West 2011” for its monolithic 3D-IC breakthrough. Or-Bach was also a finalist of the EE Times Innovator of the Year Award in 2011 and 2012 for his pioneering work on the monolithic 3D-IC. Or-Bach has exten-sive management experience including being CEO for over 20 years, being in charge of R&D, sales, marketing, busi-ness development and other corporate functions. Or-Bach has been an active board member for over 20 years and is now Chairman of the Board for Zeno Semiconductors and VisuMenu. Or-Bach has a history of innovative devel-opment in fast-turn ASICs for over 20 years. His vision led to the invention of the first Structured ASIC architecture, the first single via programmable array, and the first laser-based system for one-day Gate Array customization. In 2005, Or-Bach won the EETimes Innovator of the Year Award and was selected by EE Times to be part of the “Disruptors – The people, products and technologies that are changing the way we live, work and play.” Prior to MonolithIC 3D, Or-Bach founded eASIC in 1999 and served as the company’s CEO for six years. eASIC was funded by leading in-vestors Vinod Khosla and KPCB in three successive rounds. Under Or-Bach’s leadership, eASIC won the prestigious EETimes’ 2005 ACE Award for Ultimate Product of the year in the Logic and Programmable Logic category. Earlier, Or-Bach founded Chip Express in 1989 (recently acquired by Gigoptix) and served as the company’s president and CEO for almost 10 years, bringing the company to $40M revenue, and to in-dustry recognition for four consecutive
years as a high-tech Fast 50 Company that served over 1000 ASIC designs, in-cluding many one-day prototypes and one-week production delivery. Zvi Or-Bach received his BSc degree (1975) cum laude in electrical engineering from the Technion – Israel Institute of Technology, and MSc (1979) with dis-tinction in computer science, from the Weizmann Institute, Israel. He holds over 150 issued patents, primarily in the field of 3D integrated circuits and semi-custom chip architectures.
THIERRY POIROUXFundamentals Class InstructorCEA-Leti
Thierry Poiroux received the MS degree from Ecole Centrale Paris, France, in 1995 and the PhD degree from the Uni-versity of Nantes, France, in 2000. His PhD work was carried out at the Com-missariat à l’Énergie Atomique/Labora-toire d’Electronique et de Technologie de l’Information (CEA-Leti), Grenoble, France, and Matra MHS on plasma process-induced damage. In April 2000, he joined CEA-Leti as a Research Staff Member. Until 2002, he was in-volved in partially and fully depleted silicon-on-insulator (SOI) process inte-gration and compact modeling. From 2002 to 2007, he worked on advanced device architectures and was in charge of multiple-gate device modeling and planar double gate process integration. In 2007, he started an activity on device integration on graphene, a promising material for the beyond complemen-tary metal-oxide-semiconductor era. In 2011 and 2012, he has been the Head of the Innovative Device Laboratory of
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CEA-Leti. Since 2012, he is working on the development of the second version of Leti-UTSOI compact model, dedicat-ed to fully-depleted SOI technology. He has authored or coauthored five book chapters and more than 120 papers and communications in the fields of plasma process-induced damage, SOI and multiple-gate device physics, fabri-cation, characterization, and modeling. He is author or co-author of about 20 patents on novel devices, process inte-gration and modeling methodology.
CHETAN PRASADInvited SpeakerIntel Corporation
Chetan Prasad received his PhD in Elec-trical Engineering from Arizona State University in 2003. Since then, he has been a part of Intel’s Logic Technology Development Quality and Reliability team as a senior staff engineer working on transistor reliability R&D across In-tel’s 90nm to 14nm technologies. He currently manages all aspects of quali-ty and reliability for Intel’s 14nm SOC node. He has authored, co-authored and presented over 50 papers in peer-reviewed journals and conference proceedings, and has one awarded and some pending US patents.
MARIAM SADAKAShort Course InstructorSoitec
Mariam Sadaka has been a Soitec Fel-low since 2008, working on identifica-tion and development of next genera-tion technologies and applications for Soitec’s roadmap. In her current role, she is focused on Fully-Depleted SOI
(FDSOI) for 28/22/14nm nodes and be-yond. While at Soitec, Mariam worked on several emerging technologies in-cluding 3D integration and wide band gap Gallium Nitride technology. Previ-ously, Mariam was the director of ad-vanced R&D at Coldwatt, where she led the semiconductor power switch and nanomagnetic material development for high frequency and high efficiency power converters. From 1997 to 2005, Mariam was a senior principal staff engi-neer at Motorola/Freescale, where she developed next generation strained (Si/SiGe) and hybrid orientation SOI devic-es for the advanced CMOS roadmap, and III-V devices (HBT) for wireless ap-plications leading to product adoption in Motorola and BlackBerry phones.
Mariam received a BS in Chemistry from the American University of Beirut, an MS and Ph.D. in Chemical Engineer-ing from Arizona State University, and an MBA from the University of Texas in Austin. She holds more than 70 patents, and has authored/co-authored over 50 journal articles and conference pro-ceedings including invited talks. Mari-am serves on the board of directors of CS MANTECH, and is a member of the technical program committees for IEEE sponsored IEDM and ICICDT.
SAYEEF SALAHUDDINInvited SpeakerUniversity of California, Berkeley
Sayeef Salahuddin is an associate profes-sor of Electrical Engineering and Comput-er Sciences at the University of California, Berkeley. His group works on the design, fabrication and physics of emerging de-vices for energy efficient computing.
Salahuddin has championed the concept of ‘interacting systems’ for switching de-vices, showing fundamental advantage of such devices in terms of power dissi-pation. Negative Capacitance FET is one example of such a device.
Salahuddin received many awards in-cluding a Hellman Faculty Fellowship in 2010, the NSF CAREER award in 2011, the IEEE Nanotechnology Early Career Award in 2012, an AFOSR Young Inves-tigator Award in 2013, an ARO Young In-vestigator Award in 2013 and best paper awards from IEEE Transactions on VLSI Systems in 2013 and from the VLSI-TSA conference in 2013. He chairs the Nan-otechnology Committee of the Electron Devices Society. He also serves in the editorial board of IEEE Journal of Explor-atory Computational Devices and Cir-cuits (JXCDC) and IEEE Electron Devices Letters (EDL).
JOSEPH SHORFundamentals Class InstructorBar Ilan University
Dr. Shor received his PhD in Electrical En-gineering from Columbia University, 1993. BA in Physics, Queens College, 1986.
Joseph Shor is an Associate Profes-sor of Electrical Enginering at Bar Ilan University. Shor has published more than 50 papers in refereed Journals and Conference Proceedings in the areas of Analog Circuit Design and Device Physics. Holds 35 issued patents and several pending patents. From 2004-2015, he was a Principal Engineer at Intel, and head of the Analog Team at Intel Yakum. Between 1999-2004, he worked at Saifun Semiconductor as a Staff Engineer where he established the
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analog activities for Flash and EEPROM NROM memories. From 1994-1999, he was a Senior Analog Designer at Motorola Semiconductor in the DSP Division. From 1988-1994, he was a Se-nior Research Scientist at Kulite Semi-conductor, where he developed pro-cesses and devices for Silicon Carbide and Diamond Microsensors.
His research interests include analog circuits, Switching and Linear Voltage Regulators, thermal Sensors, PLLs and IO circuits, as well as novel sensor ma-terials. He is presently a member of the ISSCC Technical Program committee, and a frequent referee for JSSC, TCAS and other Journals, and is a senior member of the IEEE.
STANLEY S. C. SONGRump Session PanelistQualcomm Technologies, Inc.
Stanley S. C. Song received the BS de-gree from Incheon National University, Incheon, Korea, and the MS and PhD degrees in solid-state electronics from the University of Texas at Austin, Aus-tin, TX, USA. He has served in various technical and management roles in many major semiconductor companies for the last 15 years, such as Motorola, Samsung, and Texas Instruments. He is currently involved in n+1 and n+2 tech-nology pathfinding at Qualcomm, San Diego, CA, USA, where he is focusing on process module and device and circuit interaction. He has authored/co-authored over 50 journal and con-ference papers, and holds over 10 US patents.
NORIKATSU TAKAURARump Session PanelistHitachi
Norikatsu Takaura received BS and in 1991 MS in Materials Science and Engi-neering (MSE) from Waseda University. He received PhD in MSE in 1997 from Stanford University. Dr. Takaura joined Central Research Laboratory (CRL) of Hitachi Ltd. in the same year. He has engaged in research of semiconductor devices, DRAM, and non-volatile resis-tive switching devices. He has been a re-search leader of Phase Change Memory since 2002. Since 2010, He has been a group leader of Phase Change Device re-search at Japan national projects held by Ministry of Economy, Trade and Industry (METI) and New Energy and Industrial Technology Development Organization (NEDO). He was a subcommittee chair-man of memory technology of 2009 IEDM, and a member of the executive committee of 2010-12 IEDM.
THOMAS UHRMANNInvited SpeakerEV Group (EVG)
Dr. Thomas Uhrmann is director of busi-ness development at EV Group (EVG) where he is responsible for overseeing all aspects of EVG’s worldwide business development. Specifically, he is focused on 3D integration, MEMS, LEDs and a number of emerging markets.
Prior to this role, Uhrmann was busi-ness development manager for 3D and Advanced Packaging as well as Com-pound Semiconductors and Si-based Power Devices at EV Group. He holds an engineering degree in mechatronics from the University of Applied Sciences
in Regensburg and a PhD in semicon-ductor physics from Vienna University of Technology.
CHRIS VAN HOOFInvited SpeakerProgram Director Wearable Healthcare, imec
Chris Van Hoof is Director of the Body Area Networks activities at imec in Leu-ven, Belgium, and in Eindhoven, The Netherlands, and Program Director of Wearable Healthcare (HUMAN++). He also became imec Fellow in 2013.
Chris Van Hoof has a track record of 20+ years of initiating, executing and leading national and international con-tract R&D with worldwide customers. His imec research has led to three imec startups and he also delivered space qualified flight hardware to two corner-stone European Space Agency (ESA) missions. He has worked on wearable sensors for the past 10 years taking this activity from embryonic research to a business line with leading worldwide customers in the medical and consum-er space.
After obtaining a PhD in Electrical Engineering (University of Leuven, 1992), Chris Van Hoof has held posi-tions at imec as manager and director in diverse technical fields: sensors and imagers, MEMS and autonomous mi-crosystems, implantable packaging, flexible technology, wireless sensors, body-area networks.
Chris Van Hoof is also full professor at the University of Leuven (KU Leuven).
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STEVEN VITALEInvited SpeakerMIT Lincoln Laboratory
Steven Vitale is Senior Technical Staff in the Chemical, Microsystem, and Nanoscale Technologies Group at MIT Lincoln Laboratory. He received his BS in chemical engineering from Johns Hopkins University and his PhD in chemical engineering from MIT. He has been researching semiconductor device fabrication and process integra-tion for 14 years.
At MIT Lincoln Laboratory, Steven’s current research includes development of a fully-depleted silicon-on insulator (FDSOI) ultra-low-power microelec-tronics technology for energy starved systems such as space-based systems, wearable computing, and biomedical devices. He is also studying novel elec-tronic devices based on diamond and 2D transition metal dichalcogenides. Prior to joining Lincoln Laboratory, Ste-ven worked at Texas Instruments devel-oping advanced gate etch processes for the 90nm through 45nm nodes, including research into transistor per-formance improvements through re-duced source/drain silicon loss and
reduced gate line edge roughness. He has published 25 refereed journal arti-cles and holds seven patents related to semiconductor processing.
In 2011 and 2012 Steven was the gen-eral chair of the IEEE Subthreshold Mi-croelectronics Conference. He is cur-rently Secretary of the Plasma Science and Technology Division of the AVS.
PIET WESSELSInvited SpeakerEmbedded High Voltage and Power Processes, NXP
Piet Wessels joined Philips is 1987. In 1991 he led the development of a 700V embedded BCD technology. In 1995 he was process integration manager at a discrete semiconductor factory. In 2004 he led a process integration and process development department at a 5 inch, 600K wafer factory. In 2006 he be-came director of process development for high voltage and power technolo-gies within NXP, where his team has to develop technologies for factories inter-nal, but also external NXP. One of the re-cent developments is ABCD9: the first C13 embedded 100V technology in the world. Piet also leads NXP New tech-
nology team in the area of high voltage and power. In this platform all research and development groups, factories and business development groups within NXP, which work in the HV domain: sit together to define NXP HVP technolo-gy roadmap; initiate new development programs; execute benchmark studies; define R&D roadmaps, etc.
CHI-CHAO YANGInvited SpeakerNational Nano Device Laboratories (NDL)
Dr. Chih-Chao Yang received his PhDin 2007 from the National Tsing Hua Uni-versity in Taiwan. He is an associate re-searcher in emerging device division, Na-tional Nano Device Laboratories (NDL).
His research interests now include the development of monolithic 3D integrated circuit and device for internet of things. He is now utilizing low thermal budge pulse la-ser processes, including laser crystallization, laser activation and laser silicide, for fabri-cating high performance and sequentially stacked logics and memories. Such 3D se-quential integration (3DSI) technology is the key to realize high performance, rich func-tion, power efficient and low cost 3DIC.
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