2015-4-13 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection

23/4/21

Based on text by S. Mourad "Priciples of Electronic Systems"

Digital Testing: Design Representation and Fault Detection

http://www.talikom.com.my/tester4.jpg

Copyright(c)2001, Samiha Mourad 2

Outline Design Representation Models Switching functions Sensitized Path Boolean Difference Fault Detection and Redundancy Finite State Machines Tabular Representation Binary Decision Diagrams


Design Paradigm The design representation space consists of domains and levels

Behavioral domain most abstract

Structural domain specifies the architecture

Physical domain include the transistors and layout

BehavioralDomain

StructuralDomain

PhysicalDomain

RTL Level

Logic Level

Circuit Level

System Level

A

P


Domains and LevelsTable 3.1 Domains and Level of Design

D o m a i n

Behavioral Structural Physical

System System Specifications Blocks Chip

RTL RTL Specifications Registers Macro Cells

Logic Boolean Functions Logic Gates Standard Cells

L

E

V

E

L

S

Circuit Differential Equations Transistors Masks


Domains

a = b+cz = !(a·d)

BehavioralDomain

StructuralDomain

PhysicalDomain

b

c

da z

b c d


Levels

Register Level

System Level Gate Level

Z

A

B D

C

AH

Q1

Q8

EN

B

Register

A H

Q1

Q8

EN

B

Reg

iste

r

Reg. BReg. A

Adder

Clk

Circuit Level

c

b

d

a z


SPICE Modeling

RD

RS

D

G

S

CGBO

CGSO

VDS

VGD

CBD

CBS

VBSVGS

CGDO

VBD

ID

B

BQ BC

C

E

Q BE

V BC

V BE

rc

rb

re

IC

IE

(a) (b)

Z(x) - logic function of circuit N

x - input vector t - a specific input (test) vectorNf - a faulty circuit (N changes as a result of fault f)

Fault detection and redundancyDefinition: A test vector t detects a fault t iff Zf (t) Z(t)

0

1OR

1

x1

x2

x3

0

1

Z1

Z2

Example :OR bridging fault between x1 and x2Consider test t = 011

Fault detection and redundancy

Example : Z1 = x1 x2, Z1f = x1 + x2 Z2 = x2 x3 Z2f = (x1 +x2) x3Z (011) = 01, Zf (011) = 11 => t = 011 detects f

The set of all tests that detect f is given byZ(x) Zf(x) =1


0

1OR

1

x1

x2

x3

0

1

Z1

Z2

X100101XX

Stuck-at-0 fault

1/0

Fault activation

Path sensitization

Primary inputs(PI)

Primary outputs(PO)

Combinational circuit

1/0

Fault effect

1= x1= y

wf

c/0

x y

0 = wf

c/0

Example: Test for c/0 is w, x, y = 0,1,1

· Activate Fault c/0· Set x = y = 1 to make c = 1 in Fault-free Circuit

· Propagate Value on c to f· Set w = 0 to sensitize c to f

SPECIFIC-FAULT ORIENTED TEST SET GENERATION

Fault detection and redundancya set of inputs which detect all possible (detectable) faults is called a complete detection test setan input b = (b1… bn) distinguishes a fault from another fault if Z Z or

Z Z= 1

a set of tests which distinguish all pairs of fault is called a complete location test set

Example :Consider fault = x2 sa1 and = x3 sa0 • find Z1 , Z & Z

• check if (101) detects Z

• check if (101) distinguishes Z & Z

Z

x1

x2

x3


Z = [(x1 x2)’(x2 x3)’]’ = x1 x2 +x2 x3 = x2 (x1 + x3)= x2 sa1 and = x3 sa0 Z Z | (1,0,1) = Z (x1+x3)=0 1 =1Z Z | (1,0,1) = Z (x1x2)= 1 0 =1We see that the same vector x=(1,0,1) distinguishes these two faults

Example :


If only f out of x faults have been detected bya test then “test coverage ” is tc = f/x 1

One-dimensional path sensitization

A line whose value changes in the presence of the fault is sensitized to the fault by the test t.A path composed of sensitized lines is called a sensitized path.


x2 0

x3 0

x1 1

x4 1

ZG5

0/1

G3

G4

0/1

0

G2 0/1

G1

0

Example:consider G2 sa1


Fault detection and redundancy Path sensitization algorithmI. specify inputs to generate at the site of the fault

II. propagate error to the outputIII. specify inputs to obtain signal values needed in II

IC circuit modification from:http://www.wintech-nano.com/services_ic

c iAND 0 0OR 1 0NAND 0 1NOR 1 1

c x x c ix c x c ix x c c ic’ c’ c’ c’ i

Truth tables• requires 2n entriesInput Scanning is simpler• gates described by

Element evaluation

- c -- controlling value- i -- inversion

all inputs of G sensitized to f have the same value (say a)all not sensitized inputs have value c’the output of Gate is equal a i

Lemma:Gate with c, i - controlling and inversion values


c iAND 0 0OR 1 0NAND 0 1NOR 1 1

c x x c ix c x c ix x c c ic’ c’ c’ c’ i

The rules for error propagation with sensitized inputs equal to a


c i Gate Other inputs Output0 0 AND all must be 1 a0 1 NAND all must be 1 a’1 0 OR all must be 0 a1 1 NOR all must be 0 a’

Example :Diagnosesa0 fault at G2

G8=D

x1=0x3=0

x2=0x3=0

x2=0x4=0

x2=0

G4=0

G5=D’

G6=0

G7=0x3=0

x4=1

G1=1

x1=0

G2=1 D

G3=1

sa0


Conflicting requirements

Example :Diagnosesa0 fault at G2

G8=D

x1=0x3=0

x2=0x3=0

x2=0x4=0

x2=0

G4=0

G5=D’

G6=D’

G7=0x3=0

x4=0

G1=1

x1=0

G2=1 D

G3=1

sa0


Detectabilityif no test can detect fault f => f is undetectablesuch a circuit is redundantundetectable fault can prevent detection of another fault

DetectabilityExample : b sa0 is detected by t =1101

a = 0

A=1

C=0

B=1

b=1/0

0 1

0/1

0/11/0

1D=10

DetectabilityExample : b sa0 is no longer detected by t =1101 if

a sa1 is present

a=0/1

b=1/0

0/1 1/0

0

0/11/0

1D=10

A=1

C=0

B=1

Detectability

Undetectable fault simplification ruleAND (NAND) input sa1 remove inputAND (NAND) input sa0 remove gate, replace by 0(1)OR (NOR) input sa0 remove inputOR (NOR) input sa1 remove gate, replace by 1(0)

Redundant circuit can always be simplified by removing a gate or gate input

Rules

DetectabilityTriple modular redundancy (TMR) is used in faulttolerant design. TMR is untestable, off line testing possible for individual modules only

A

MA

A

F= ab + a’c = 1u1

Redundancy may be used to avoid hazardsExample : Consider : b=c=1, a changes from 1 to 0

a=1u0b=111

c=111Y

X=1u0

Z=0u1

redundant

Detectability


Boolean Algebra

Boolean function F(x) maps domain B n to B, where B = {1,0} and F: B n B.

For any element c B, the constant function is f(xi)= c, where xi B n

For any xi B n, the projection function is f(xi)= xi

The set of variables {x1, x2, xn} is called the cube or support of the function

A Boolean function can be expressed in different forms, for instancef x x x x x x x x( , , ) ' ,1 2 3 1 2 2 1 2

Boolean difference

Definition : The Boolean difference of f(x) is equal D(f) = df(x)/dx = f(x) f(x’)An equivalent definition results from the following Shannon’s law f(x) = x f(1) + x’ f(0)

Lemma: f(x) f(x’) = f(0) f(1)Then the Boolean difference isf x x x f x x xi n i n( , , , , ) ( , , , , )1 10 1 1

Boolean differenceBoolean difference of a product is simple

df(x1x2…xn)/dx1=0 x2…xn= x2…xn

And a Boolean difference of a sum is

df(x1+x2+…+xn)/dx1= (x2+…+xn)1=

= (x2+…+xn)’=x’2…x’n

Boolean difference

x sa0 will be tested by input vectors that satisfy :

T0 = x (df/dx) =1

x sa1 will be tested by T1 = x’(df/dx) =1

Theorem:Boolean difference can be used to obtain all tests for stuck-at faults


Fault Detection Consider an example function

f (x) = g (x) +x3, where g(x) = x1x2 ,

Thus df (x)/dx2 = x3 (x1 + x3) = x3’x1 = 1.

then x1 = 1 and x3 = 0.

For the SA1 and SA0 faults on x2, the test patterns are then x1x2x3 = (100) and (110), respectively.

x1x2 g

x3f


Fault Detection:

Repeat calculations for stuck-at faults on x3. df (x)/dx3 = g (x) 1 = x1 x2 1 = (x1 x2)'.

Test patterns to detect all the faults x3/0 and x3/1 are T0=x3 (x1 x2)' = 1 and T1=x3’ (x1 x2)' = 1. for x3/0, we must have x3x'1 +x3x'2 = 1, this results in three test patterns: x1x2x3 = (001, 011, or 101) and for x3/1, we have x1x2x3 = (000, 010, or 100)

x1x2 g

x3f

Boolean difference

G5 f

x2

x3

x1

x4

G1

G2

G3

G4

Example :Find set of tests for x1 sa1 in the circuit

Boolean difference

Example :T1 = x1’(df/dx1) = x1’{f(0) f(1)} = x1’ [x4 (x2 + x3)] = x1’(x4x2’x3’ + x4’x2 + x4’x3)

x=0001 is a solution which sensitize the path x1G2G4G5

G5 f

x2

x3

x1

x4

G1

G2

G3

G4

Boolean difference

1 0 1

2 0 1

3

4

5

6

f x xf xf

f x xf xf

A A B AB

A AB AB

AC AB A C B

A B A C A B C

( ) ( ) ( )

( ) ( ) ( )

( )

( )

( ) ( ) ( )

Transistor level circuit modification on 90nm process fromhttp://www.wintech-nano.com/services_ic

Boolean difference

fx1

x2

Example : find the Boolean difference of f w.r.t. x2

Boolean difference

Example : f x x x x x

df

dxf f x x

T xdf

dx

T xdf

dx

( )

( ) ( )

1 2 1 2

21 1

0 22

1 22

0 1 0

0

0

Not testable

Boolean difference

Theorem :The set of all tests which detect h sa0 is defined by :

T h xdf x h

dh

T h xdf x h

dh

0

1

( )( , )

( )( , )

And h sa1 is defined by :

To Propagate Fault, Set x = 1, y or z =0' 'c v w

For c/1, must set c = 0,So v = w = 1

Test for c/1v w x y z1 1 1 0 11 1 1 1 01 1 1 0 0

TEST PATTERN GENERATION – BOOLEAN DIFFERENCE

av

wx

yz

c

d

e

g

h

jf

1

b

' ' '( )( ) ( ) ( )

df d cx yzyz x yz x y z x y z

dc dc

x(yz)’

Boolean difference

Example :Find all h sa0 tests

f

x1

x2

x3

x4

h

Boolean difference

Example :Find all h sa0 tests

f h x x x x

where h x x

T hdf

dhh f h f h

h x x x x

hx x x x

x x x x x x

x x x x

3 4 2 4

1 2

0

3 4 2 4

3 4 2 4

1 2 3 4 2 4

1 2 3 4

0 1

1

[ ( ) ( )]

[( ) ]

( )( )

f

x1

x2

x3

x4

h

Boolean difference

Example : Find G1 sa1 tests

G5 f

x2

x3

x1

x4

G1

G2

G3

G4

Boolean difference

Example : Find G1 sa1 tests

G5 f

x2

x3

x1

x4

G1

G2

G3

G4

f G x x x G x x

T Gdf

dGG f f G x x x x x

x x x x x x x x x x x x x

1 1 1 4 1 2 3

1 11

1 1 1 4 1 1 4

2 3 1 4 1 2 3 1 4 1 1 2 3

0 1

,

[ ( ) ( )] [( ( )]

( )

Boolean differenceBoolean difference can be formed by concatenating Boolean differences (Simple chain rule)

dZ

dx

dZ

dy

dy

dx

In the previous example we have

f G G G G x G x x

df

dG

df

dG

dG

dG

d G G

dGx

G x x x x x x x x

:

, ,

( )

( )

3 4 3 1 1 4 1 4

1 3

3

1

3 4

31

4 1 1 4 1 1 4 1 1

Boolean differenceLemma : (Hong Dai)

f x x f x x

x x f f

x x f f

x x f f

x x f f

( ) ( )

[ ( ) ( )]

[ ( ) ( )]

[ ( ) ( )]

[ ( ) ( )]

1 2 1 2

1 2

1 2

1 2

1 2

00 11

10 01

01 10

00 11

Boolean differenceTest for multiple faults

for x sa x sa

T x x f x x f x x

x x f f

these results can be extended to more than faults

x x x sa

T x x x f x x x f x x x

x x x f f

n

n n n

n

1 2

0 0 1 2 1 2 1 2

1 2

1 2

0 0 1 2 1 2 1 2

1 2

0 0

11 00

2

0

11 1 00 0

&

( ( ) ( ))

( ( ) ( ))

( ( ) ( ))

( ( ) ( ))

Boolean differenceTest for multiple faults

for x sa x sa

T x x f x x f x x

x x f f

for x sa x sa

T f f

x xd f

dx xx x

df

dxx x

df

dx

1 2

01 1 2 1 2 1 2

1 2

1 2

0 0

1 2

2

1 21 2

11 2

2

0 1

10 01

0 0

00

&

( ( ) ( ))

( ( ) ( ))

( )


Finite State MachineA finite state machine is formally expressed as a 6-tuplet (I, S, , S0, O, ), where

I is the finite non-empty set of inputs S is the finite and non-empty set of states :S x I S is the next state function S0 S is the set of initial states O is the set of outputs : S x I O is the output function for a Mealy

machine, : S O is the output function for a Moore machine.


Graphical & Tabular Representation

Table 3.3 State Table for FSM M

I PS NS Out0 A C 11 A B 0

Present Next State 0 B C 0State I=0 I=1 1 B B 1A C,1 B,0 0 C D 1B C,0 B,1 1 C C 1C D,1 C,1 0 D A 1D A,1 C,0 1 D C 0

Q

QSET

CLR

DCombinationalCircuit

I

Z

z

Clk

Graphical Representation (FSM)


Binary Decision Diagram

( a )

x1x2

x1

x2

1 0

1

1

0

0

x1 + x2

x1

x2

1 0

1

1

0

0

( b )

f = f =


Binary Decision Diagram

x2x4 + x2 'x3

x3

x1

x2

1

1

0

0

x4x3

x3

x11 0

01

1

1

1

0

0

001

x1

x2

x3

x4

f

g

(a)

(c)

(b)

f =x1 x2 x4 + x1`x3+ x2`x3

Wikipedia 56

Binary Decision DiagramBinary decision tree and truth table for the function f(x1, x2, x3) = x1’ x2 ‘x3’ + x1 x2 + x2 x3

BDD for the function f


Test Generation with BDDf=g+x3=x1 x2 + x3

To get the Boolean difference for x1 we need to find paths to x1 =1 and x1 =0 from1 and 0 function values using the same internal signals (no fork at any node)so df/d x1 =x2x3’

The same procedure for internal signal g

df/dg=x3’

g 1

1

0

0

01

x1

x2

x3

f

0

1

(b)

1

1

0

0

01

x1

x2

x3

f

0

1

(a)


01

1

1

1

0

0

001

x1

x2

x3

x4

f

Test Generation with BDD

For Boolean functionf =x1 x2 x4 + x1‘x3+ x2‘x3

Boolean difference to test for x1

s_a faults is df/d x1 = x2x4x3’ + x2x4’x3


Conclusion Design Representation Models used in Fault

Simulation Path Sensitization to Detect a Fault Boolean Difference Complete Detection and Location Sets Finite State Machines Binary Decision Diagrams

Documents

2015-4-13 Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection