IEEE Catalog Number: ISBN:

CFP12162-PRT 978-1-4577-2145-8

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)

Dresden, Germany 12-16 March 2012

Pages 1-804

1/2

Table of Contents

Design, Automation and Test in Europe Conference and Exhibition - DATE 2012 DATE 12 SponsorsDATE Executive CommitteeDATE Sponsor CommitteeTechnical Program Topic Chairs Technical Program CommitteeReviewersForeword ......................................................................................................................Best Paper AwardsTutorialsPH.D. ForumCall for Papers: DATE 2013 KEYNOTE ADDRESSES The Mobile Society - Chances and Challenges for Micro- and Power Electronics ..................................... 1

K Meder, President, Automotive Electronics Division, Bosch, DE New Foundry Models - Accelerations in Transformations of the Semiconductor Industry ......................... 2

M Chian, Senior Vice President Design Enablement, GlobalFoundries, DE 2.2 Validation of Modern Microprocessors Moderators: D Grosse, Bremen U, DE; V Bertacco, U of Michigan, US Automated Generation of Directed Tests for Transition Coverage in Cache Coherence Protocols............ 3

X Qin and P Mishra On ESL Verification of Memory Consistency for System-on-Chip Multiprocessing..................................... 9

E A Rambo, O P Henschel and L C V dos Santos Generating Instruction Streams Using Abstract CSP ................................................................................ 15

Y Katz, M Rimon and A Ziv A Cycle-Approximate, Mixed-ISA Simulator for the KAHRISMA Architecture........................................... 21

T Stripf, R Koenig and J Becker A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems........... 27

J Gao, J Wang, Y Han, L Zhang and X Li 2.3 Memory System Optimization Moderators: T Austin, EECS, U of Michigan, US; C Silvano, Politecnico di Milano, IT CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory................................. 33

K Chen, S Li, N Muralimanohar, J H Ahn, J B.Brockman and N P.Jouppi TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access ......................................... 39

S Stipic, S Tomic, F Zyulkyarov, A Cristal, O Unsal and M Valero Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design .................... 45

Y-T Chen, J Cong, H Huang, B Liu, C Liu, M Potkonjak and G Reinman DRAM Selection and Configuration for Real-Time Mobile Systems.......................................................... 51

M D Gomony, C Weis, B Akesson, N Wehn and K Goossens

2.4 Architectures and Efficient Designs for Automotive and Energy-Management Systems Moderators: C Sebeke, Bosch, DE; G Merrett, Southampton U, UK Using Timing Analysis for the Design of Future Switched Based Ethernet Automotive Networks............ 57

J Rox, R Ernst and P Giusto Fair Energy Resource Allocation by Minority Game Algorithm for Smart Buildings ................................. 63

C Zhang, W Wu, H Huang and H Yu On Demand Dependent Deactivation of Automotive ECUs....................................................................... 69

C Schmutzler, M Simons and J Becker Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks......... 75

M Magno, S Marinkovic, D Brunelli, E Popovici, B O’Flynn and L Benini 2.5 Physical Design for Low-Power Moderators: J Teich, Erlangen-Nuremberg U, DE; W Fornaciari, Politecnico di Milano, IT IR-Drop Analysis of Graphene-Based Power Distribution Networks ......................................................... 81

S Miryala, A Calimera, E Macii and M Poncino Off-path Leakage Power Aware Routing for SRAM-based FPGAs ........................................................... 87

K Huang, Y Hu, X Li, B Liu, H Liu and J Gong Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization................ 93

A Makosiej, O Thomas, A Vladimerescu and A Amara Post-Synthesis Leakage Power Minimization ............................................................................................ 99

M Rahman and C Sechen 2.6 Optimized Utilization of Embedded Platforms Moderators: F Slomka, Ulm U, DE; O Bringmann, FZI Karlsruhe, DE Fast and Lightweight Support for Nested Parallelism on Cluster-Based Embedded Many-Cores.......... 105

A Marongiu, P Burgio and L Benini A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms.... 111

I Anagnostopoulos, A Bartzas, G Kathareios and D Soudris Dual Greedy: Adaptive Garbage Collection for Page-Mapping Solid-State Disks................................... 117

W-H Lin and L-P Chang 2.7 SPECIAL SESSION - HOT TOPIC - EDA Solutions to New-Defect Detection in Advanced Process Technologies Moderator: E J Marinissen, IMEC, BE EDA Solutions to New-Defect Detection in Advanced Process Technologies ........................................ 123

E J Marinissen, G Vandling, S K Goel, F Hapke, J Rivers, N Mittermaier, S Bahl 2.8 Beyond CMOS - Benchmarking for Future Technologies Moderators: C M Sotomayor Torres, Barcelona U, ES; W Rosenstiel, edacentrum and Tuebingen U, DE Beyond CMOS – Benchmarking for Future Technologies....................................................................... 129

C M Sotomayor Torres, J Ahopelto, M W M Graef, R M Popp, W Rosenstiel

3.2 Effective Functional Simulation and Validation Moderators: P P Sanchez, Cantabria U, ES; F Fummi, Verona U, IT Accurately Timed Transaction Level Models for Virtual Prototyping at High Abstraction Level .............. 135

K Lu, D Mueller-Gritschneder and U Schlichtmann Out-of-Order Parallel Simulation for ESL Design..................................................................................... 141

W Chen, X Han and R Doemer A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis ........................... 147

H-Y Lin, C-Y Wang, S-C Chang, Y-C Chen, H-M Chou, C-Y Huang, Y-C Yang and C-C Shen

Approximating Checkers for Simulation Acceleration.............................................................................. 153

B Mammo, D Chatterjee, D Pidan, A Nahir, A Ziv, R Morad and V Bertacco 3.3 Industrial Design Methodologies Moderators: A Jerraya, CEA, FR; R Zafalon, STMicroelectronics, IT Guidelines for Model Based Systems Engineering ................................................................................. 159

D Steinbach SURF Algorithm in FPGA: A Novel Architecture for High Demanding Industrial Applications ................ 161

N Battezzati, S Colazzo, M Maffione and L Senepa NOCEVE: Network On Chip Emulation and Verification Environment .................................................... 163

O Hammami, X Li and J-M Brault Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks .................................................................................................................................................. 165

A Sassone, A Calimera, A Macii, E Macii, M Poncino, R Goldman, V Melikyan, E Babayan and S Rinaudo

Challenges in Verifying an Integrated 3D Design .................................................................................... 167

T G Yip, C Y Hung and V Iyengar 3.4 Large-Scale Energy and Thermal Management Moderators: G Palermo, Politecnico di Milano, IT; M Poncino, Politecnico di Torino, IT Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems.................................................................................................................................................... 169

Y Wang, Q Xie, M Pedram, Y Kim, N Chang and M Poncino Benefits of Green Energy and Proportionality in High Speed Wide Area Networks Connecting Data Centers ............................................................................................................................................ 175

B Aksanli, T S Rosing and I Monga Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer ....................................................................................................................................... 181

A Bartolini, M Sadri, J-N Furst, A K Coskun and L Benini Neighbor-Aware Dynamic Thermal Management for Multi-core Platform ............................................... 187

G Liu, M Fan and G Quan 3.5 PANEL - Key Challenges for Next Generation Computing .......................................................... 193 Moderator: R Riemenschneider, European Commission, BE

3.6 Model-Based Design and Verification for Embedded Systems Moderators: W Yi, Uppsala U, SE; S Ben Salem, Verimag Laboratory, FR Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration.................. 194

Y Yang, M Geilen, T Basten, S Stuijk and H Corporaal Verifying Timing Synchronization Constraints in Distributed Embedded Architectures........................... 200

A C Rajeev, S Mohalik and S Ramesh Task Implementation of Synchronous Finite State Machines.................................................................. 206

M Di Natale and H Zeng Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design ................................................................................................................................ 212

G Di Guglielmo, L Di Guglielmo, F Fummi and G Pravadelli 3.7 Improving Reliability and Yield in Advanced Technologies Moderators: S Nassif, IBM, US; S Khursheed, Southampton U, UK NBTI Mitigation by Optimized NOP Assignment and Insertion................................................................ 218

F Firouzi, S Kiamehr and M B Tahoori An Accurate Single Event Effect Digital Design Flow for Reliable System Level Design........................ 224

J Pontes, N Calazans and P Vivet Cross Entropy Minimization for Efficient Estimation of SRAM Failure Rate ............................................ 230

M A Shahid 3.8 HOT TOPIC - Design Automation Tools for Engineering Biological Systems Moderator: J Madsen, DTU, DK Experimentally Driven Verification of Synthetic Biological Circuits.......................................................... 236

B Yordanov, E Appleton, R Ganguly, E A Gol, S B Carr, S Bhatia, T Haddock, C Belta, D Densmore

Genetic/Bio Design Automation for (Re-)Engineering Biological Systems.............................................. 242

S Hassoun IP1 Interactive Presentations Fast Cycle Estimation Methodology for Instruction-Level Emulator ........................................................ 248

D Thach, Y Tamiya, S Kuwamura and A Ike Verification Coverage of Embedded Multicore Applications ................................................................... 252

E Deniz, A Sen and J Holt Hazard Driven Test Generation for SMT Processors ............................................................................. 256

P Singh, V Narayanan and D L Landis Extending the Lifetime of NAND Flash Memory by Salvaging Bad Blocks.............................................. 260

C Wang and W-F Wong A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem................. 264

S Kwon, D Kim, Y Kim, S Yoo and S Lee A High-Performance Dense Block Matching Solution for Automotive 6D-Vision .................................... 268

H Sahlbach, S Whitty and R Ernst Optimization Intensive Energy Harvesting ............................................................................................... 272

M Rofouei, M A Ghodrat, M Potkonjak and A Martinez Nova Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach.................................... 276

P Milbredt, M Glass, M Lukasiewycz, A Steininger and J Teich Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems.................................................................................................................................. 280

S Werner, O Dey, D Goehringer, M Huebner and J Becker VaMV: Variability-aware Memory Virtualization ....................................................................................... 284

L A D Bathen, N D Dutt, A Nicolau and P Gupta Hybrid Simulation for Extensible Processor Cores .................................................................................. 288

J Jovic, S Yakoushkin, L Murillo, J Eusse, R Leupers and G Ascheid Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug...................................... 292

Z Poulos, Y-S Yang, J Anderson, A Veneris and B Le MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution.................................................................................................................................... 296

M Becker, G B G Defo, F Fummi, W Mueller, G Pravadelli and S Vinco Runtime Power Gating in Caches of GPUs for Leakage Energy Savings............................................... 300

Y Wang, S Roy and N Ranganathan Automatic Generation of Functional Models for Embedded Processor Extensions ................................ 304

F Sun An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models...................................................................................................................................................... 308 P Peranandam, S Raviram, M Satpathy, A Yeolekar, A Gadkari and S Ramesh Model Driven Resource Usage Simulation for Critical Embedded Systems ........................................... 312

M Lafaye, L Pautet, E Borde, M Gatti and D Faura RAG: An Efficient Reliability Analysis of Logic Circuits on Graphics Processing Units........................... 316

M Li and M S Hsiao 4.2 Routing Solutions for Upcoming NoC Challenges Moderators: J Flich, UP Valencia, ES; M Palesi, Kore U, IT CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks........................ 320

M Ebrahimi, M Daneshtalab, P Liljeberg, J Plosila and H Tenhunen An MILP-Based Aging-Aware Routing Algorithm for NoCs ..................................................................... 326

K Bhardwaj, K Chakraborty and S Roy AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs........................................... 332

S Akbari, A Shafiee, M Fathy and R Berangi 4.3 Industrial Embedded System Design Moderators: F Clermidy, CEA-LETI, FR; T Simunic Rosing, UC San Diego, US Middleware Services for Network Interoperability in Smart Energy Efficient Buildings ........................... 338

E Patti, A Acquaviva, F Abate, A Osello, A Cucuccio, M Jahn, M Jentsch and E Macii

Low-power Embedded System for Real-Time Correction of Fish-Eye Automotive Cameras ................. 340

M Turturici, S Saponara, L Fanucci and E Franchi Mechatronic System for Energy Efficiency in Bus Transport................................................................... 342

M Donno, A Ferrari, A Scarpelli, P Perlo and A Bocca Intelligent and Collaborative Embedded Computing in Automation Engineering .................................... 344

M A Al Faruque and A Canedo 4.4 System-Level Power and Reliability Estimation and Optimization Moderators: A K Coskun, Boston U, US; J-J Chen, Karlsruhe Institute of Technology, DE Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis ....... 346

Y Xu, B Li, R Hasholzner, B Rohfleisch, C Haubelt and J Teich Runtime Power Estimator Calibration for High-Performance Microprocessors....................................... 352

H Wang, S X-D Tan, X-X Liu and A Gupta Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards ............................................................................................................................................. 358

N Druml, C Steger, R Weiss, A Genser and J Haid Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization ............................ 364

H Mahmood, M Poncino, M Loghi and E Macii 4.5 EMBEDDED TUTORIAL - State-of-the-Art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems Moderators: A Legay, INRIA/Rennes, FR State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems.................................................................................................................................................... 370

M Bozga, A David, A Hartmanns, H Hermanns, K G Larsen, A Legay and J Tretmans 4.6 Compilers and Source-Level Simulation Moderators: R Rabbah, IBM Research, US; B Franke, Edinburgh U, UK Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models .................................... 376

S Stattelmann, G Gebhard, C Cullmann, O Bringmann and W Rosenstiel Accurate Source-Level Simulation of Embedded Software with Respect to Compiler Optimizations............................................................................................................................................ 382

Z Wang and J Henkel Scheduling for Register File Energy Minimization in Explicit Datapath Architectures ............................. 388

D She, Y He, B Mesman and H Corporaal Multi-Objective Aware Extraction of Task-Level Parallelism Using Genetic Algorithms.......................... 394

D Cordes and P Marwedel 4.7 Advances in Test Generation Moderators: G Mrugalski, Mentor Graphics, PL; S Hellebrand, Paderborn U, DE RTL Analysis and Modifications for Improving At-speed Test ................................................................. 400

K-H Chang, H-Z Chou and I L Markov Test Generation for Clock-Domain Crossing Faults in Integrated Circuits .............................................. 406

N Karimi, K Chakrabarty, P Gupta and S Patil A New SBST Algorithm for Testing the Register File of VLIW Processors.............................................. 412

D Sabena, M Sonza Reorda and L Sterpone On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints ......................... 418

J Jiang, M Sauer, A Czutro, B Becker and I Polian 5.1 Special Day E-Mobility – Embedded Systems and SW Challenges: Moderator: S Chakraborty, TU Munich, DE Embedded Systems and Software Challenges in Electric Vehicles ........................................................ 424 S Chakraborty, M Lukasiewycz, C Buckl, S Fahmy, N Chang, S Park, Y Kim,

P Leteinturier and H Adlkofer 5.2 Panel - Accelerators and Emulatiors for HS Verification Moderator: B Al-Hashimi U of Southampton, UK Accelerators and Emulators: Can They Become the Platform of Choice for Hardware Verification? ............................................................................................................................................. 430 5.3 Medical and Healthcare Applications Moderators: C Van Hoof, IMEC, BE; Y Chen, ETH Zuerich, CH A Closed-loop System for Artifact Mitigation in Ambulatory Electrocardiogram Monitoring .................... 431

M Shoaib, G Marsh, H Garudadri and S Majumdar Enabling Advanced Inference on Sensor Nodes Through Direct Use of Compressively-sensed Signals...................................................................................................................................................... 437

M Shoaib, N K Jha and N Verma A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System............................................................................................... 443

G Yang, J Chen, F Jonsson, H Tenhunen and L-R Zheng 5.4 Microarchitecture Moderators: M Berekovic, TU Braunschweig, DE; T Austin, U of Michigan, US Energy-Efficient Branch Prediction with Compiler-Guided History Stack ................................................ 449

M Tan, X Liu, Z Xie, D Tong and X Cheng Toward Virtualizing Branch Direction Prediction...................................................................................... 455

M Sadooghi-Alvandi, K Aasaraai and A Moshovos S/DC: A Storage and Energy Efficient Data Prefetcher ........................................................................... 461

X Dang, X Wang, D Tong, J Lu, J Yi and K Wang An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors ............................................................................................................................................... 467

M Kamal, A Afzali-Kusha, S Safari and M Pedram 5.5 Shared Memory Management in Multicore Moderators: C Silvano, Polimi, IT; M Berekovic, TU Braunschweig, DE PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches.................................... 473

K Aisopos, J Moses, R Illikkal, R Iyer and D Newell

Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores................ 479

A Das, M Schuchardt, N Hardavellas, G Memik and A Choudhary Dynamic Cache Management in Multi-Core Architectures through Run-time Adaptation....................... 485

F Hameed, L Bauer and J Henkel Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs ................................................................................................................................. 491

J L Abellan, J Fernandez, M E Acacio, D Bertozzi, D Bortolotti, A Marongiu and L Benini 5.6 Scheduling and Allocation Moderators: G Lipari, Scuola Superiore Sant'Anna, IT; R Kirner, Hertfortshire U, UK Preemption Delay Analysis for Floating Non-Preemptive Region Scheduling ........................................ 497

J M Marinho, V Nelis, S M Petters and I Puaut Harmonic Semi-Partitioned Scheduling for Fixed-Priority Real-Time Tasks on Multi-Core Platform ....... 503

M Fan and G Quan Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving................................... 509

J Huang, J O Blech, A Raabe, C Buckl and A Knoll Formal Analysis of Sporadic Overload in Real-Time Systems ................................................................ 515

S Quinton, M Hanke and R Ernst 5.7 Testing of Non-Volatile Memories Moderators: R Aitken, ARM, US; B Tasic, NXP Semiconductors, NL Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis ................ 521

Y Cai, E F Haratsch, O Mutlu and K Mai Modeling and Testing of Interference Faults in the Nano NAND Flash Memory..................................... 527

J Zha, X Cui and C L Lee Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures ............................ 532

J Azevedo, A Virazel, A Bosio, L Dilillo, P Girard, A Todri, G Prenat, J Alvarez-Herault and K Mackay

IP2 Interactive Presentations Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling.............................................................................................................................. 538

F Jafari, A Jantsch and Z Lu Dynamic-Priority Arbiter and Multiplexer Soft Macros for On-Chip Networks Switches .......................... 542

G Dimitrakopoulos and E Kalligeros Low Power Aging-Aware Register File Design by Duty Cycle Balancing................................................ 546

S Wang, T Jin, C Zheng and G Duan PowerAdviser: An RTL Power Platform for Interactive Sequential Optimizations ................................... 550

N Vyagrheswarudu, S Das and A Ranjan Towards Parallel Execution of IEC 61131 Industrial Cyber-Physical Systems Applications .............................................................................................................................................. 554

A Canedo and M A Al-Faruque

A Scan Pattern Debugger for Partial Scan Industrial Designs................................................................. 558

K Chandrasekar, S K Misra, S Sengupta and M S Hsiao FAST-GP: An RTL Functional Verification Framework Based on Fault Simulation on GP-GPUs ............................................................................................................................................ 562

N Bombieri, F Fummi and V Guarnieri

Exploiting Binary Translation for Fast ASIP Design Space Exploration on FPGAs................................. 566 S Pomata, P Meloni, G Tuveri, L Raffo and M Lindwer

Design of a Low-Energy Data Processing Architecture for WSN Nodes................................................. 570

C Walravens and W Dehaene Application-Specific Power-Efficient Approach for Reducing Register File Vulnerability ........................ 574

H Tabkhi and G Schirner On-line Scheduling of Target Sensitive Periodic Tasks with the Gravitational Task Model .................... 578

R Guerra and G Fohler Online Scheduling for Multi-Core Shared Reconfigurable Fabric ............................................................ 582

L Chen, T Marconi and T Mitra SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model.................................................. 586

A Mohammadi, M Ebrahimi, A Ejlali and S G Miremadi 6.1 PANEL - Role of EDA in the Development of Electric Vehicles (Special Day E-Mobility) .............................................................................................................................................. 590 Moderator: O Bringmann, FZI Research Center for Information Technology, Karlsruhe, DE 6.1.2 Keynote Address Research and Innovation on Advanced Computing – an EU Perspective............................................... 591

Thierry Van der Pyl, Director Components and Systems, European Commission 6.2 EMBEDDED TUTORIAL - Memristor Technology Moderator: R Tetzlaff, TU Dresden, DE Memristor Technology in Future Electronic System Design .................................................................... 592

R Tetzlaff, A Bruening L O Chua, R S Williams 6.3 Thermal Aware Low Power Design Moderators: A Macii, Politecnico di Torino, IT; A Garcia-Ortiz, Bremen U, DE TempoMP: Integrated Prediction and Management of Temperature in Heterogeneous MPSoCs ......... 593

S Sharifi, R Ayoub and T Simunic Rosing Thermal Balancing of Liquid-Cooled 3D-MPSoCs Using Channel Modulation ........................................ 599

M M Sabry, A Sridhar and D Atienza Statistical Thermal Modeling and Optimization Considering Leakage Power Variations ......................... 605

D-C Juan, Y-L Chuang, D Marculescu, Y-W Chang Analysis and Runtime Management of 3D Systems with Stacked DRAM for Boosting Energy Efficiency ................................................................................................................................................... 611

J Meng and A K Coskun

6.4 Basic Techniques for Improving the Formal Verification Flow Moderators: M Wedler, Kaiserslautern U, DE; G Cabodi, Politecnico di Torino, IT A Guiding Coverage Metric for Formal Verification................................................................................... 617

F Haedicke, D Grosse and R Drechsler Verification of Partial Designs Using Incremental QBF Solving............................................................... 623

P Marin, C Miller, M Lewis and B Becker Non-Solution Implications Using Reverse Domination in a Modern SAT-based Debugging Environment ............................................................................................................................................. 629

B Le, H Mangassarian, B Keng and A Veneris 6.5 System-on-Chip Composition and Synthesis Moderators: T Stefanov, Leiden U, NL; D Sciuto, Politecnico di Milano, IT Optimizing Performance Analysis for Synchronous Dataflow Graphs with Shared Resources .............. 635

D Thiele and R Ernst Compositional System-Level Design Exploration with Planning of High-Level Synthesis....................... 641

H-Y Liu, M Petracca and L P Carloni Correct-by-Construction Multi-Component SoC Design ........................................................................... 647

R Sinha, P S Roop, Z Salcic and S Basu 6.6 Timing Analysis Moderators: P Puschner, TU Wien, AT; S M Petters, CISTER-ISEP, PT Model Checking of Scenario-Aware Dataflow with CADP ........................................................................653

B Theelen, J-P Katoen and H Wu An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture................................ 659

A Prakash and H D Patel Bounding WCET of Applications Using SDRAM with Priority Based Budget Scheduling in MPSoCs .................................................................................................................................................... 665

H Shah, A Raabe and A Knoll Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications ................. 671

M Gerdes, F Kluge, T Ungerer, C Rochange and P Sainrat 6.7 HOT TOPIC - Design for Test and Reliability in Ultimate CMOS Moderator: L Anghel, TIMA, FR Design for Test and Reliability in Ultimate CMOS .................................................................................... 677

M Nicolaidis, L Anghel, N-E Zergainoh, Y Zorian, T Karnik, K Bowman, J Tschanz, S-L Lu, C Tokunaga, A Raychowdhury, M Khellah, J Kulkarni, V De and D Avresky

7.1 HOT TOPIC - Energy of Optimization (Special Day E-Mobility) Moderator: K Knoedler, Robert Bosch GmbH, Heilbronn, DE Optimal Energy Management and Recovery for FEV............................................................................... 683

K Knoedler, J Steinmann, S Laversanne, S Jones, A Huss, E Kural, D Sanchez, O Bringmann, J Zimmermann,

7.2 HOT TOPIC - Virtual Platforms: Breaking New Grounds Moderators: S A Huss, TU Darmstadt, DE Virtual Platforms: Breaking New Grounds ............................................................................................... 685

R Leupers, G Martin, R Plyaskin, A Herkersdorf, F Schirrmeister, T Kogel, M Vaupel 7.3 Multimedia and Consumer Applications Moderators: T Theocharides, Cyprus U, CY; F Kienle, TU Kaiserslautern, DE An FPGA-based Accelerator for Cortical Object Classification ............................................................... 691

M S Park, S Kestur, J Sabarad, V Narayanan and M J Irwin Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding ................... 697

M Shafique, B Zatt, S Rehman, F Kriebel and J Henkel Towards Accurate Hardware Stereo Correspondence: A Real-Time FPGA Implementation of a Segmentation-Based Adaptive Support Weight Algorithm ................................................................ 703

C Ttofis and T Theocharides An FPGA-based Parallel Processor for Black-Scholes Option Pricing Using Finite Differences Schemes ................................................................................................................................................... 709

G Chatziparaskevas, A Brokalakis and I Papaefstathiou 7.4 Nanoelectronic Devices Moderators: S Garg, Toronto U, CA; C Nicopoulos, Cyprus U, CY A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits ............................ 715

L Sekanina and Z Vasicek Mach-Zehnder Interferometer Based Design of All Optical Reversible Binary Adder ............................. 721

S Kotiyal, H Thapliyal and N Ranganathan Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever- Based NEMS Switches ............................................................................................................................. 727

S Patil, M-W Jang, C-L Chen, D Lee, Z Ye, W E Partlo III, D J Lilja, S A Campbell and T Cui

7.5 High Level and Statistical Design of Mixed-Signal Systems Moderators: C Dehollain, EPF Lausanne, CH; D Morche, CEA-LETI, FR Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters .................................................................................................. 733

L Wang, T J Kazmierski, B M Al-Hashimi, M Aloufi and J Wenninger Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System .................................................................................................... 739

A Leveque, F Pecheux, M-M Louerat and H Aboushady, F Cenni, S Scotti, A Massouri and L Clavier

Hierarchical Analog Circuit Reliability Analysis Using Multivariate Nonlinear Regression and Active Learning Sample Selection ........................................................................................................... 745

E Maricau, D De Jonghe and G Gielen A Fast Analog Circuit Yield Estimation Method for Medium and High Dimensional Problems................ 751

B Liu, J Messaoudi and G Gielen

Fast Isomorphism Testing for a Graph-based Analog Circuit Synthesis Framework .............................. 757

M Meissner, O Mitea, L Luy and L Hedrich

7.6 Advances in Dataflow Modeling and Analysis Moderators: C Haubelt, Rostock U, DE; L S Indrusiak, York U, UK Design of Streaming Applications on MPSoCs Using Abstract Clocks ................................................... 763

A Gamatie SPDF: A Schedulable Parametric Data-Flow MoC.................................................................................. 769

P Fradet, A Girault and P Poplavko Modeling Static-Order Schedules in Synchronous Dataflow Graphs ...................................................... 775

M Damavandpeyma, S Stuijk, T Basten, M Geilen and H Corporaal Design Space Pruning through Hybrid Analysis in System-level Design Space Exploration.................. 781

R Piscitelli and A D Pimentel 7.7 Test and Repair of New Technologies Moderators: J Tyszer, TU Poznan, PL; H-J Wunderlich, Stuttgart U, DE Test Pin Count Reduction for NoC-based Test Delivery in Multicore SOCs ........................................... 787

M Richter and K Chakrabarty On Effective TSV Repair for 3D-Stacked ICs .......................................................................................... 793

L Jiang, Q Xu and B Eklow DfT Schemes for Resistive Open Defects in RRAMs .............................................................................. 799

N Z Haron and S Hamdioui 7.8 HOT TOPIC - New Directions in Timing Modeling and Analysis of Automotive Software Moderator: W Mueller, U Paderborn, DE Timing Modeling with AUTOSAR - Current State and Future Directions................................................. 805 M-A Peraldi-Frati, H Blom, D Karlsson and S Kuntz Challenges and New Trends in Probabilistic Timing Analysis ................................................................. 810

S Quinton, R Ernst, D Bertrand and P Meumeu Yomsi IP3 Interactive Presentations QBF-Based Boolean Function Bi-Decomposition .................................................................................... 816

H Chen, M Janota and J Marques-Silva Automatic Transition Between Structural System Views in a Safety Relevant Embedded Systems Development Process ................................................................................................................ 820

C Ellen, C Etzien and M Oertel Towards New Applications of Multi-Function Logic: Image Multi-Filtering................................................ 824

L Sekanina and V Salajka Memory-Map Selection for Firm Real-Time SDRAM Controllers ............................................................. 828

S Goossens, T Kouters, B Akesson and K Goossens Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs ............. 832

Y Liang, Z Cui, S Zhao, K Rupnow, Y Zhang, D L Jones and D Chen

Impact of TSV Area on the Dynamic Range and Frame Rate Performance of 3D-Integrated Image Sensors ......................................................................................................................................... 836

A Xhakoni, D San Segundo Bello and G Gielen Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric.................... 840

M J Dousti and M Pedram Voltage Propagation Method for 3-D Power Grid Analysis...................................................................... 844

C Zhang, V F Pavlidis and G De Micheli Yield Optimization for Radio Frequency Receiver at System Level ......................................................... 848

S A Nazin, D Morche and A Reinhardt Parallel Statistical Analysis of Analog Circuits by GPU-accelerated Graph-based Approach................. 852

X-X Liu, S X-D Tan and H Wang Automated Critical Device Identification for Configurable Analogue Transistors ..................................... 858

R Rudolf, P Taatizadeh, R Wilcock and P Wilson Analysis of Multi-Domain Scenarios for Optimized Dynamic Power Management Strategies ................ 862

J Zimmermann, O Bringmann and W Rosenstiel PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing............................................... 866

A Das, U Kocabas, A-R Sadeghi and I Verbauwhede 8.1 HOT TOPIC - Robustness Challenges in Automotive (Special Day E-Mobility) Moderator: J Lau, Infineon, DE Complexity, Quality and Robustness - The Challenges of Tomorrow's Automotive Electronics.............. 870

U Abelein, H Lochner, D Hahn and S Straube Measuring and Improving the Robustness of Automotive Smart Power Microelectronics ...................... 872

T Nirmaier, V Meyer zu Bexten, M Tristl, M Harrant, M Kunze, M Rafaila, J Lau, G Pelz 8.2 PANEL - EDA for Trailing Edge Technologies Moderator: P Rolandi, STMicroelectronics Italy What Is EDA Doing for Trailing Edge Technologies? ............................................................................. 874

Panelists: A Bruening, A Domic, R Kress, J Sawicki and C Sebeke 8.3 Innovative Reliable Systems and Applications Moderators: J Ayala, Madrid Complutense U, ES; M D Santambrogio, Politecnico di Milano, IT Reli: Hardware/Software Checkpoint and Recovery Scheme for Embedded Processors....................... 875

T Li, R Ragel and S Parameswaran A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories.................................................................................................................................................. 881

C Zambelli, M Indaco, M Fabiano, S Di Carlo, P Prinetto, P Olivo and D Bertozzi A Resilient Architecture for Low Latency Communication in Shared-L1 Processor Clusters................... 887

M R Kakoee, I Loi and L Benini Performance-Reliability Tradeoff Analysis for Multithreaded Applications ............................................... 893

I Oz, H R Topcuoglu, M Kandemir and O Tosun

8.4 Advances in Formal SoC Verification Moderators: D Grosse, Bremen U, DE; F Rahim, Atrenta, FR Efficient Groebner Basis Reductions for Formal Verification of Galois Field Multipliers .......................... 899

J Lv, P Kalla and F Enescu Scalable Progress Verification in Credit-Based Flow-Control Systems.................................................... 905

S Ray and R K Brayton Formal Methods for Ranking Counterexamples through Assumption Mining .......................................... 911

S Mitra, A Banerjee and P Dasgupta 8.5 Variability and Delay Moderators: S Sapatnekar, Minnesota U, US; J Cortadella, UP Catalunya, ES Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations...................... 917

Q Tang, A Zjajo, M Berkelaar and N van der Meijs Current Source Modeling for Power and Timing Analysis at Different Supply Voltages .......................... 923

C Knoth, H Jedda and U Schlichtmann Clock Skew Scheduling for Timing Speculation........................................................................................ 929

R Ye, F Yuan, H Zhou and Q Xu 8.6 System-Level Optimization of Embedded Real-Time Systems Moderators: J Teich, Erlangen-Nuremberg U, DE; J-J Chen, Karlsruhe Institute of Technology, DE Robust and Flexible Mapping for Real-time Distributed Applications during the Early Design Phases ...................................................................................................................................................... 935

J Gan, P Pop, F Gruian and J Madsen A Methodology for Automated Design of Hard-Real-Time Embedded Streaming Systems..................... 941

M A Bamakhrama, J T Zhai, H Nikolov and T Stefanov Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints .................................................................................................................................. 947

K Jiang, P Eles and Z Peng 8.7 On-Line Test for Secure Systems Moderators: X Vera, Intel Labs Barcelona, ES; J Abella, Barcelona Supercomputing Center, ES Logic Encryption: A Fault Analysis Perspective........................................................................................ 953

J Rajendran, Y Pino, O Sinanoglu and R Karri Low-Cost Implementations of On-the-Fly Tests for Random Number Generators................................... 959

F Veljkovic, V Rozic and I Verbauwhede Post-Deployment Trust Evaluation in Wireless Cryptographic ICs........................................................... 965

Y Jin, D Maliuk and Y Makris

8.8 EMBEDDED TUTORIAL - Batteries and Battery Management Systems Moderators: L Fanucci, U Pisa, IT; H Gall, austriamicrosystems, AT Batteries and Battery Management Systems for Electric Vehicles........................................................... 971

M Brandl, H Gall, M Wenger, V Lorentz, M Giegerich, F Baronti, G Fantechi, L Fanucci, R Roncella, R Saletti, S Saponara, A Thaler, M Cifrain and W Prochazka

9.2 SPECIAL SESSION - From Ultra-Low-Power Multi-Core Design to Exascale Computing Moderators: R Hermida, UCM Madrid, ES; T Simunic Rosing, UCSD, US Power Management of Multi-Core Chips: Challenges and Pitfalls .......................................................... 977

P Bose, A Buyuktosunoglu, J A Darringer, M S Gupta, M B Healy, H Jacobson, I Nair, J A Rivers, J Shin, A Vega, A J Weger

P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator.............................................................................................................................. 983 L Benini, E Flamand, D Fuin and D Melpignano Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems ................... 988

A Y Dogan, J Constantin, M Ruggiero, A Burg and D Atienza Reducing the Energy Cost of Computing through Efficient Co-Scheduling of Parallel Workloads .......... 994

C Hankendi and A K Coskun

9.3 Architecture and Building Blocks for Secure Systems Moderators: L Fesquet, TIMA Laboratory, FR; L Torres, LIRMM, FR SAFER PATH: Security Architecture Using Fragmented Execution and Replication for Protection against Trojaned Hardware.................................................................................................... 1000

M Beaumont, B Hopkins and T Newby ASIC Implementations of Five SHA-3 Finalists....................................................................................... 1006

X Guo, M Srivastav, S Huang, D Ganta, M B Henry, L Nazhandali and P Schaumont Side Channel Analysis of the SHA-3 Finalists ........................................................................................ 1012

M Zohner, M Kasper, M Stoettinger and S A Huss 9.4 Advances in High-Level Synthesis Moderators: G Coutinho, ICL, UK; P Coussy, Bretagne-Sud U, FR Combining Module Selection and Replication for Throughput-Driven Streaming Programs.................. 1018

J Cong, M Huang, B Liu, P Zhang and Y Zou Exploiting Area/Delay Tradeoffs in High-Level Synthesis....................................................................... 1024

A Kondratyev, L Lavagno, M Meyer and Y Watanabe Predicting Best Design Trade-offs: A Case Study in Processor Customization ..................................... 1030

M Zuluaga, E Bonilla and N Topham 9.5 Supply Voltage and Circuitry Based Power Reductions Moderators: M Lopez-Vallejo, UP Madrid, ES; W Nebel, Oldenburg U and OFFIS, DE Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis .................................... 1036

R Wille, R Drechsler, C Osewold and A Garcia-Ortiz Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM....................... 1042

V Sharma, S Cosemans, M Ashouei, J Huisken, F Catthoor and W Dehaene Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems........................................ 1048

H R Pourshaghaghi, H Fatemi and J Pineda de Gyvez MAPG: Memory Access Power Gating ................................................................................................... 1054

K Jeong, A B Kahng, S Kang, T S Rosing and R Strong

State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems .................. 1060

Q Xie, X Lin, Y Wang, M Pedram, D Shin and N Chang 9.6 Creation and Processing of System-level Models Moderators: E Villar, Cantabria U, ES; J Haase, TU Wien, AT Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller..... 1066

V Todorov, D Mueller-Gritschneder, H Reinig and U Schlichtmann Refinement of UML/MARTE Models for the Design of Networked Embedded Systems........................ 1072

E Ebeid, F Fummi, D Quaglia and F Stefanni Debugging of Inconsistent UML/OCL Models......................................................................................... 1078

R Wille, M Soeken and R Drechsler 9.7 Test and Monitoring of RF and Mixed-Signal ICs Moderators: S Sattler, Erlangen-Nuremberg U, DE; H Stratigopoulos, IMAG / CNRS, FR An Analytical Technique for Characterization of Transceiver IQ Imbalances in the Loop-Back Mode ..................................................................................................................................... 1084

A Nassery and S Ozev Testing RF Circuits with True Non-Intrusive Built-In Sensors................................................................. 1090

L Abdallah, H-G Stratigopoulos, S Mir and J Altet Monitoring Active Filters under Automotive Aging Scenarios with Embedded Instrument ..................... 1096

J Wan and H G Kerkhoff IP4 Interactive Presentations Analysis of Instruction-level Vulnerability to Dynamic Voltage and Temperature Variations ............................................................................................................................................... 1102

A Rahimi, L Benini and R K Gupta CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions....... 1106

A Pellegrini, R Smolinski, L Chen, X Fu, S K S Hari, J Jiang, S V Adve, T Austin and V Bertacco,

A Hybrid HW-SW Approach for Intermittent Error Mitigation in Streaming-Based Embedded Systems ................................................................................................................................ 1110

M M Sabry, D Atienza and F Catthoor Probabilistic Response Time Bound for CAN Messages with Arbitrary Deadlines ................................ 1114

P Axer, M Sebastian and R Ernst Exploring Pausible Clocking Based GALS Design for 40-nm System Integration.................................. 1118

X Fan, M Kristic, E Grass, B Sanders and C Heer Static Analysis of Asynchronous Clock Domain Crossings ....................................................................1122

S Chaturvedi A Scalable GPU-based Approach to Accelerate the Multiple-choice Knapsack Problem..................... 1126

B Suri, U D Bordoloi and P Eles Enhancing Non-Linear Kernels by an Optimized Memory Hierarchy in a High Level Synthesis Flow ........................................................................................................................................ 1130

S Mancini and F Rousseau

Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors .............. 1134

A A Sinkar, H Wang and N S Kim An Energy Efficient DRAM Subsystem for 3D Integrated SoCs ............................................................. 1138

C Weis, I Loi, L Benini and N Wehn Eliminating Invariants in UML/OCL Models ............................................................................................ 1142

M Soeken, R Wille and R Drechsler On-Chip Source Synchronous Interface Timing Test Scheme with Calibration ..................................... 1146

H Kim and J A Abraham 10.1 SPECIAL DAY MORE-THAN-MOORE: Technologies Moderator: M Brillouët, CEA-Leti, FR ITRS 2011 Analog EDA Challenges and Approaches – Invited Paper................................................... 1150

H Graeb UWB: Innovative Architectures Enable Disruptive Low Power Wireless Applications – Invited Paper .......................................................................................................................................... 1156

D Morche, M Pelissier, G Masson and P Vincent 10.2 Pathways to Servers of the Future Moderator: G Fettweis, TU Dresden, DE Pathways to Servers of the Future - Highly Adaptive Energy Efficient Computing (HAEC) ................. 1161

G Fettweis, W Nagel and W Lehner 10.3 Side-Channel Analysis and Protection of Secure Embedded Systems Moderators: F Regazzoni, ALaRI, CH; P Schaumont, Virginia Tech, US Amplitude Demodulation-based EM Analysis of Different RSA Implementations ................................. 1167

G Perin, L Torres, P Benoit and P Maurine RSM: A Small and Fast Countermeasure for AES, Secure against First- and Second-order Zero-Offset SCAs................................................................................................................................... 1173

M Nassar, Y Souissi, S Guilley and J-L Danger Revealing Side-Channel Issues of Complex Circuits by Enhanced Leakage Models............................ 1179

A Heuser, W Schindler and M Stoettinger 10.4 Topics in High-Level Synthesis Moderators: K Bertels, TU Delft, NL; P Brisk, UC Riverside, US 3DHLS: Incorporating High-Level Synthesis in Physical Planning of Three-Dimensional (3D) ICs .................................................................................................................................................. 1185

Y Chen, G Sun, Q Zou and Y Xie Multi-Token Resource Sharing for Pipelined Asynchronous Systems.................................................... 1191

J Hansen and M Singh Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs...................................... 1197

L Aksoy, E Costa, P Flores and J Monteiro

10.5 Modeling of Complex Analogue and Digital Systems Moderators: T Kazmierski, Southampton U, UK; N van der Meijs, TU Delft, NL An Efficient Framework for Passive Compact Dynamical Modeling of Multiport Linear Systems .......... 1203

Z Mahmood, R Suaya and L Daniel Analysis and Design of Sub-Harmonically Injection Locked Oscillators ................................................ 1209

A Neogy and J Roychowdhury Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping................... 1215

P Gao, X Xing, J Craninckx and G Gielen Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates................................. 1221

W Schoenmaker, M Matthes, B De Smedt, S Baumanns, C Tischendorf and R Janssen 10.6 Cyber-Physical Systems Moderators: P Eles, Linkoping U, SE; R Ernst, TU Braunschweig, DE Time-triggered Implementations of Mixed-Criticality Automotive Software ............................................ 1227

D Goswami, M Lukasiewycz, R Schneider and S Chakraborty Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols .......................... 1233

A Masrur, D Goswami, S Chakraborty, J-J Chen, A Annaswamy and A Banerjee A Cyberphysical Synthesis Approach for Error Recovery in Digital Microfluidic Biochips...................... 1239

Y Luo, K Chakrabarty and T-Y Ho Predictive Control of Networked Control Systems over Differentiated Services Lossy Networks.......... 1245

R Muradore, D Quaglia and P Fiorini 10.7 On-Line Test and Fault Tolerance Moderators: D Gizopoulos, Athens U, GR; M Nicolaidis, TIMA Laboratory, FR Input Vector Monitoring on Line Concurrent BIST Based on Multilevel Decoding Logic........................ 1251

I Voyiatzis High Performance Reliable Variable Latency Carry Select Addition ...................................................... 1257

K Du, P Varman and K Mohanram Salvaging Chips with Caches beyond Repair ......................................................................................... 1263

H Hsuing, B Cha and S K Gupta Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms..................................................................... 1269

K-C Wu, M-C Lee, D Marculescu and S-C Wang 10.8 EMBEDDED TUTORIAL - Moore Meets Maxwell Moderator: R Camposano, Nimbic Inc., US Moore Meets Maxwell ............................................................................................................................. 1275

R Camposano, D Gope, S Grivet-Talocia and V Jandhyala

11.1 SPECIAL DAY MORE-THAN-MOORE: Heterogeneous Integration Moderator: M Brillouët, CEA-Leti, FR Challenges and Emerging Solutions in Testing TSV-Based 2½ D-and 3D-Stacked ICs – Invited Paper .......................................................................................................................................... 1277

E J Marinissen 11.2 The Quest for NoC Performance Moderators: D Bertozzi, Ferrara U, IT; C Seiculescu, EPF Lausanne, CH A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up ................................................. 1283

R Stefan, A Molnos, A Ambrose and K Goossens Parallel Probing: Dynamic and Constant Time Setup Procedure in Circuit Switching NoC ................... 1289

S Liu, A Jantsch and Z Lu A Flit-level Speedup Scheme for Network-on-Chips Using Self-Reconfigurable Bi-directional Channels ........................................................................................................................... 1295

Z Qian, Y F Teh and C-Y Tsui 11.3 Emerging Memory Technologies (1) Moderators: G Sun, Peking U, CN; Y Liu, Tsinghua U, CN Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference .................. 1301

X Bi, C Zhang, H Li, Y Chen and R E Pino 3D-FlashMap: A Physical-Location-Aware Block Mapping Strategy for 3D NAND Flash Memory ........ 1307

Y Wang, L A D Bathen, Z Shao and N D Dutt Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs ................................................ 1313

Y Zhang, X Wang, Y Li, A K Jones and Y Chen 11.4 Physical Anchors for Secure Systems Moderators: L Torres, LIRMM, FR; V Fischer, Hubert Curien Laboratory, FR Comparative Analysis of SRAM Memories Used as PUF Primitives...................................................... 1319

G-J Schrijen and V van der Leest Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs .............. 1325

A Cherkaoui, V Fischer, A Aubert and L Fesquet A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection............................... 1331

M Li, A Davoodi and M Tehranipoor 11.5 Analogue Design Validation Moderators: M Zwolinski, Southampton U, UK; J Raik, TU Tallin, EE Towards Improving Simulation of Analog Circuits Using Model Order Reduction.................................. 1337

H Aridhi, M H Zaki and S Tahar Efficiency Evaluation of Parametric Failure Mitigation Techniques for Reliable SRAM Operation........ 1343

E I Vatajelu and J Figueras A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation ............... 1349

X-X Liu, S X-D Tan, H Wang and H Yu

Simulation of the Steady State of Oscillators in the Time Domain ......................................................... 1355

H G Brachtendorf, K Bittner and R Laur 11.6 Techniques and Technologies Power Aware Reconfiguration Moderators: M Platzner, Paderborn U, DE; D Goehringer, Fraunhofer Institute, DE Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique ................................................................................................................................... 1361

C Chen, W S Lee, R Parsa, S Chong, J Provine, J Watt, R T Howe, H-S P Wong and S Mitra

State-based Full Predication for Low Power Coarse-Grained Reconfigurable Architecture .................. 1367

K Han, S Park and K Choi UPaRC -- Ultra-Fast Power-aware Reconfiguration Controller .............................................................. 1373

R Bonamy, H-M Pham, S Pillement and D Chillet Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures............................................................................................................. 1379

G Mariani, V-M Sima, G Palermo, V Zaccaria, C Silvano and K Bertels 11.7 Rise and Fall of Layout Moderators: R Otten, TU Eindhoven, NL; P Groeneveld, Magma Design Automation, US VLSI Legalization with Minimum Perturbation by Iterative Augmentation .............................................. 1385

U Brenner Agglomerative-Based Flip-Flop Merging with Signal Wirelength Optimization....................................... 1391

S S-Y Liu, C-J Lee and H-M Chen Fixed Origin Corner Square Inspection Layout Regularity Metric........................................................... 1397

M Pons, M Morgan and C Piguet

11.8 HOT TOPIC - Programmability and Performance Portability of Multi-/Many-Core Moderator: C Kessler, Linkoping U, SE Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems................................................................................................................................................... 1403

C Kessler, U Dastgeer, S Thibault, R Namyst, A Richards, U Dolinsky, S Benkner, J L Traff and S Pllana

IP5 Interactive Presentations Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC.................................................................................................................................. 1409

Y Xu, W Yu, Q Chen, L Jiang and N Wong Verifying Jitter in an Analog and Mixed Signal Design Using Dynamic Time Warping ......................... 1413

R Narayanan, A Daghar, M H Zaki and S Tahar MEDS: Mockup Electronic Data Sheets for Automated Testing of Cyber-Physical Systems Using Digital Mockups.............................................................................................................. 1417

B Miller, F Vahid and T Givargis Component-Based and Aspect-Oriented Methodology and Tool for Real-Time Embedded Control Systems Design ....................................................................................................... 1421

R Hamouche and R Kocik Cyber-Physical Cloud Computing: The Binding and Migration Problem ................................................ 1425

C Kirsch, E Pereira, R Sengupta, H Chen, R Hansen, J Huang, F Landolt, M Lippautz, A Rottmann, R Swick, R Trummer, and D Vizzini

An Adaptive Approach for Online Fault Management in Many-Core Architectures................................ 1429

C Bolchini, A Miele and D Sciuto An Hybrid Architecture to Detect Transient Faults in Microprocessors: An Experimental Validation................................................................................................................................................ 1433

S Campagna and M Violante Evaluation of a New RFID System Performance Monitoring Approach.................................................. 1439

G Fritz, V Beroulle, O-E-K Aktouf and D Hely A Framework for Simulating Hybrid MTJ/CMOS Circuits: Atoms to System Approach ......................... 1443

G Panagopoulos, C Augustine and K Roy A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems............................................................................................................ 1447

D Liu, T Wang, Y Wang, Z Qin and Z Shao Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices .......................... 1451

B Zhao, J Yang, Y Zhang, Y Chen and H Li Layout-Aware Optimization of STT MRAMs ........................................................................................... 1455

S K Gupta, S P Park, N N Mojumder and K Roy Characterization of the Bistable Ring PUF ............................................................................................. 1459

Q Chen, G Csaba, P Lugli, U Schlichtmann and U Ruehrmair An Operational Matrix-Based Algorithm for Simulating Linear and Fractional Differential Circuits .................................................................................................................................. 1463

Y Wang, H Liu, G K H Pang and N Wong A Flexible and Fast Software Implementation of the FFT on the BPE Platform..................................... 1467

T Cupaiuolo and D Lo Iacono Hierarchical Propagation of Geometric Constraints for Full-Custom Physical Design of ICs........................................................................................................................................... 1471

M Mittag, A Krinke, G Jerke and W Rosenstiel Double-Patterning Friendly Grid-Based Detailed Routing with Online Conflict Resolution ............................................................................................................................................... 1475

I S Abed and A G Wassal Design and Analysis of Via-Configurable Routing Fabrics for Structured ASICs ................................... 1479

H-P Tsai, R-B Lin and L-C Lai 12.1 SPECIAL DAY MORE-THAN-MOORE: Applications Moderator: M Brillouët, CEA-Leti, FR Towards A Wireless Medic Smart Card – Invited Paper.........................................................................1483

S Krone, B Almeroth, F Guderian and G Fettweis

12.2 The Frontier of NoC Design Moderators: K Goossens, TU Eindhoven, NL; S Murali, IMEC India, CH A Fast, Source-Synchronous Ring-based Network-on-Chip Design ..................................................... 1489

A Mandal, S P Khatri and R N Mahapatra Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches............................................. 1495

W Song, D Edwards, J Garside and W J Bainbridge Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication .......................... 1501

Y Zheng, P Lisherness, M Gao, J Bovington, S Yang and K-T Cheng 12.3 Emerging Memory Technologies (2) Moderators: H Li, NYU, US; Z Shao, The Hong Kong Polytechnic U, CN Modeling and Design Exploration of FBDRAM as On-chip Memory ......................................................1507

G Sun, C Xu and Y Xie Bloom Filter-based Dynamic Wear Leveling for Phase-Change RAM ................................................... 1513

J Yun, S Lee and S Yoo A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors ...................... 1519

Y Wang, Y Liu, Y Liu, D Zhang, S Li, B Sai, M-F Chiang and H Yang 12.4 Digital Communication Systems Moderators: F Kienle, TU Kaiserslautern, DE; F Clermidy, CEA-LETI, FR A Network-on-Chip-based Turbo/LDPC Decoder Architecture...............................................................1525

C Condo, M Martina and G Masera A Complexity Adaptive Channel Estimator for Low Power ..................................................................... 1531

Z Yu, C H van Berkel and H Li A High Performance Split-Radix FFT with Constant Geometry Architecture.......................................... 1537

J Kwong and M Goel 12.5 Architecture and Networks for Adaptive Computing Moderators: F Ferrandi, Politecnico di Milano, IT; S Niar, Valenciennes U, FR Selective Flexibility: Breaking the Rigidity of Datapath Merging............................................................. 1543

M Stojilovic, D Novo, L Saranovac, P Brisk and P Ienne An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design................................... 1549

M Rosière, J-I Desbarbieux, N Drach and F Wajsbürt Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures ............................................ 1555

A Grudnitsky, L Bauer and J Henkel Congestion-Aware Scheduling for NoC-based Reconfigurable Systems............................................... 1561

H-L Chao, Y-R Chen, S-Y Tung, P-A Hsiung and S-J Chen

12.6 Boolean Methods in Logic Synthesis Moderators: M Berkelaar, TU Delft, NL; J Monteiro, INESC-ID/TU Lisbon, PT Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction ................................................................................................................................................ 1567

K-F Tang, P-K Huang, C-N Chou and C-Y Huang Almost Every Wire is Removable: A Modeling and Solution for Removing Any Circuit Wire................. 1573

X Yang, T-K Lam, W-C Tang and Y-L Wu Mapping into LUT Structures .................................................................................................................. 1579

S Ray, A Mishchenko, N Een, R Brayton, S Jang and C Chen Row-Shift Decompositions for Index Generation Functions ................................................................... 1585

T Sasao Custom On-Chip Sensors for Post-Silicon Failing Path Isolation in the Presence of Process Variations ................................................................................................................................................ 1591

M Li, A Davoodi and L Xie 12.7 Impact of Modern Technology on Layout Moderators: J Lienig, TU Dresden, DE; P Groeneveld, Magma Design Automation, US On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer................................................. 1597

H-W Hsu, M-L Chen, H-M Chen, H-C Li and S-H Chen AIR (Aerial Image Retargeting): A Novel Technique for In-Fab Automatic Model-Based Retargeting-for-Yield ............................................................................................................................... 1603

A Y Hamouda, M Anis and K S Karim Layout-Driven Robustness Analysis for Misaligned Carbon Nanotubes in CNTFET-based Standard Cells......................................................................................................................................... 1609

M Beste and M B Tahoori 12.8 EMBEDDDED TUTORIAL - Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs Moderator: TBD Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs................................... 1615

D De Jonghe, E Maricau, G Gielen, T McConaghy, B Tasic, and H Stratigopoulos Author Index