Low-Frequency Noise and RTN on Near-Ballistic III-V GAA Nanowire MOSFETs N. Conrad, M. Si*, S. H. Shin, J. J. Gu, J. Zhang, M. A. Alam, P. D. Ye**

School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906, U.S.A. Tel: 1-765-494-7611, Fax: 1-765-496-6443, *Email: msi@purdue.edu **Email: yep@purdue.edu

Abstract

In this work, we report the first observation of RTN in highly scaled InGaAs GAA MOSFETs fabricated by a top-down approach. RTN and low frequency noise were systematically studied for devices with various gate dielectrics, channel lengths and nanowire diameters. Mobility fluctuation is confirmed to be the source of low-frequency noise, showing 1/f characteristics. Low-frequency noise was found to decrease as the channel length scaled down from 80 nm to 20 nm, indicating the near-ballistic transport in highly scaled InGaAs GAA MOSFET.

Introduction

InGaAs has been considered as one of the promising channel materials for CMOS logic circuit beyond 10 nm node because of its large electron injection velocity [1]. InGaAs gate-all-around (GAA) MOSFETs have been demonstrated to offer large drive current and excellent immunity to short channel effects down to deep sub-100 nm channel length [2]. On the other hand, classical theories suggest that low-frequency noise increases inversely with decreasing channel length. If it is true, this may negate some of the performance gain of short channel transistors [3-5]. Meanwhile, traditional oxide characterization methods, such as C-V and charge pumping, cannot be used for ultra-small devices without a body contact. Therefore, noise and RTN characterizations can be used as alternative probes to quantitatively analyze performance, variability and reliability of highly scaled devices [6-10]. Several groups have recently reported RTN of bottom-up synthesized long-channel InAs nanowire MOSFETs [11-13]. However, there is no report on RTN and low-frequency noise studies of highly scaled III-V GAA MOSFETs by top-down approach. In this work, we (i) report the first observation of RTN on top-down fabricated InGaAs GAA MOSFETs, (ii) examine the origin of low-frequency noise on highly scaled InGaAs GAA MOSFETs, (iii) systematically study the low-frequency noise and RTN characteristics of near-ballistic InGaAs GAA nanowire MOSFETs.

Experiments

Fig. 1(a) shows the schematic diagram and cross-sectional view of an InGaAs GAA MOSFET. The top-down fabrication process is shown in Fig. 1(b), which is the same as reported in Ref. [2]. The samples used for noise characterizations and device dimensions are summarized in Table 1. Samples A and B have a 0.5 nm Al2O3/4 nm LaAlO3 stack (EOT = 1.2 nm), where Al2O3 was grown before LaAlO3 for sample A and reverse order for sample B. Sample C has 3.5 nm Al2O3 as gate dielectric (EOT = 1.7 nm). The

RTN and low-frequency characterization setup is shown in Fig. 2. The gate voltage (Vgs) is supplied by a digital controllable voltage source. A Stanford SR570 battery-powered current amplifier is used as source voltage supply and monitor for the source current (Is). Is is used due to the relatively large junction leakage current in drain current (Id). Is shows more clearly the fundamental transport properties inside the nanowire. The amplifier output is directly connected to a Tektronix TDS5032B oscilloscope to record RTN signal and an Agilent 35670A dynamic signal analyzer to obtain the power spectrum density (PSD) of the noise of Is. All noise measurements were performed at Vds =50mV and at room temperature unless otherwise specified.

Results and Discussion

Figs. 3-4 show the well-behaved output and transfer characteristics of a GAA MOSFET with Lch=WNW=20 nm. PBTI measurement at Vgs=0.6, 0.8V on Sample A and B is shown in Fig. 5. PBTI measurement on Sample C can be found in [14]. VT shifts less than 10 mV during noise measurements is ensured under maximum Vgs=0.4 V conditions. Fig. 6(a) and (b) show the RTN signals of an InGaAs GAA MOSFET, with Lch=20 nm, WNW=80 nm and 3.5 nm Al2O3 as gate dielectric, in time domain at Vgs=-0.025 V and Vgs=-0.075 V at 15oC. The histogram and lag plot at Vgs=-0.025 V of the same device are shown in Fig. 7(a) and (b). Two distinct current switching levels are observed, which clearly indicates the existence of a single active trap. Fig. 8 shows ‘PSD of Is’ normalized by Is

2 (i.e., SIs/Is

2) of the RTN signal shown in Fig. 6(a). A typical Lorentzian spectrum is shown in the noise spectrum with 1/f2 characteristics. Clear RTN signals are observed on about 1/3 of devices measured on Sample A, B and C, but only when Vgs is near threshold voltage (VT). Fig. 9 shows the comparison of noise spectrum between a device with RTN signal and a device without RTN. The two devices share the same device dimension with Lch=20 nm, WNW=25 nm and 3.5 nm Al2O3 as gate dielectric. It is clear that the noise spectrum of the device without RTN shows 1/f characteristics, while the noise spectrum of the device with RTN is the superposition of 1/f noise spectrum and a Lorentzian spectrum. Fig. 10 shows (a) Is histogram and (b), (c) RTN signals in time domain on a Lch=20 nm, WNW=25 nm device of Sample B, showing the superposition of RTN signal and mobility fluctuation (1/f) noise. This phenomenon suggests the fact that mobility fluctuation (rather than carrier number fluctuation) is the origin of low-frequency noise on devices without RTN signal. Fig. 11 shows SIs/Is

2 as a function of Is on Sample A, B and C with Lch=20nm and WNW=20nm at f=10Hz which are weakly dependent on the different interfaces. All the three selected devices show 1/f spectrum

20.1.1 IEDM14-502978-1-4799-8001-7/14/$31.00 ©2014 IEEE

without RTN. That SIs/Is2 can be modulated by Is indicates

that the noise source is from channel rather than series resistance. In addition, SIs/Is

2 depends only weakly on the gate oxide, suggesting that oxide trapping and de-trapping induced carrier number fluctuation is not the source of low-frequency noise in this work. Fig. 12 shows the scaling metrics of SIs/Is

2 versus Lch at f=10 Hz and WNW=20 nm for Sample B. Normalized Is noise is reduced as Lch scaling down, which is opposite to the conventional noise Lch scaling characteristic (SIs/Is

2~1/Lch). This phenomenon leads to the main conclusion of this work: that near-ballistic transport of electrons in the channel is achieved, as determined through noise studies. As electrons from the source cannot equilibrate to lattice temperature immediately at drain contact, the conventional mobility fluctuation model, which assumes diffusive transport, can no longer be applied. In our near-ballistic InGaAs GAA MOSFETs, electrons encounter less scattering at smaller Lch during transport from source to drain. Therefore, scattering induced mobility fluctuation decreases at small Lch so that normalized Is noise is reduced at small Lch. This further confirms that mobility fluctuation is the origin of low-frequency noise for highly scaled InGaAs MOSFETs. Fig. 13 shows the relation between SIs/Is

2 and Vds at Vgs=0V. Smaller normalized Is noise is obtained at high Vds because ballistic efficiency is higher at high Vds than low Vds. Fig. 14 shows the thermo-reflectance image of an InGaAs GAA MOSFET with Lch=80 nm, WNW=30 nm at Vgs=1 V. The drain side is heated at high Vds by ballistic electrons, indicating that electrons travel substantial distance into the contact before reaching equilibrium with the lattice. This supports the conclusion of Fig. 13 that InGaAs GAA MOSFETs in this work are near-ballistic. Hot Carrier Injection measurement also confirms the near-ballistic transport in the devices as we reported in [15]. Fig. 15 shows the relation between normalized Is noise with WNW. SIs/Is

2

shows weak dependence on WNW. Figs. 16-21 show the property of RTN in the same condition as in Fig. 6 from Vgs=-0.15V to 0V. Capture/emission time constants (τc/τe) are extracted and τc/τe distributions exactly follow Poisson distribution as predicted theoretically, as shown in Fig. 16. Fig. 17 shows the relation between τc, τe and Vgs. Fig. 17 studies the relation between τc/τe and Vgs. The positive correlation between τc/τe and Vgs indicates that electrons trapping and de-trapping occur between channel and gate oxide, as suggested in Ref. [10]. Fig. 19 shows the relation between time constants and the reciprocal of temperature (1000/T). τc and τe are extracted at 15oC, 30oC and 45oC and the activation energy (Ea) is also extracted. Fig. 21 shows the Is histogram at different Vgs. A single peak at both low Vgs and high Vgs are obtained. Between -0.15V to 0.05V, double peaks are observed indicating the existence of RTN. At low Vgs, it is hard to observe the RTN signal because τe is longer than the measurement time. At high Vgs, RTN is negligible comparing with noise induced by mobility fluctuation because carrier number fluctuation induced noise drops faster than mobility induced noise with Is increases. ∆Id and ∆Id/Id

relation with different Vgs of RTN signals is shown in Fig. 20, which confirms RTN signals are hard to be observed at high Vgs. Two-trap RTN signals are also observed on some of the devices, as shown in Fig. 22.

Conclusion

For highly scaled InGaAs GAA MOSFETs, mobility fluctuation is the source of low-frequency noise, showing 1/f characteristics. Low-frequency noise is suppressed at shorter channel length due to the near-ballistic transport at deep sub-100nm. RTN is for the first time observed on top-down InGaAs GAA MOSFETs only around threshold voltage because RTN is negligible compared to mobility fluctuation induced noise at high Vgs.

Acknowledgement

The authors would like to thank X. W. Wang, X. Lou, R. G. Gordon for the valuable discussions and technical supports. The work is partly supported by AFOSR Task project.

Reference

[1] J. A. del Alamo, "Nanometre-scale electronics with III-V compound semiconductors." Nature 479, 317-323, (2011). [2] J. J. Gu et. al., “20–80nm Channel length InGaAs gate-all-around nanowire MOSFETs with EOT= 1.2 nm and lowest SS= 63mV/dec”, IEDM Tech. Dig. 633 (2012). [3] P. Ren et al., "New observations on complex RTN in scaled high-κ/metal-gate MOSFETs — The role of defect coupling under DC/AC condition", IEDM Tech. Dig. 778 (2013). [4] H. Miki et al., "Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs ", IEDM Tech. Dig. 450 (2012). [5] N. Tega et al., "Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nm," VLSI Tech. Dig. 50 (2009). [6] T. Grasser et al., "The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps," Electron Devices, IEEE Transactions on, 58, 3652 (2011). [7] J. P. Campbell et al., "Random telegraph noise in highly scaled nMOSFETs," Reliability Physics Symposium, IEEE International, 382 (2009) [8] W. Feng et al., "Fundamental origin of excellent low-noise property in 3D Si-MOSFETs ∼ Impact of charge-centroid in the channel due to quantum effect on 1/f noise", IEDM Tech. Dig. 630 (2011). [9] J. Chen et al., "Experimental study of channel doping concentration impacts on random telegraph signal noise and successful noise suppression by strain induced mobility enhancement", VLSI Tech. Dig. 184 (2013). [10] T. Nagumo et al., "Statistical characterization of trap position, energy, amplitude and time constants by RTN measurement of multiple individual traps", IEDM Tech. Dig. 628 (2010). [11] J. Salfi et al., "Direct observation of single-charge-detection capability of nanowire field-effect transistors", Nature Nanotechnology, 5(10), 737-741 (2010). [12] J. Salfi et al., "Probing the gate−voltage-dependent surface potential of individual InAs nanowires using random telegraph signals", ACS Nano, 5(3), 2191-2199 (2010). [13] G. Holloway et al., "Trapped charge dynamics in InAs nanowires", Journal of Applied Physics, 113(2), 024511 (2013). [14] S. H. Shin et al. "Impact of Nanowire Variability on Performance and Reliability of Gate-all-around III-V MOSFETs", IEDM Tech. Dig. 188 (2013). [15] S. H. Shin et al., "Origin and Implications of Hot Carrier Degradation of Gate-all-around nanowire III-V MOSFETs," Reliability Physics Symposium, IEEE International, 978 (2014).

20.1.2IEDM14-503

101 102 103 10410-3

10-2

10-1

Lch = 80nmWNW=20nm

ΔVT ~ t0.15-0.18

Sample A (Vgs=0.6V) Sample A (Vgs=0.8V) Sample B (Vgs=0.6V) Sample B (Vgs=0.8V)

ΔVT (

V)

Stress Time (s)

InP Substratei-InAlAs etch stop80 nm i-InP

30 nm i-InGaAs30 nm InGaAs (implanted)

(a) (b)MBE Growth

S/D implantation (20keV 1×1014cm-2)

Dopant activation (600°C 15s in N2)

Fin ICP etch (BCl3/Ar)

HCl:H2O (1:2) nanowire release

10% (NH4)2S 10min passivation

ALD High-K dielectric

ALD gate metal (WN 40nm)

WN gate etch (CF4/Ar)

Au/Ge/Ni S/D contact

Ni/Au test pad deposition

WNW

A

A’

A A’

TNW WN10nm In0.65Ga0.35As/10nm In0.53Ga0.47As/10nm In0.65Ga0.35AsHigh-K Dielectric

Fig. 1 (a) Schematic diagram, cross-section view and (b) fabrication process of an InGaAs GAA MOSFET.

Table 1 Description of samples and device dimensions used in this work.

Fig. 2 Noise characterization setup diagram.

1.6 1.7 1.8 1.9

1.6

1.7

1.8

1.9

1.6 1.7 1.80

1000

2000

3000

4000

5000

6000

Cou

nt

Is (μA)

Vgs = -0.025V

Sample CLch = 20nmWNW=20nm T = 15°C

(b)(a)

I s (t=

i+1)

(μA

)

Is (t=i) (μA)10-1 100 101 102

10-7

10-6

10-5

10-4

10-3

1/f 2

Noise spectrum@Vgs = -0.025V

S Is/I2 s (

1/H

z)

Frequency (Hz)

1/f

0.0 0.2 0.4 0.6 0.80

200

400

600

800Vgs = 0~0.8V in 0.05V stepVT = 0.13VSample ALch = 20nmWNW=20nm

I s (μA

/μm

)

Vds (V)0.0 0.2 0.4 0.6 0.8

10-2

10-1

100

101

102

103

Vds = 0.05V

Vds=0.5V

Vds=1V

SS (Vds=0.05V) = 75mV/decSS (Vds=0.5V) = 88mV/decDIBL = 35mV/V

Sample ALch = 20nmWNW=20nm

I s (μA

/μm

)

Vgs (V)Fig. 4 Transfer characteristics of the same device shown in Fig. 3.

Fig. 3 Output characteristics of a 20nm Lch GAA MOSFET with Al2/O3/LaAlO3 gate dielectric (Sample A, EOT=1.2nm) and WNW=20nm. Is is used due to relatively large junction leakage current in Id.

2.5 3.0 3.5 4.0 4.51.6

1.7

1.8

2.5 3.0 3.5 4.0 4.50.7

0.8

0.9Vgs = -0.075V(b)

(a)

I s (μA

)

time (s)

τc

τe

Vgs = -0.025V

VT = -0.1V

T=15°C

Sample CLch = 20nmWNW=20nm

I s (μA

)

time (s)

Fig. 5 Time evolution of ΔVT in PBTI (0-104s) under stress of 0.6V and 0.8V for Sample A and Sample B devices with Lch=80nm and WNW=20nm.

Sample A(Al2O3 first)

Sample B(LaAlO3 first)

Sample C(Al2O3 only)

Channel Material

10 nm In0.65Ga0.35As/10 nm In0.53Ga0.47As/10 nm In0.65Ga0.35As

10 nm In0.65Ga0.35As/10 nm In0.53Ga0.47As/10 nm In0.65Ga0.35As

10 nm In0.65Ga0.35As/10 nm In0.53Ga0.47As/10 nm In0.65Ga0.35As

Lch (nm) 20 20,30,50,80 20

WNW (nm) 20 20,25,30,35 20

TNW (nm) 30 30 30

Gate oxide0.5nm Al2O3/4nm LaAlO3

4nm LaAlO3/0.5nm Al2O3

3.5nm Al2O3

EOT (nm) 1.2 1.2 1.7

Fig. 7 (a) Histogram and (b) lag plot of a typical RTN signal shown in Fig. 6(a). The histogram and lag plot show two RTN levels.

Fig. 10 (a) Histogram of a RTN signal of sample B with Lch=20nm and WNW=25nm. (b) and (c) RTN signals in time domain of the same signal as (a). (c) is a time segment inside (b).

Fig. 6 Is fluctuation due to RTN in (a) Vgs=-0.025 V, (b) Vgs=-0.075 V on InGaAs GAA MOSFETs measured at 15oC.

0.00 0.05 0.10 0.15 0.200.36

0.38

0.40

0.42-0.5 0.0 0.5 1.0 1.5 2.0 2.5

0.36

0.38

0.40

0.42

0.37 0.38 0.39 0.400

1000

2000

3000

4000

low frequency noiseby mobility fluctuation

Cou

nt

Is (μA)

Vgs = 0.05V

RTN

I s (μA

)

time (s)

Sample B

(c)

(b)(a)

Lch = 20nmWNW=25nm

I s (μA

)

time (s)

Fig. 8 Normalized Is noise of RTN signal shown in Fig. 6(a), showing 1/f2 characteristics.

10-1 100 101 102 103

10-9

10-8

10-7

10-6

10-5

10-4

Vgs = 0.05V

Lch = 20nmWNW=25nm Sample B

Mobility Fluctuation only

S Is/I2 s (

1/H

z)

Frequency (Hz)

1/f

RTN+Mobility Fluctuation

10-7 10-6 10-5 10-4

10-8

10-7

10-6

10-5

Sample A Sample B Sample C

S Is/I2 s (

1/H

z)

Is (A)

f = 10HzLch = 20nmWNW=20nm

Gate oxide plays a minor role!

Fig. 9 Normalized Is noise of Sample B devices with RTN signal and without RTN signal. Noise spectrum of device without RTN is attributed to mobility fluctuation.

Fig. 11 Normalized Is noise at f=10 Hz for Sample A, B and C devices with Lch=20 nm and WNW=20 nm. Devices with different gate oxides exhibit similar noise level showing weakly dependent on interfaces.

20.1.3 IEDM14-504

20 40 60 80 10010-8

10-7

10-6

10-5

1/Lch

S Is/I2 s (

1/H

z)

Lch (nm)

Vgs = 0.2V Vgs = 0.3V

Sample B

f = 10HzWNW=20nm

Fig. 13 Normalized Is noise as a function of Vds. Normalized Is noise is reduced at high Vds due to the increasing ballistic efficiency at high Vds.

-60 -40 -20 0 20 400.20

0.22

0.24

-0.4 -0.2 0.0 0.2 0.4

0.21

0.22

0.23

-0.52 -0.51 -0.50 -0.49 -0.48

0.21

0.22

0.23 Fast Trap

I s (μA

)

time (s)

Slow Trap

Three Is levelsindicate 2 traps

Vgs = 0.075VLch = 50nmWNW=30nmI s (

μA)

time (s)

I s (μA

)

time (s)

0.0 0.2 0.4 0.6 0.8 1.00.5

1.0

1.5

S Is/I2 s (

1/H

z)

Vds (V)

f = 10HzVgs = 0VLch = 20nm

Sample B×10-6

0.058 0.060 0.062 0.0640

2000

4000

Cou

nt

Id (μA)

Vgs = -0.2V

0.4 0.5 0.60

2000

4000

6000

8000

Id (μA)

Vgs = -0.1V

1.6 1.7 1.80

2000

4000

6000

Id (μA)

Vgs = -0.025V

2.3 2.4 2.50

2000

4000

Cou

nt

Id (μA)

Vgs = 0V

3.0 3.1 3.20

1000

2000

3000

Id (μA)

Vgs = 0.025V

3.8 3.9 4.00

1000

2000

3000

Sample CLch = 20nmWNW=20nm

Id (μA)

Vgs = 0.05V

-0.15 -0.10 -0.05 0.0010-2

10-1

100

101

Sample CLch = 20nmWNW=20nm

τ e,τc (

s)

Vgs (V)

τc (s) τe (s)

T = 15°C

3.2 3.4

10-2

10-1

3.2 3.4

10-1

100

101

Ea=198mV

Ea=194mV

Ea=242mV

Ea=202mV

Ea=196mV

τ c (s)

1000/T (K-1)

Vgs=-0.125 V Vgs=-0.075 V Vgs=-0.025 V

Ea=152mVSample CLch = 20nmWNW=20nm

(b)(a)

T=15°C, 30°C, 45°C

Vgs=-0.125 V Vgs=-0.075 V Vgs=-0.025 V

τ e (s)

1000/T (K-1)-0.12 -0.08 -0.04 0.00 0.04 0.08

0.04

0.06

0.08

0.10

0.12

0.14

ΔIs (

μA)

Vgs (V)

ΔIs of RTN

0

5

10

15

20

25

Sample CLch = 20nmWNW=20nm T = 15°C

ΔIs/Is of RTN

ΔIs/I

s (%

)

Fig. 22 RTN with 2 level trap response measured on Sample B at Lch=50 nm, WNW=30 nm and Vgs=0.075 V. (a) RTN signal in 100 s time length. A slow trap with τe~3 s can be observed. (b) and (c) show the RTN signals in 1s and 0.04 s time length. A fast trap with τc=10 ms is observed.

Fig. 16 Distribution of (a) capture and (b) emission time constant of RTN signal shown in Fig. 4.

0.1 0.2 0.3 0.4 0.50

40

80

120

(b)(a)

τc = 0.072sC

ount

τc (s)

τc count

Sample CLch = 20nmWNW=20nm

~ A×exp(-t/τc)

Vgs = -0.025V T = 15°C

0.4 0.8 1.2 1.60

40

80

120

Cou

nt

τe (s)

τe count

τe = 0.2s ~ A×exp(-t/τe)

Fig. 19 Temperature dependent (a) capture and (b) emission time constant of RTN in device shown in Fig. 4.

Fig. 20 ∆Is and ∆Is/Is relation with different Vgs of RTN signals shown in Fig. 6.

Fig. 17 Mean capture and emission time constant corresponding to different gate voltages.

Fig. 21 Relation between Is histogram and Vgs of RTN signals shown in Fig. 4. RTN signals are observed around VT in most of devices of Samples A, B and C. This characteristic confirms that carrier number fluctuation induced Is fluctuation is negligible under high Vgs and mobility fluctuation is the dominant noise source at on-state.

Fig. 15 WNW dependence of normalized Is noise at f=10 Hz and Lch=20, 50 nm for Sample B. Normalized Is noise shows weak WNW dependence.

Fig. 12 Scaling metrics of normalized Is noise at f=10 Hz and WNW=20 nm for Sample B. Normalized Is noise reduces as Lch scaling down which is opposite to the conventional 1/Lch scaling, indicating near-ballistic transport at small Lch.

Fig. 14 Thermo-reflectance image on an InGaAs GAA MOSFET with Lch=80 nm, WNW=30 nm at Vgs=1 V. The drain side is heated far beyond the end of channel at high Vds, which clearly indicates near-ballistic transport.

20 25 30 3510-8

10-7

10-6

10-5

f = 10HzVgs = 0.3V

Sample B Lch =20nm Lch =50nm

S Is/I2 s (

1/H

z)

WNW (nm)

Fig. 18 τc/τe dependence on Vgs. The positive correlation indicates electron trapping happens between channel and gate oxide.

-0.15 -0.10 -0.05 0.0010-3

10-2

10-1

100

τ c/τe

Vgs (V)

T = 15°C

Sample CLch = 20nmWNW=20nm

Vds=4V

Vds=2V

Vds=0V

Device Image

0 5 10 15

20.1.4IEDM14-505