IMPACT • NT • 1

2008 IMPACT Workshop

Faculty Presentation: Novel TechnologiesTsu-Jae King Liu, Nathan Cheung, Costas Spanos, EECS Dept.Eugene Haller, Materials Science and Engineering Dept.University of California at Berkeley

04/09/2008

IMPACT • NT • 2

Overview

Devices:– Assessment of non-classical MOSFET structures for reducing variability

Processes:– Investigation of advanced fabrication techniques for reducing variability– Characterization and modeling of dopant diffusion to allow for precise

control of doping profiles in nanoscale MOSFETs– Investigation of processes for integrating new channel materials and 3-

D engineering of channel strain to improve performance

Metrology:– Development of an optical metrology platform with Si wafer form factor

04/09/2008

IMPACT • NT • 3

Tri-Gate Bulk MOSFET Design for Improved Robustness to RDFChanghwan Shin, Xin Sun, Tsu-Jae King Liu

Motivation:– Random variability in transistor performance

has emerged as one of the major challenges for continued CMOS scaling.

– Line edge roughness (LER)– Random dopant fluctuations (RDF)

– Statistical variation in threshold voltage (VTH) due to RDF is expected to increase dramatically as gate lengths are scaled below 30nm.

Objective:– Investigate benefits of transistor structures for reducing variability

Approach:– Atomistic 3-D process and device simulations

Future Work:– Inclusion of gate LER effects

04/09/2008

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The Tri-Gate Bulk MOSFETM. Kito et al. (Toshiba Corp.), 2005 Symp. VLSI Technology

A tri-gate structure is readily achieved by slightly recessing the STI oxide (or by epitaxial growth) just prior to gate-stack formation

Superior electrostatic integrity is achieved with the tri-gate structure– Smaller S and DIBL

STI-induced mobility variations are reduced, due to elevated channel

XTEM images

•gate •gate

X. Sun et al. (UC Berkeley), to be published

Measured I-V

IMPACT • NT • 5

MOSFET with Discretized Doping Profiles

20nm

Cross-section along channel

(a)

Plan view

20nm

(b)

N+ N+

P-substrate

Isometric view20nm

Cross-section along channel

20nm

Cross-section along channel

(a)

Plan view

20nm

(a)

Plan view

20nm

(b)

N+ N+

P-substrate

Isometric view

(b)

N+ N+

P-substrate

Isometric view

(a) Cross-sectional views of tri-gate bulk MOSFET with discretized doping profiles(b) Isometric view of a tri-gate bulk MOSFET, showing the randomly placed dopant atoms

04/09/2008

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Simulated ID-VGS Curves (VDS = 0.1V)

VDS = 0.1 V

IDlin = 7.7 μA/20nmσ(VTH) = 50.5 mV<VTH> - VTH0 = - 94.2mV

Planar Bulk MOSFET

VDS = 0.1 V

IDlin = 12.5 μA/20nm

Tri-gate Bulk MOSFET

σ(VTH) = 35.4 mV<VTH> - VTH0 = - 75.8 mV

The sequence of random dopant placement and I-V simulation was iterated 200 times for each MOSFET structure, in order to obtain reliable VTH statistics.– The 20nm-gate-length planar and tri-gate bulk MOSFETs have identical

nominal retrograde-well and source/drain doping profiles.– Curves obtained for continuum doping profiles are shown for reference.

04/09/2008

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VTH Adjustment Approaches

04/09/2008

VTH of a tri-gate bulk MOSFET can be adjusted by tuning either the dose (Npeak) or the depth (TSi) of the retrograde well.– 200 atomistic simulations were run for each nominal design.

VTH tuning via TSi adjustment provides for less variation and trade-off in short-channel control.

0.1 0.2 0.3 0.420

25

30

35

40

45

50

55

60

<DIBL>= 76 mV/V

<DIBL>= 23 mV/V

TSi adjust, Npeak=2e19cm -3

Dose adjust, TSi=14nm<DIBL>: average DIBL in discrete domain

<DIBL>= 33 mV/V

<DIBL>= 50.5 mV/V

<DIBL>= 120 mV/V

sigm

a(V TH

) [m

V]

VTH,lin [V]

IMPACT • NT • 8

Impact of LER on Double-Gate FinFET VariabilityKedar Patel, Tsu-Jae King Liu, and Costas J. Spanos

2

( )x

A x e

α

ξρ⎛ ⎞

−⎜ ⎟⎝ ⎠=

Motivation:– Advanced transistor structures such as the FinFET

may be needed to eliminate RDF-induced variability.

Objective:– Examine the impact of LER on FinFET performance

Approach:– Model device parameters such as Vt, Ioff, and Idsat using LER descriptors:

Future Work:– AC simulation to include effects of overlap capacitance– Study of the impact of fin LER– Incorporate LER variability into generalized IC variability model

04/09/2008

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LER in a FinFET

F and B

Fin LER

h

+ =

F TB

Gate

L

h

Fin

fint

GateFin

T

Gate LER

fint

Top FET has a smooth channel surface but non-uniform Lg due to gate LER. Front FET and back FET can have rough channel surfaces due to fin LER, but relatively uniform Lg (dependent on the gate etch process).

04/09/2008

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Gate LER Impact on a FinFETDifferent Lg values, and misalignment between the FG and BG:

Li

Gate

Fin

(b) FinFET Top View

S D

<L>

1 2

3 4

FG

Body

BG

S D

(a) DG-FET Cross-section

Gate EtchProgression

LFG

LBG

1 2

3 4

(c) FinFET Unfolded View

tfin

h

h

Lfg and Lbg are determined by “sampling” the auto-correlated LER function along each edge of the gate electrode at the front and back surfaces of the fin

– Points 1-4 are determined by the fin width, since it determines the sampling distance.

Although the primary criterion for the choice of fin width (tfin) is SCE control, mitigation of gate LER effects to reduce variability may be an important secondary consideration.

04/09/2008

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Model Description

( )2 22 1 ( )offset LER A finx tσ σ ρ∆ = − =

The locations of points “1”, “3” and “4” relative to point “2” are random but related variables.

24 offset∆ ≡ ∆

ReferencePoint

12 fgL L≡34 bgL L≡

CD fg bgL L∆ ≡ −

fint

y

04/09/2008

2

( )x

A x e

α

ξρ⎛ ⎞

−⎜ ⎟⎝ ⎠=

Auto-correlation function fit,

x

2 4

13

S

D

2 2 3 2 ( )CD LER A finx tσ σ ρ∆ ⎡ ⎤= − =⎣ ⎦

For a resist-defined gate electrode,

For a spacer-defined gate electrode (when both lines are perfectly correlated), the variation is zero:

2 0CD

σ∆ =

IMPACT • NT • 12

Simulated Device ParametersTaken from ITRS (2005 ed.)• 32nm HP node

Parameter ValueVdd 0.9Vφm 4.7eVLg 13nmNB 1e15Ns/d 1e20tox 6ALfin (Type B) 5*Lg

Lsp 0.55*Lg

tfin 8.4nmtpoly 16nmσs/d 4nm/dec

Lfg

Lbg

ImplantBaseline +S/D Contact

Type “A”

Lfg

Lbg

PerfectlyAligned

Misaligned

Lfg

Lbg

S/DContact

ImplantBaseline

Type “B”

04/09/2008

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Simulation Results: Variability in Vt,sat

(a) (b)

0 0.5 1 1.5 2 2.5 3 3.50

2

4

6

8

10

12

14

16

18

20

σLWR [nm]

σV

t,sat

[mV

]

Resist-defined, ξ=10nm

tfin=8.4nm (ITRS)

tfin=10nm

0 10 20 30 40 500

2

4

6

8

10

12

14

16

18

20

ξ [nm]

σV

t,sat

[mV

]

Resist-defined, tfin=8.4nm

σLWR=0.5nm

σLWR=1.5nm

σLWR=3nm

(a) (b)

0 0.5 1 1.5 2 2.5 3 3.50

2

4

6

8

10

12

14

16

18

20

σLWR [nm]

σV

t,sat

[mV

]

Resist-defined, ξ=10nm

tfin=8.4nm (ITRS)

tfin=10nm

0 10 20 30 40 500

2

4

6

8

10

12

14

16

18

20

ξ [nm]

σV

t,sat

[mV

]

Resist-defined, tfin=8.4nm

σLWR=0.5nm

σLWR=1.5nm

σLWR=3nm

An increase in σLWR, an increase in tfin, or a decrease in ξ each result in greater variation in the offset between the FG and BG (∆offset) hence the effective channel length; thus, variation in the threshold voltage increases due to SCE. Note that Vt,sat variation is less than 10mV for 1nm σLWR, which should be acceptable. (The ITRS roadmap calls for 0.52nm σLWR.)

Variability trends for Id,sat and log10(Ioff) are consistent with the trends observed here

04/09/2008

IMPACT • NT • 14

Spacer-Defined vs. Resist-Defined Gate

(a) (b)

0 0.5 1 1.5 2 2.5 3 3.50

2

4

6

8

10

12

14

16

18

20

σLWR [nm]

σV

t,sat

[mV

]

tfin=8.4nm (ITRS), ξ=10nm

ResistSpacer

0 10 20 30 40 500

2

4

6

8

10

12

14

16

18

20

ξ [nm]σ

Vt,s

at [m

V]

tfin=8.4nm, σLWR=1.5nm

ResistSpacer

(a) (b)

0 0.5 1 1.5 2 2.5 3 3.50

2

4

6

8

10

12

14

16

18

20

σLWR [nm]

σV

t,sat

[mV

]

tfin=8.4nm (ITRS), ξ=10nm

ResistSpacer

0 10 20 30 40 500

2

4

6

8

10

12

14

16

18

20

ξ [nm]σ

Vt,s

at [m

V]

tfin=8.4nm, σLWR=1.5nm

ResistSpacer

Variability is dramatically lowered when the gate electrode is spacer-defined.Since Lg is invariant with LER for a spacer-defined gate electrode, these results suggest that a CD mismatch contributes more to variability in performance than an offset between the FG and BG.

04/09/2008

IMPACT • NT • 15

Dopant and Self-Diffusion Studies in Isotopically Controlled Ge & SiGeChris Liao and Eugene Haller in collaboration with Prof. H. Bracht, Univ. of Münster

Motivation:– Si1-xGex and Ge will be used in future CMOS technologies– Equilibrium diffusion and non-equilibrium diffusion

related effects are not well understood in Si1-xGex & Ge – Fabrication of Ge n-MOSFETs is difficult due to enhanced dopant diffusion

and low active dopant concentration .

Objective:– Characterize and model dopant diffusion and activation in Si1-xGex and Ge

Approach:– Study dopant and self diffusion in Ge, using isotopically controlled structures

– P, As, and Sb; B with possible TED effect– carbon-related retardation of dopant diffusion

– Study dopant and self diffusion in relaxed Si1-xGex, using isotopically controlled structures

– As diffusion in Si0.95Ge0.05

04/09/2008

IMPACT • NT • 16

As Diffusion in Ge

vacancy mechanism:

1016

1017

1018

0 10 20 30 40depth (µm)

conc

entr a

t ion

ofAs

( cm

-3) 680°C, 3d

730°C, 3d770°C, 4d820°C, 100min868°C, 300min920°C, 180min

1016

1017

1018

1019

1020

0 25 50 75 100depth (µm)

conc

ent ra

t ion

o fAs

(cm

- 3) 640°C, 19d

680°C, 90h730°C, 2d770°C, 2d820°C, 100min868°C, 150min

n: free electron concentration ni:intrinsic carrier concentration

eqAs

AsVeqAsV

AsVAsi

iAsAs

sC

DCDD

nnnDD

+

−−

− ==⎟⎟⎠

⎞⎜⎜⎝

⎛= )()(*

)(

2

with )(−+− +↔ 2

s VAs)AsV(

H. Bracht and S. Brotzmann, Materials Science in Semiconductor Processing 9, 471, (2006)

04/09/2008

IMPACT • NT • 17

P and Sb Diffusion in GeGe:P Ge:Sb

1015

1016

1017

1018

1019

0 30 60 90depth (µm)

conc

entra

t ion

o fS b

( cm

- 3) 600°C, 18d

700°C, 3d750°C, 3d900°C, 4h

1016

1017

1018

1019

0 20 40 60depth (µm)

conc

ent ra

t ion

ofP

(cm

-3)

820°C, 7d845°C, 164h870°C, 70h895°C, 1d920°C, 20h920°C, 6h

04/09/2008S. Brotzmann, H.Bracht, JAP 103, 033508 (2008)

−+− +↔ 2s VX)XV(

eqX

)XV(eq

)XV(*)XV(X

2

iiXX

sC

DCDD with

nn)n(DD

+

−−

− ==⎟⎟⎠

⎞⎜⎜⎝

⎛=

{ }Sb,As,PX∈

n: free electron concentrationni: intrinsic carrier concentration

vacancy mechanism:

IMPACT • NT • 18

As and Ge Self-Diffusion: Effect of C

1017

1019

1021

1023

0 500 1000 1500 2000

75As12C

74Ge

depth (nm)

conc

entra

tion

(cm

-3)

700°C, 15 min

1017

1019

1021

1023

0 500 1000 1500 2000

74Ge

75As in natGe/70Ge ...

75As in natGe

depth (nm)

conc

entra

tion

(cm

-3)

700°C, 15 min

segregation of As in the 70Ge layers

retarded As diffusion

As diffusion is retarded by carbon 04/09/2008

IMPACT • NT • 19

Simultaneous Dopant and Self-Diffusion in Ge

vacancy mechanism reaction with carbon

reaction with dopant X 02s

00

2s

)VX(X)XV(eCVXC)XV(

VX)XV(

↔+

+↔+

+↔

+−

−−

−+−

{ }Sb,As,PX∈

1020

1021

1022

0 500 1000 1500

best fit with V2-73Ge

depth (nm)

conc

entra

tion

(cm

-3)

1017

1019

1021

1023

0 500 1000 1500 2000

simulationsimulation

74Ge

75As in natGe/70Ge ...

75As in natGe

depth (nm)

conc

entra

tion

(cm

-3)

700°C, 15 min

04/09/2008

IMPACT • NT • 20

Future WorkDiffusion in strained isotopically enriched silicon-germanium layers:– This structure will be used to study the effects of strain on dopant and self

diffusion in Si1-xGex

– By varying x and y, compressive or tensile strains can be introduced

Si substrate

SiGe graded buffer layer100 nm nat. Si1-yGey

100 nm nat. Si1-yGey

200 nm 28Si1-x70Gex

04/09/2008

IMPACT • NT • 21

2008 IMPACT Workshop

Your Photo Here

Faculty Presentation: Novel Technologies

Laminated Si/Ge Substrates for 3D Strain ControlProf. Nathan Cheung, EECS, UC Berkeley

04/09/2008

IMPACT • NT • 22

Current Milestones

SOI and GeOI layer transfer demonstrated

Carrier mobility, fixed charge density, and interface trap density of GeOI improved by forming gas annealingEpi-Ge layer transferRemoval of implanted hydrogen essential to extend thermal stability of GeOI to 700 ℃ and above

550°C annealedGeOIafter CMP

As thermal-cutGeOI 550°C annealed GeOI

180nm Ge

(after CMP)As thermal-cutGeOI

BOXBOX

04/09/2008

IMPACT • NT • 23

State-of-the-art GeOI results

400 500 6000.1

1

10

100

Slow ramp Fast ramp

Qf (

1010

q/cm

2 )

T(oC)

Qf

Pseudo-MO

SFET fails w

hen T>600 ℃

400 500 6000

100

200

300

400

500 µpB (Slow ramp) µpB (Fast ramp)

Mob

ility

(cm

2 /Vs

)

T (oC)

Bulk

GeOI data after forming gas annealing

Pseudo-MO

SFET fails w

hen T>600 ℃

Interface fixed charge density, Qf ~1010 q/cm2

Interface trap density,Qit ~1010 q/cm2

Interface hole mobility, µpl 420 cm2/V-secInterface electron mobility, µnl 190 cm2/V-sec

Bulk hole mobility, µpB 500 cm2/V-sec (2X of Si)

•Jin and Cheung, EDL and TED (2008)04/09/2008

IMPACT • NT • 24

Possible reason of degradation : residual HGe

Oxide

Si substrate

750 ℃ 60s

tGe ~ 300nm

750 ℃ 60s 750 ℃ 60s

tGe ~ 200nm

Bubble size increases with annealing temperatureTransfer thickness is larger than cutting depth

Ge bubble size decreases when GeOI is thinned by RIE before annealing04/09/2008

IMPACT • NT • 25

Epi-Ge as the donor wafer for layer transfer

04/09/2008

AFM image shows terrace steps on Epi-Ge wafer Non-ideal wafer bonding using Epi-Ge

A 250 ℃ 3 days B 250 ℃ 7 days

2cm4cm

GeOI GeOI

Longer annealing time exhibits larger area layer transfer result

IMPACT • NT • 26

In progress : CMP Epi-Ge before bonding

200nm 200nm

CMP

SEM images of GeOI surface before and after CMP

04/09/2008

The RMS of GeOI substrates can be smoothed down to 0.3nmSame CMP recipe can be used to smooth Epi-Ge surface

AFM images of GeOI surface before and after CMP

IMPACT • NT • 27

In Progress: Buried stress film (BSF) to strain channelBuried stress film (BSF) to strain channel

09/06/2007

(1) 1000 (1) 1000 ℃ annealing increase 0.5GPa stress in silicon channel (σ ∝ ∆T)

(2) For NMOS (Buried stress sheet orthogonal to S-D direction), increase 0.2-0.4GPa compressive stress in channel

(3) For PMOS (Buried stress sheet parallel to S-D direction), increase 1GPa compressive stress in channel and the mobility increase 50%

Buried uniaxial stress sheet formed

Ge/Si layer transferred

1000 ℃ thermal expansion

NMOS and PMOS fabrication

Stress sheet

Stress sheet

Com

pres

sive

she

et

Stress sheet

High-K dielectric

IMPACT • NT • 28

Future Milestones

Increase GeOI substrate electrically stability up to 700-900 CImprove Epi-Ge bonding by CMP Epi-Ge surface Form buried stress sheet structure to induce strain in Ge film Prototype GeOI MOSFET with buried stress sheet

04/09/2008

IMPACT • NT • 29

2008 IMPACT Workshop

Your Photo Here

Faculty Presentation: Novel Technologies

Optical Metrology Wafer with Si Wafer Form-FactorProf. Nathan Cheung, EECS, UC Berkeley

04/09/2008

IMPACT • NT • 30

Current Milestones

Zero Footprint Metrology Wafer Data Acquisition System

Design and prototyping of refractive index optical stack with spectroscopy capability

Si3N4, SiO2 Stack

Cavity

Optical Window

several mm

Bulk Silicon WaferWhite PhosphorLED* PD Array*

Photo/RF Transmitter*

Molecules

Multilayer Diffraction Stack

*Internal Power Source Not Shown

04/09/2008

IMPACT • NT • 31

Metrology Wafer Prototype with DAQ*DAQ provided by KLA Tencor

LEFT: Topside of metrology wafer. Cell powered on (see blue LED, center).

RIGHT: Backside of metrology wafer. DAQ, current limiting resistors, thin Lithium-Polymerbattery, and power switch shown. Components on backside for flexibility in testing components.

No External Connectors! Self contained for in-situ real time acquisition.

04/09/2008

IMPACT • NT • 32

Data Acquisition in ActionCopper End-Point Etch Detection: 200 nm Cu etched by CR-7 (perchloric based, Cyantek).

DAQ output = k*(photodiode current)

Need to increase sample rate above 1 Hz.

Module Temperature

2021222324252627282930

0 10 20 30

Time, [s]

Tem

pera

ture

, [C

]

Supply Voltage

0

0.5

11.5

2

2.5

33.5

4

4.5

0 10 20 30

Time, [s]Su

pply

Vol

tage

, [V]

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

40 50 60 70 80 90 100 110 120

Time, [s]

Ref

lect

ance

, [a.

u.]

200 nm Cu

Begin of etch, 50 nm

End of etch, 0 nm

04/09/2008

IMPACT • NT • 33

First Order Design: Optical Raytracing

0

5000

10000

15000

200000 210000 220000 230000 240000 250000 260000 270000 280000

X Position, [nm]

Z Po

sitio

n, [n

m]

467.815 nm508.582 nm706.52 nm

Optical Raytracing

45o Mirror (Metal)Light inMultilayer thin-film stack

~few um thick

Photodiode array

Slit

Lateral length can be on the mm scale

zx 1x

0

5000

277000 278000 279000 280000 281000 282000 283000 284000 285000

10 nm resolution for

12 um commercial CCD detector pixel after ~12 mm of lateral travel

04/09/2008

IMPACT • NT • 34

Spectroscopy Applications

Combine established interference capability with the proposed spectroscopy capability to extract key parameters for reaction rate modeling.

With addition of the proposed spectroscopy capability, interfacechemical kinetics and precursor identification can be measured which enables quantitative reaction rate modeling.

Molecular Fluorescence Spectroscopy (MFS) Precursor Identification Interface Chemical Kinetics

Reaction Rate Modeling

DepositionWet and Dry Etching

Resist Development

04/09/2008

IMPACT • NT • 35 04/09/2008

Future Milestones

Fabricate dispersion stack and verify

Prototype spectroscopy capability into Si wafer form factor– Encapsulate DAQ– Design and implement optical switch– Hybrid integration of power source and resistors.