2005ACDL016

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IEICE TRANS. ELECTRON., VOL.E89–C, NO.6 JUNE 20061

LETTER Special Section on Analog Circuit and Device Technologies

Design of Analog Current-Mode Loser-Take-All Circuit

Mohsen ASLONI†a), Student Member , Abdollah KHOEI†b),

and Khayrollah HADIDI†c), Members

SUMMARY A CMOS circuit is proposed which takes multi-ple analog input currents and extracts minimum input current atthe output. It is very fast and requires no subtraction from theconstant current source. It exhibits O(N) complexity and usesonly 4×N MOS transistors where N is the number of system in-puts. This circuit consumes very little power and very small area.The substrate bias affects the threshold voltage of transistors andimproves performance of the structure.key words: loser-take-all, winner-take-all

1. Introduction

One of the principal parts of computational systemssuch as fuzzy controllers and neural networks is infer-ence engine which consists of the Min and Max cir-cuits [4],[5],[7],[8],[9]. These circuits use the loser-take-all (LTA) and winner-take-all (WTA) structures. Since1988 in which lazzaro[6] presented the report on WTAstructures, a lot of WTA and closely related LTA cir-

cuits have been proposed[1],[3] . Some of the proposedarchitectures use winner-take-all to compute loser-take-all function by subtracting input values from a fixed ref-erence current. The scheme of this structure is shownin Fig. 1. One of these circuits uses subtraction froma fixed current and then selection of maximum currentperforms as a minimum current selector[2]. The analogsubtraction implies loss of accuracy and limits the in-put current to the value of a fixed reference, moreover itneeds large number of MOS transistors, which increasespower consumption. There are two types of the struc-tures which have O(N) and O(N2), respectively. Thesystems with O(N2) occupy more area and consumehigh power because they grow quadratically with num-ber of the input currents. Also, due to many devicesbetween minimum input and output stage, the circuitprecision decreases. On the other hand, structures withO(N) complexity grow linearly with the number of in-put currents. This paper presents a new structure withO(N) complexity which decreases the occupied area andpower consumption. It does not need any subtraction

Manuscript received November 2, 2005.Manuscript revised January 15, 2006.†The authors are with the Microelectronic Research

Laboratory, Department of Electrical Engineering, Urmia

University,Urmia57159, Irana) E-mail: st−[email protected]) E-mail: [email protected]) E-mail: [email protected]

of currents, hence precision of the circuit is preserved.This structure also uses the body effect of transistorsand improves the performance of the proposed circuit.

Fig. 1 LTA network using WTA network

Section 2 presents the proposed circuit architectureand describes its operation. Calculations are done insection 3. The analysis of accuracy is given in section4 and analysis of substrate bias is presented in section5 and simulation results on the proposed circuit are insection 6. Section 7 concludes this paper.

2. Circuit Description

The function of loser-take-all structure is defined byrelation (1).

f (I 1, I 2,...,I N ) = min(I 1, I 2,...,I N ) (1)

This function can be obtained with function of winner-take-all structure using (2).

f (I 1, I 2,...,I N ) = min(I 1, I 2,...,I N )

= I ref − max(I 1, I 2,...,I N ) (2)

The structure presented in this paper uses the first

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2IEICE TRANS. ELECTRON., VOL.E89–C, NO.6 JUNE 2006

Fig. 2 The schematic diagram of the proposed circuit

method which consumes less power and has better pre-cision. It comprises of input cells and output block.

The schematic diagram of the proposed circuit isshown in Fig. 2. There are N cells which correspond toN inputs of the structure. Every cell has 4 MOS tran-sistors as shown. Also, there is the output stage com-posed of two cascoded devices. The first input block is

different from the other input blocks because this blockproduces the bias voltage of the LTA circuit. It is as-sumed that the circuit has 2 inputs, for simplicity. Toanalyze this structure, the operation region of the cir-cuit is divided to 3 regions. In the first region, I2 ismore than I1. In the second region, I1 is more thanI2 and in the third region, I1 and I2 are the same. Inthe first region, since the bias voltage is identified byI1, and I2 is more than I1, M4 can not sink all I2. SoM4 only sinks I1 and (I2 - I1) is drawn by M6. In thesecond region, as I1 is more than I2 and the bias volt-ages of the circuit are identified by I1, then M2 and M4tend to work in triode region. For this reason, M

5 will

be on and (I1 - I2) is drawn by M5. So M2 stays insaturation region but M4 leaves saturation region andoperates in triode region. The third region is locatedbetween latter two regions. In this region, as I1 is thesame as I2 and the overdrive voltages of M1 and M2 arethe same, hence M5 and M6 are in cut-off region.

3. Principal Conditions

In this section, the conditions in which the circuit is op-erated, is shown. The sizes of M1 and M2 are the sameas well as M3 and M4. For simplicity, two parameters

are defined that are used in this paper:

k = 1

2µnC ox(

W

L ) (3)

∆V TD = |V TP | − V TN (4)

In the first region, M5 is off, as M4 is in saturation

region, thus:

I min

k4≤ ∆V TD (5)

There are three conditions in the second region. Forthe first condition, M5 is in saturation region and M4

is in triode region.

∆I

k5+ ∆V TD ≥

I min

k4(6)

For the second condition, M2 is in saturation re-gion.

V S 2 ≥ V S 1 − V TN (7)

Also it is obtained that:

V I 1 − V S 2 =

∆I

k5+ |V TP | (8)

Also:

V S 2 = V I 1 − {

∆I

k5

+|V TP

|} (9)

And:

V I 1 = V S 1 + {

I M 3

K 3+ V TN } (10)

Substituting (9) and (10) in (7), we obtain:

V S 1 + {

I M 3

k3+ V TN }

−{

∆I

K 5+ |V TP |} ≥ V S 1 − V TN (11)

Using k3 = k4 and substituting them in (11), we obtain:

I min

k4≥

∆I

k5+ ∆V TD − V TN 0 (12)

For the third condition, using this point that M4

is in triode region, we obtain:

I min

k4≤ |V TP | (13)

It is assumed that the range of the applied inputcurrents is restricted to IH . For obtaining the basic con-

dition, the current range of the circuit is substituted in(5), (6), (12) and (13). Now we calculate these bound-aries:

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LETTER3

3.1 Boundries’s Calculations

1. By substituting IMin = IH in (5), it is obtained: I H

k4≤ ∆V TD (14)

2. By substituting IMin= IH and ID=0 in (6), wehave:

I H

k4≤ ∆V TD (15)

3. By substituting IMin =0 and ID= IH in (12), it isresulted in:

I H k5

≤ V TN 0 − ∆V TD (16)

4. By substituting IMin =IH in (13), it is obtainedthat:

I H

k4≤ |V TP | (17)

From combination of above four conditions, we ob-tain the final equation for estimating the currentrange belonged to the input currents:

I H = min(k4∆V 2TD, k5(V TN 0 − ∆V TD)2) (18)

It is seen clearly that the range of the input cur-rents is dependent to k4, k5, ∆V TD and V TN 0 but itis known that two last parameters are not variablein CMOS processes, so only k4 and k5 are variable.However, we know that the bulk effect, affects on∆V TD .Now, we can increase the current range of inputs.

4. Error of The Circuit

Obtaining precise error in this structure and similarstructures is difficult. For this reason, the error of the

proposed circuit is estimated. The largest error in thisstructure is produced in the case of I 1 ≥ I 2 . WhenI 1 ≥ I 2 , because M1, M2 and M5 are in saturationregion, and drain to source voltages of M1 and M2 arenot the same, we have:

I out

I min

= I M 1

I M 2

= 1 + λV TN

1 + λ(V ds − V dssat.) (19)

In the worst case, we have:

V ds − V dssat. = 0 ⇒ I out

I min

= 1 + λV TN (20)

However, since M5 is in saturation region, it in-

hibits the drain to source voltage of M2 to drop to theboundary of saturation and triode region. Thus thisworst case does not occur.

5. The Substrate Bias Effect

When the voltage is applied to the bulk, it affects thethreshold voltage of a MOS transistor. The thresholddifference due to an applied source to the bulk voltageis expressed as:

∆V T = γ ( |2φF + V SB | −

2φF ) (21)

Where γ is the body effect parameter given by:

γ =

√ 2εsqN aC ox

(22)

So, we obtain by:

∆V TD ∼= γ 5 |2φF + |V SB5 ||

−γ 4 |2φF + V SB4

| (23)

Hence ∆V TD can be increased with bulk bias.Hence, according to (18) the range of input currentswill also increases, if the first term of (18) would besmaller than the second term.

6. Simulation Results

We simulated the circuit for 2 input and 3 input casesin 0.35µ process with 3.3 v power supply. Using (18),the range of input current obtained is about 0

∼ 20

µA. The sizes of MOS transistors for simulation of thecircuit are shown in Table 1. The results are shown inFig. 3 ,Fig. 4 ,Fig. 5 and Fig. 6 . In both cases, thecircuit is simulated for two ranges of input currents.

7. Conclusion

We presented a new CMOS structure for loser-take-allnetwork. It exhibits O(N) complexity and uses only

Table 1 The sizes of MOS transistors

M n W L M n W L

M 1 1µ 0.5µ M 4 1µ 0.5µM 2 1µ 0.5µ M 5 5µ 0.5µ

M 3 1µ 0.5µ M 6 3µ 0.5µ

Fig. 3 Simulation results for 2 input case circuit with currentrange of 4 ∼ 6 µA for I N 1 and I N 2

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4IEICE TRANS. ELECTRON., VOL.E89–C, NO.6 JUNE 2006

Fig. 4 Simulation results for 2 input case circuit with currentrange of 2 ∼ 8 µA for I N 1 and I N 2

Fig. 5 Simulation results for 3 input case circuit with currentrange of 4∼6 µA for I N 1 ,IN 2 and 2∼8 µA for I N 3

Fig. 6 Simulation results for 3 input case circuit with currentrange of 2∼8 µA for I N 1 ,IN 2 and IN 3

4×N MOSFETs. For this reason, the power consump-tion is low and occupied area is small, while it achieves

high speed operation. In fact, the main reason for itshigh speed and good precision is lack of any currentsubtraction. Notice that the currents all are unipolarand the related range is about 0 ∼ 20 µA .

References

[1] G.N. Patel and S.P. DeWeerth: ’Compact current-modeloser-take-all circuit’, Electron. Lett. , 23rd November 1995,31, (24), pp. 2091-2092

[2] I. Baturone, J.L. Huertas, A. Barriga and S. SanchezSolano: ’Current-mode multiple-input Max circuit’, Elec-tron. Lett. , 28th April 1994, 30,(9),pp. 678-680

[3] C. Y. Huang and B. D. Liu: ’Current-mode multiple input

maximum circuit for fuzzy logic controllers’, Electron. Lett.,10th November 1994,30,(23),pp. 1924-1925[4] C. J. Huang, C. Y. Wang, and B. D. Liu: ’Modular current-

mode multiple input minimum circuit for fuzzy logic con-

trollers’, Electron. Lett. , 6th June 1996, 32,(12), pp. 1067-1069

[5] N. Donckers, C. Dualibe and M. Verleysen: ’A Current-

mode CMOS Loser-Take-All with minimum function forneural computation’ , ISCAS 2000 - IEEE InternationalSymposium on Circuits and Systems, May 28-31, 2000,Geneva, Switzerland, pp. 415-418

[6] J. Lazzaro, S. Ryckebusch, M. A. Mahowald and C. A.Mead: ’Winner-take-all networks of O(n) complexity’ ,Ad-vances in neural information processing system, 1, D. S.Touretsky, Ed. Los Altos, CA: Morgan Kaufman,1989, pp.703-711

[7] M. Sasaki, T. Inoue, U. Shirai and F. Ueno: ’FuzzyMultiple-Input Maximum and Minimum Circuits in Cur-rent Mode and Their Analyses Using Bounded-DifferenceEquations’ , IEEE Transactions on computers, June 1990,Vol. 39, No. 6, pp. 768-774

[8] L. Lemaitre, M. J. Patyra and D. Mlynek: ’Analysis and

Design of CMOS Fuzzy Logic Controller in Current Mode’,IEEE Journal of Solid-State Circuits, March 1994, Vol 29,No. 3, pp. 317-322

[9] R. G. Carvajal, A. Torralba, R. Millan and L. G. Franquelo:’Automatic Synthesis of Analog and Mixed-Signal FuzzyControllers with Emphasis in Power Consumption’, ISCAS’99. Proceedings of the 1999 IEEE International Symposiumon Circuits and Systems, vol.5, pp. 571-574

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