2001/02/16TGC off-detector PDR1 Sector Logic Status Report Design Prototype-(-1) Prototype-0 Schedule 2001/02/16TGC off-detector PDR2 Sector Logic A Sector Logic Combines hit information of wires(R) and strips( ) from Hi-Pt modules to generate track candidates. Selects 2 highest Pt-tracks in each trigger sector and send them to MUCTPI Locates in USA15 2001/02/16TGC off-detector PDR3 Design A Sector Logic consists of Coincidence R - coincidence matrix EI/FI coincidence Track Selection Logic Pre-selector Track selector Decoder/Encoder Readout Block Design Choice Pipelined Logic LUT for R- Coincidence Using FPGA 2001/02/16TGC off-detector PDR4 Prototyping PT3(general-purpose logic board) [Purpose] Verify the functionality of Track Selection Logic. [Status] Done. June 2000) Prototype-(-1) [Purpose] Verify the functionality of R- coincidence. [Technology] Using SRAM or BlockRAM(FPGA internal). [Status] Done. (This report) Prototype-0 [Purpose] A part of total prototype test (Sep.2001~) [Function] Almost all of full spec. forward sector logic. [Status]Design 2001/02/16TGC off-detector PDR5 prototype-(-1) Purpose To check design of R- coincidence unit. SRAM version BlockRAM version Feature Xilinx XCV300(QFP, 2.5V) x2 4Mbit SRAM(15ns, IDT) x 4 XC95288XL-7PQ208C x1 32bit Ext I/O for observe signals 6U VME(A24D16) 5V on VME BUS 3.3V on board 2001/02/16TGC off-detector PDR6 R- Coincidence in SRAM Selects 1 track with Pt information in a Sub Sector Cluster SSC consists of 8 sub sectors witch corresponds to HPt logic in R: 1 candidate max. HPt logic in : 2 candidates max. All information puts into one big Fast SRAM and it returns 1 track information. Solve 2 hit inputs in at coincidence table at SRAM 2001/02/16TGC off-detector PDR7 R- Coincidence in SRAM Each SRAM covers 1 SSC It MHz max 2001/02/16TGC off-detector PDR8 R- Coincidence in FPGA Use Block RAM in Xilinx Virtex FPGA Xilinx Virtex-EM : Extended memory series XCV405E:560Kbit (4Kbit x 140) XCV812E: 1M bit (4Kbit x 280) [Solution] Divide SSC into 2 pieces Each piece inputs 1 candidate in R and , and returns 1 tracks. Each piece inputs 13bits max, and outputs 3bits(Pt information). Additional Pt Selector is required. 64k bit per SSC 2001/02/16TGC off-detector PDR9 R- Coincidence in FPGA XCV300 has 16 Block RAM (4Kbit) 1 SSC LUT is implemented in 4bit x 1K x 8 (half SSC) x 2 It MHz max 2001/02/16TGC off-detector PDR10 SRAM vs BlockRAM SRAMBlock RAM (Xilinx Virtex) Size 4MB560K / 1Mbit Access Speed 8-15 ns2-4 ns Latency 1 clock (asynchronous) 2 clock (read-thorugh synchronous) Availability sometimes badgood Flexibility in designing matrix goodsome constraint Configuration Download 2 step (FPGA+RAM) 1 step We chose Block RAM design for Prototype-0 2001/02/16TGC off-detector PDR11 prototype-0 Purpose For prototyping test system. Almost same functionality as forward sector logic Feature 9U VME (A32D32 ) 3 Virtex chip (BGA package) XCV400E (82KBit) XCV405E (560KBit) G-Link chips will be on a mezzanine board. No readout ASIC 2001/02/16TGC off-detector PDR12 Prototype-1 Feature 9U VME (VME64x ) 6U (or 3U) Transition Board G-Link chips on the transition board special connector for J3 3 Virtex chip (BGA package) XCV400E (82KBit) XCV405E (560KBit) Readout ASIC same as one for SLB Purpose Full functionality of forward sector logic 2001/02/16TGC off-detector PDR13 Schedule May 2001 Prototype-0 delivery Sep Full system test 1 st qtr Prototype-1