2 TSTE12 Design of Digital Systems Friendly reminder · when "0110" => GE

TSTE12 Design of Digital Systems Department of Electrical Engineering [email protected] Palmkvist Linköping University http://www.isy.liu.se/

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TSTE12 Design of Digital Systems

● Lecture 9– HDL based design


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Friendly reminder

● 1st handin deadline Monday 18/9 23:59 (today!)– New set published today Monday 25/9

– See handin webpage for info on how to access my test cases and simulation results (after deadline)

● Complete requirement specification● Project (incl. time) plan and design sketch

– Initial version deadline Tuesday 19/9

● Remember weekly meetings with transcript!


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Example of combinational logic● Binary comparison. Compare two two-bit words

– GE: Greater or equal

– LE: Less or equal

– E: Equal

– G: Greater

– L: Lessentity COM is generic (D:time); port (N1, N0, M1, M0: in BIT; GE, LE, E, G, L: out BIT);end COM;


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Descriptions

● ROM– Table lookup

use work.TRUTH4x5.all;architecture TABLE of COM isbegin process (N1,N0,M1,M0) variable INDEX: INTEGER; variable WOUT: WORD; begin INDEX := INTVAL (N1&N0&M1&M0); WOUT := TRUTH (INDEX); GE <= WOUT(4) after D; LE <= WOUT(3) after D; E <= WOUT(2) after D; G <= WOUT(1) after D; L <= WOUT(0) after D; end process;end TABLE;

package TRUTH4x5 is constant NUM_OUTPUTS: INTEGER:=5; constant NUM_INPUTS: INTEGER:=4; constant NUM_ROWS: INTEGER:= 2 ** NUM_INPUTS; type WORD is array(NUM_OUTPUTS-1 downto 0) of BIT; type ADDR is array(NUM_INPUTS-1 downto 0) of BIT; type MEM is array (0 to NUM_ROWS-1) of WORD; constant TRUTH: MEM := ("11100", "01001", "01001", "01001", "10010", "11100", "01001", "01001", "10010", "10010", "11100", "01001", "10010", "10010", "10010", "11100"); function INTVAL(VAL:ADDR) return INTEGER;end TRUTH4x5;

package body TRUTH4x5 is function INTVAL(VAL: ADDR) return INTEGER is variable SUM: INTEGER:=0; begin for N in VAL'LOW to VAL'HIGH loop if VAL(N) = '1' then SUM := SUM + (2 ** N); end if; end loop; return SUM; end INTVAL;end TRUTH4x5;

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Descriptions, CASE statementarchitecture MUX of COM isbegin process(N1,N0,M1,M0) begin case N1&N0&M1&M0 is when "0000" => GE <= '1' after D; LE <= '1' after D; E <= '1' after D; G <= '0' after D; L <= '0' after D; when "0001" => GE <= '0' after D; LE <= '1' after D; E <= '0' after D; G <= '0' after D; L <= '1' after D; when "0010" => GE <= '0' after D; LE <= '1' after D; E <= '0' after D; G <= '0' after D; L <= '1' after D; when "0011" => GE <= '0' after D; LE <= '1' after D; E <= '0' after D; G <= '0' after D; L <= '1' after D; when "0100" => GE <= '1' after D; LE <= '0' after D; E <= '0' after D; G <= '1' after D; L <= '0' after D; when "0101" => GE <= '1' after D; LE <= '1' after D; E <= '1' after D; G <= '0' after D; L <= '0' after D; when "0110" => GE <= '0' after D; LE <= '1' after D; E <= '0' after D; G <= '0' after D; L <= '1' after D; when "0111" => GE <= '0' after D; LE <= '1' after D; E <= '0' after D; G <= '0' after D; L <= '1' after D; when "1000" => GE <= '1' after D; LE <= '0' after D; E <= '0' after D; G <= '1' after D; L <= '0' after D; when "1001" => GE <= '1' after D; LE <= '0' after D; E <= '0' after D; G <= '1' after D; L <= '0' after D; when "1010" => GE <= '1' after D; LE <= '1' after D; E <= '1' after D; G <= '0' after D; L <= '0' after D;

when "1011" => GE <= '0' after D; LE <= '1' after D; E <= '0' after D; G <= '0' after D; L <= '1' after D; when "1100" => GE <= '1' after D; LE <= '0' after D; E <= '0' after D; G <= '1' after D; L <= '0' after D; when "1101" => GE <= '1' after D; LE <= '0' after D; E <= '0' after D; G <= '1' after D; L <= '0' after D; when "1110" => GE <= '1' after D; LE <= '0' after D; E <= '0' after D; G <= '1' after D; L <= '0' after D; when "1111" => GE <= '1' after D; LE <= '1' after D; E <= '1' after D; G <= '0' after D; L <= '0' after D; end case; end process;end MUX;


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Descriptions, improved CASE

● Remove one variablein the selection of the case statement

● Use the removedvariable as output value or its inverse

● More variables can be removed

architecture MUX3 of COM isbegin process (N1, N0, M1, M0) begin case N1&N0&M1 is when "000" => GE <= not M0 after D; LE <= '1' after D; E <= not M0 after D; G <= '0' after D; L <= M0 after D; when "001" => GE <= '0' after D; LE <= '1' after D; E <= '0' after D; G <= '0' after D; L <= '1' after D; when "010" => GE <= '1' after D; LE <= M0 after D; E <= M0 after D; G <= not M0 after D; L <= '0' after D; when "011" => GE <= '0' after D; LE <= '1' after D; E <= '0' after D; G <= '0' after D; L <= '1' after D; when "100" => GE <= '1' after D; LE <= '0' after D; E <= '0' after D; G <= '1' after D; L <= '0' after D; when "101" => GE <= not M0 after D; LE <= '1' after D; E <= not M0 after D; G <= '0' after D; L <= M0 after D; when "110" => GE <= '1' after D; LE <= '0' after D; E <= '0' after D; G <= '1' after D; L <= '0' after D; when "111" => GE <= '1' after D; LE <= M0 after D; E <= M0 after D; G <= not M0 after D; L <= '0' after D; end case; end process;end MUX3;


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Hardware, improved Case statement

● One mux plus inverter● Every output have its

own multiplexer(same as for non-improved case statement)


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Partitioning

● Rewrite expressions, sharing common subexpression– E= GE AND LE

– G = GE AND NOT LE

– L = LE AND NOT GE

● That is, two expressions followed by simple generation of E, G, and L

● Designer makes logic synthesis instead of tool– Synthesis tool may still modify description

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architecture POSDF of COM is signal Z1,Z0: BIT;begin Z1 <= (not N0 or M1 or M0) and (not N1 or M1) and (not N1 or not N0 or M0); Z0 <= (N1 or N0 or not M0) and (N1 or not M1) and (N0 or not M1 or not M0); LE <= Z1 after D; GE <= Z0 after D; E <= Z1 and Z0 after D; G <= Z0 and not Z1 after D; L <= Z1 and not Z0 after D;end POSDF;

Two-level logic

● Many different choices● Can be described

as structure


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Structural descriptionarchitecture TWO_LEVEL_OR_AND of COM is signal Z10,Z11,Z12,Z00,Z01,Z02: BIT; signal N0BAR,N1BAR,M0BAR,M1BAR: BIT; signal Z0,Z1,Z0NOT,Z1NOT: BIT; component NOT2G generic (D: TIME); port (I: in BIT; O: out BIT); end component; for all: NOT2G use entity NOT2(BEHAVIOR); component AND2G generic (D: TIME); port (I1, I2: in BIT; O: out BIT); end component; for all: AND2G use entity AND2(BEHAVIOR); component AND3G generic (D: TIME); port(I1,I2,I3: in BIT; O: out BIT); end component; for all: AND3G use entity AND3(BEHAVIOR); component OR2G generic (D: TIME); port(I1,I2: in BIT; O: out BIT); end component; for all: OR2G use entity OR2(BEHAVIOR); component OR3G generic (D: TIME); port (I1,I2,I3: in BIT; O: out BIT); end component; for all: OR3G use entity OR3(BEHAVIOR); component WIREG port (I: in BIT; O: out BIT); end component; for all: WIREG use entity WIRE(BEHAVIOR);

beginC1: NOT2G generic map (2 ns) port map (N0, N0BAR); C2: NOT2G generic map (2 ns) port map (N1, N1BAR); C3: NOT2G generic map (2 ns) port map (M0, M0BAR); C4: NOT2G generic map (2 ns) port map (M1, M1BAR); C5: OR3G generic map (2 ns) port map (N0BAR, M1, M0, Z10); C6: OR2G generic map (2 ns) port map (N1BAR, M1, Z11); C7: OR3G generic map (2 ns) port map (N1BAR, N0BAR, M0, Z12); C8: AND3G generic map (2 ns) port map (Z10, Z11, Z12, Z1); C9: OR3G generic map (2 ns) port map (N1, N0, M0BAR, Z00);

C10:OR2G generic map (2 ns) port map (N1, M1BAR, Z01); C11:OR3G generic map (2 ns) port map (N0, M1BAR, M0BAR, Z02); C12:AND3G generic map (2 ns) port map (Z00, Z01, Z02, Z0); C13:NOT2G generic map (2 ns) port map (Z1, Z1NOT); C14:NOT2G generic map (2 ns) port map (Z0, Z0NOT); C15:AND2G generic map (2 ns) port map (Z0, Z1, E); C16:AND2G generic map (2 ns) port map (Z0, Z1NOT, G); C17:AND2G generic map (2 ns) port map (Z1, Z0NOT, L); C18:WIREG port map (Z0, GE);C19: WIREG port map (Z1, LE);end TWO_LEVEL_OR_AND;


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Finite state machines (FSM)

● Example: serial/parallel converter– A indicates start of data

– Output Z only during one clock cycle

entity STOP is port (R, A, D, CLK: in BIT; Z: out BIT_VECTOR(3 downto 0); DONE: out BIT);end STOP;


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FSM design, cont.

● First: Select type of state machine (Moore, Mealy)– Moore machine have stable output after a few gate

delays

– Moore machine can not produce output dependent on current input values

– Moore machine may require more states than Mealy machines

– Mealy machine may sometimes be required due to direct respons from FSM on input signal change

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● Second: Create a state diagram. Good start is reset-state S0. – S1: First data on D, Done=0, Z unspecified

– S2: Second data on D, Done =0, Z unspecified

– S3: Third data on D, Done = 0, Z unspecified

– S4: Fourth data on D, Done = 0, Z unspecified

– S5: Output on Z, Done= 1

– In S5 can A also be 1 (indicating new data)● Next clock cycle must take care data, i.e., use S1 without

passing through S0

FSM design, cont.


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FSM state diagram● Some tools can translate state diagram automatically

to VHDL (e.g., HDL Designer)


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Alternative description

● Transition list– Textual description of the FSM

– Useful for large state diagrams

– Graphs become hard to understand when number of states increase

– Possible to cope with complexity by use of hierarchyPresent Transition Next Data OutputState Expression State Transfers

S0 R+A S0 None DONE=0, Z unspecifiedS0 R & A S1

S1 R S2 Store bit 1 DONE=0, Z unspecifiedS1 R S0

S5 R & A S1 None DONE=1, Z=parallel data outS5 R + A S0


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FSM description in VHDL when S3 => -- Data Section -- Shift in the third bit SHIFT_REG <= D & SHIFT_REG(3 downto 1); -- Control Section if R='0' then STATE <= S4; elsif R='1' then STATE <= S0; end if; when S4 => -- Data Section -- Shift in the fourth bit SHIFT_REG <= D & SHIFT_REG(3 downto 1); -- Control Section if R='0' then STATE <= S5; elsif R='1' then STATE <= S0; end if; when S5 => -- Data Section -- Control Section if R='0' and A='1' then STATE <= S1; elsif R='1' or A='0' then STATE <= S0; end if; end case; end if; end process STATE;

architecture FSM_RTL of STOP is type STATE_TYPE is (S0, S1, S2, S3, S4, S5); signal STATE: STATE_TYPE; signal SHIFT_REG: BIT_VECTOR (3 downto 0);beginSTATE: process (CLK) begin if CLK='1' then case STATE is when S0 => -- Data Section -- Control Section if R='1' or A='0' then STATE <= S0; elsif R='0' and A='1' then STATE <= S1; end if; when S1 => -- Data Section SHIFT_REG <= D & SHIFT_REG(3 downto 1); -- Control Section if R='0' then STATE <= S2; elsif R='1' then STATE <= S0; end if; when S2 => -- Data Section SHIFT_REG <= D & SHIFT_REG(3 downto 1); -- Control Section if R='0' then STATE <= S3; elsif R='1' then STATE <= S0; end if;

OUTPUT: process (STATE) begin case STATE is when S0 to S4 => DONE <= '0'; when S5 => DONE <= '1'; Z <= SHIFT_REG; end case; end process OUTPUT;end FSM_RTL;

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System partitioning

● Control unit, datapath, output unit– Output unit combines data and control signals

– In Mealy machines are the output unit dependent on the input data

– In Moore machines are the output unit only dependent on the datapath and control unit


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State machine partitioning

● State machines partitioned into multiple processes– Updating (clocked), i.e., the state register

– Next state calculation

– Output calculation

● May find different combinations of these– Single process

– Two processes (nextstate + output, state update)

– Three processes (nextstate, output, state update)

– Multiple processes to avoid creating Mealy instead of Moore machine


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State assignment

● States are not coded in VHDL– Use enumeration

– Allows synthesis tools do a better work

– Powerful computer algorithms usually find better state assignment

– Possible to control state minimisation and assignment in synthesis tool


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Alternative: aggregate (table based)

● Represent states as enumeration

● Code the state table as an array describing next state and output data

● Mealy FSM inexample

entity TWO_CONSECUTIVE is port(CLK,R,X: in BIT; Z: out BIT);end TWO_CONSECUTIVE;--architecture FSM of TWO_CONSECUTIVE is type STATE is (S0,S1,S2); signal FSM_STATE: STATE := S0; type TRANSITION is record OUTPUT: BIT; NEXT_STATE: STATE; end record; type TRANSITION_MATRIX is array(STATE,BIT) of TRANSITION; constant STATE_TRANS: TRANSITION_MATRIX := (S0 => ('0' => ('0',S1), '1' => ('0',S2)), S1 => ('0' => ('1',S1), '1' => ('0',S2)), S2 => ('0' => ('0',S1), '1' => ('1',S2)));begin process(R,X,CLK,FSM_STATE) begin if R = '0' then -- Reset FSM_STATE <= S0; elsif CLK'EVENT and CLK ='1' then -- Clock event FSM_STATE <= STATE_TRANS(FSM_STATE,X).NEXT_STATE; end if; if FSM_STATE'EVENT or X'EVENT then -- Output Function Z <= STATE_TRANS(FSM_STATE,X).OUTPUT; end if; end process;end FSM;

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Design process

● Best would be to write a direct synthesizable model direct– Hard to do

● First create executable model– Validate system (check for correct behavior)

– Use complex data types, real values

– Not synthesizable, may use full power of the VHDL language


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Design process, cont.● Often use an iterative design flow

● First model is a behavioral model– Check against customer requirements

– Not interested of synthesis, use all VHDL constructs


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Design process, cont.● Model 1A

– Synthesizable– Fixed point number systems– Limited memory size

● Difference in behavior– Noise like errors in signal processing systems– Need to know the effect of these errors on the overall

behavior– Need to know what can be and not be done in the model,

i.e., application area knowledge is needed, not only implementation in general (Karnough maps, VHDL etc.)


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Two approaches

● Application specific tools vs language domain modelling

● Application specific– Use description formats common in the application

domain

– Models often simulated and/or translated to other computer languages

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Application Specific tools, Example● Dataflow diagram, e.g., DSP● Tools

– SPW, Simulink (Matlab), DSP station, DSP builder

– Only suitable for the application domain

– Demonstrate working algorithm in simulation

– Often supports statistical calculations to evaluate performance reduction due to limited wordlength etc.

● Describe operations and how they communicate– Not every block corresponds to a hardware block,

only describes a function


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Language-Domain modelling

● Models described in a computer language instead of graphical entry– System-C, VHDL, Verilog, C++, Java

– Hierarchy important to reduce complexity of the description.


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Comparison

● Application domain

+ Well defined, correct functionality. Fast and easy to verify functionality. No need to understand language details

- Not very optimal/efficient if models not directly connected to the intended application area. Covers only a limited set of applications


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Synthesis and simulation● Synthesis style is tools dependent

– Something working in one tool may not work in another tool!

– Continuous development, new features added in each new release

– A standard also exist specifying a common set of expected synthesis constructs

● Wordlength and data types: Real -> Integer -> bitvectors

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ASIC design flow

● Behavoural model development● Behavoural model validation

● testbench design

● Logic synthesis● Post synthesis simulation

● gate delay, no wire delay alternatively only a coarse wire delay estimation

● System partitioning● divide into chips or large blocks on chip● I/O is limiting chip size and data speed


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● Floor planning● where to put modules/subsystems on chip

● Placement● detailed description on where each cell is placed

● Routing● connect cells with wires● Clock tree, power routing

● Circuit extraction● extract more detailed timing from circuit

ASIC design flow, cont.


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ASIC design flow, cont.

● Post layout simulation● including wire capacitance, cross talk etc.

● Send masks to manufacturer● Turn around time at least 4 weeks, probably 1-3 month


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FPGA design flow● Behavoural model development● Behavoural model validation (testbench)● Logic synthesis● Mapping to CLBs● Placement● Routing● Circuit level extraction● Post layout simulation● Generation of a POF/SOF/BIT file

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Design manager design flow (Xilinx)● Translate: Convert to local database format. Some

mapping into technology dependent mappings.● Map: Allocate CLB, IOB, etc. ● Place & route: Place and route, timing limitations

may be included.● Timing: Extract timing. Performed through static

timing analysis (Add delays from flip-flop outputs to flip-flop inputs).

● Configure: Translate layout information into a POF/SOF (bit) file to program the FPGA. May be stored in ROM or load through a processor/PC.


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Synthesis design flow Precision logic

● Analyse– Parse HDL

– Find libraries and cells

– Check dependencies

– Resolve generics

● Elaborate– Translate into a generic RTL + black box operators

– Create hierarchy, infer flipflops & latches, memory, operators, FSM


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Synthesis design flow, Precision logic, cont.

● Pre-optimization– Boundary optimization

● propagating constants, remove unused outputs, shared input signals

– Constant propagation

– Resource sharing

● Operator implementation● Hierarchy manipulations● Tristate handling


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Synthesis design flow, Precision logic, cont.

● DRC checking● Technology mapping● Register retiming

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Synthesis control ● Control synthesis process

– Pin assignment

– Timing requirements

– General placement information

– Precompiled netlists

● VHDL attributes– No standard yet

● Synthesis tool control scripts– Tools dependent

– Optimization, hierarchyTSTE12 Design of Digital Systems Department of Electrical Engineering [email protected] Palmkvist Linköping University http://www.isy.liu.se/

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Synthesis example

● Parallel to serial converter– Shift out parallel input data from PAR_IN onto SO

once START = '1'

– Lower abstraction level, bit datatypes

Library ieee;Use ieee.std_logic_1164.all;

entity PAR_TO_SER isPort( START,SHCLK: in STD_LOGIC; PAR_IN: in STD_LOGIC_VECTOR(7 downto 0); SO: out STD_LOGIC);end PAR_TO_SER;


39Hardware engineer view of the

implementation– Counter and multiplexer

Library ieee;Use ieee.std_logic_1164.all;

entity PAR_TO_SER isPort( START,SHCLK: in STD_LOGIC; PAR_IN: in STD_LOGIC_VECTOR(7 downto 0); SO: out STD_LOGIC);end PAR_TO_SER;

architecture ALG1 of PAR_TO_SER is begin

P1:process(START,SHCLK) variable COUNT: INTEGER range 7 downto -1 := 0; variable DONE: BOOLEAN;begin if START = '1' then COUNT := 7; DONE := FALSE; elsif SHCLK'EVENT and SHCLK = '1' then if DONE = FALSE then SO <= PAR_IN(COUNT); COUNT := COUNT - 1; end if; if COUNT < 0 then DONE := TRUE; else DONE := FALSE; end if; end if;end process;end ALG1;


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Programmer implementation

– Uses waveform assignment with delay information

– Same behavior, less obvious how to implement

Library IEEE;use IEEE.std_logic_1164.all;

entity PAR_TO_SER_SCHED isgeneric(PERIOD: TIME);Port( START: in STD_LOGIC; PAR_IN: in STD_LOGIC_VECTOR(7 downto 0); SO: out STD_LOGIC);end PAR_TO_SER_SCHED;

architecture ALG2 of PAR_TO_SER_SCHED isbeginP1:process(START) variable COUNT: INTEGER;begin if START = '1' then COUNT := 7; while COUNT >= 0 loop SO <= transport PAR_IN(COUNT) after (7-COUNT)*PERIOD; COUNT := COUNT - 1; end loop; end if;end process;end ALG2;

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Sensitivity list issues– Used in simulation to trigger processes

– In synthesis it only indicates inputs, often without affecting the synthesis

architecture ALG of T_FF issignal Q: STD_LOGIC;begin

process(RESET,T,CLK) begin if (RESET = '1') then Q <= '0'; elsif (CLK'EVENT and CLK = '1') then if T = '1' then Q <= not Q ; end if; end if;end process;

QOUT <= Q;end ALG;

architecture ALG of T_FF2 issignal Q: STD_LOGIC;begin

process(RESET,T,CLK) begin if (RESET = '1') then Q <= '0'; elsif (CLK'EVENT and CLK = '1') then if T = '1' then Q <= not Q ; end if; end if; QOUT <= Q;end process;

end ALG;


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Example T-flipflop

● Different behavior in the two models– Output delayed in 2nd code due to missing Q in

sensitivity list

● Synthesis can generate the same results– Flipflop with exor gate

in feedback

● Delay– Can not use an assignment

“after xx ns”, only wait for an event (on a clock)

– Wait statements for fixed delay does not make sense


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Data types

● Should use std_logic● Bit works, but the synthesized model will use

std_logic– Testbenches can not be directly reused if data type

changes


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Clock detection● CLK'EVENT AND CLK='1'

– Do not use additional enable signals in the clock edge detection

● Exists also 'RISING_EDGE and 'FALLING_EDGE– Handles also L, H, and Z in the expected way

● Synchronous/asynchronous reset/setIF asyncexpression THEN -- async reset & initelsif clockdetection -- sync expressionsend if;

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Gated clocks

● Generally not a good idea– Glitch in control signal may produce glitch on clock!

– Clock buffers may introduce large delays● Less time left for the calculation of the control signal value

● Must not combine clock edge detection with logic– If clk'event and clk='1' and enable = '1' then

● Some hardware supports gated clocks– Special forms of flipflops


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Reset of internal states

● What to do if no asynchronous reset?– Initial data must be

clocked in usinga control signal

● Code examplewithout reset– Works in simulation

due to initialisationof TEQDET

● Simulation of synthesis errordue to initialisation to 'U'

entity EQDET isPort( I,CLK: in STD_LOGIC; TEQDET: inout STD_LOGIC :='0'); end EQDET;

architecture ALG of EQDET is begin process variable EQ,IBK1,IBK2: STD_LOGIC; begin wait until (CLK'EVENT and CLK = '1'); if(IBK1 =IBK2) and (IBK2 = I) then EQ := '1'; else EQ := '0'; end if; TEQDET <= (EQ xor TEQDET); IBK2 := IBK1; IBK1 := I; end process;end ALG;


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Using explicit reset

● Asynchronous reset● Possible to use

synchronous resetinstead

architecture ALG of EQDET is begin process(RESET,CLK) variable EQ,IBK1,IBK2: STD_LOGIC; begin if (RESET = '1') then IBK1 := '0'; IBK2 := '0'; TEQDET <= '0'; elsif (CLK'EVENT and CLK = '1') then if (IBK1 = I) and (IBK1 = IBK2) then EQ := '1'; else EQ := '0'; end if; TEQDET <= (EQ xor TEQDET); IBK2 := IBK1; IBK1 := I; end if; end process;end ALG;

entity EQDET isPort( RESET,I,CLK: in STD_LOGIC; TEQDET: inout STD_LOGIC);end EQDET;


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Simulation and synthesis results

● Order of IBK1 and IBK2updates are importantif variables are used

● Update ordernot important if signals are used– EQ still a variable!

● Both descriptions givesame synthesis result

architecture ALG of EQDET is signal IBK1,IBK2: STD_LOGIC; begin process(RESET,CLK) variable EQ: STD_LOGIC; begin if (RESET = '1') then IBK1 <= '0'; IBK2 <= '0'; TEQDET <= '0'; elsif (CLK'EVENT and CLK = '1') then if (IBK1 = I) and (IBK1 = IBK2) then EQ := '1'; else EQ := '0'; end if; TEQDET <= (EQ xor TEQDET); IBK1 <= I; IBK2 <= IBK1; end if; end process;end ALG;

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Synthesized version

● 2 bit shiftregister plus T-flipflop– Cost is 3 D-flipflops and 4 2-input gates


50

FSM based alternative

● Same functionality, different synthesis result!– State machine

+ data path

– Toggle T-flipflop in S2

– Save input in internal flipflop (not state)

architecture FSM of EQDET is beginP1:process(RESET,CLK)type STATE_TYPE is (S0,S1,S2);variable STATE: STATE_TYPE;variable IBK1: STD_LOGIC;begin if RESET = '1' then STATE := S0; IBK1 := '0'; TEQDET <= '0'; elsif (CLK'EVENT and CLK = '1') then case (STATE) is when S0 => STATE := S1; IBK1 := I; when S1 => if (IBK1 = I) then STATE := S2; else STATE := S1; end if; IBK1 := I; when S2 => if (IBK1 = I) then STATE := S2; TEQDET <= not TEQDET; else STATE := S1; end if; IBK1 := I; end case;end if;end process;end FSM;


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Implementation of FSM based design

● 1st flipflop for storing old input● Last flipflop for T-flipflop function● Middle two for FSM implementation


52

FSM design

● Structure: 2 or 3 process● Case vs if-elsif-then

– Case with all enumerations better

– Use symbolic states

● Output signal update– Separate output process

– May give latches if not given output values

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Counter design

● Use loadable down counter if not power of 2– Avoid comparison operation, uses zero detection

instead


54

Simple rules/hints

● Do not assign initial values to signals and variables in the declaration– Not supported for synthesis

– Use explicit assignment instead inside a process

● Always use limited number ranges– May get 32 bit arithmetic if not limited

● Allow synthesis tool to select state coding– Can sometimes be done better manually


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Storage elements● RAM-block synthesis

– Ordinary array implementation: flip-flops

– Some tools (e.g., leonardo, precision logic) may find these and use built-in RAM

– Altera CycloneII 2C70: 250 blocks a 4Kbit => 128 Kbyte internal memory

● Latches– Not supported in all technologies (due to glitches

etc).

– Some tools produce latches using combination logic


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Memory models

● Large number of available types– Single/multi port

– Synchronous/asynchronous

● RAM areas may be initialized (when FPGA is configured)

● ROM sometimes implemented as initialized RAM areas– Described as case statements or array of constants

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Single port memory model


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Synthesis of combinational logic

● Simple example: full adder– 3 different versions

architecture ROM of ONES_CNT isbegin process (A) type ROM_TABLE is array( 0 to 7) of STD_LOGIC_VECTOR(1 downto 0); constant ROM: ROM_TABLE := (('0','0'),('0','1'),('0','1'),('1','0'), ('0','1'),('1','0'),('1','0'),('1','1')); begin C <= ROM(CONV_INTEGER(A)); end process; end ROM;

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;use IEEE.std_logic_arith.all;

entity ONES_CNT is port (A: in STD_LOGIC_VECTOR(2 downto 0); C: out STD_LOGIC_VECTOR(1 downto 0));end ONES_CNT;

architecture DATA_FLOW of ONES_CNT isbegin C(1) <= (A(1) and A(0)) or (A(2) and A(0)) or (A(2) and A(1)); C(0) <= (A(2) and not A(1) and not A(0)) or (not A(2) and not A(1) and A(0)) or (A(2) and A(1) and A(0)) or (not A(2) and A(1) and not A(0));end DATA_FLOW;

architecture MUX of ONES_CNT isbegin

process(A) begin case A is when "000" => C<= "00"; when "001"|"010"|"100" => C<= "01"; when "011"|"101"|"110" => C<= "10"; when "111" => C<= "11"; when others => null; end case; end process;end MUX;


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Implementation of full adder

● Synthesis results for data-flow, mux, ROM– Synopsis: 9 cells, 2.49 ns delay


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Simple adder: Algorithmic

● Initial translation: loop with counter

● Loop unrolling => parallel form

architecture ALGORITHMIC of ONES_CNT isbegin P1:process(A) variable NUM: INTEGER range 0 to 3; begin NUM := 0; for I in 0 to 2 loop if A(I) = '1' then NUM := NUM + 1; end if; end loop; case NUM is when 0 => C <= "00"; when 1 => C <= "01"; when 2 => C <= "10"; when 3 => C <= "11"; end case;end process P1;end ALGORITHMIC;

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Algorithmic model implementation

● Synopsis finds combinational circuit– 17 cells, 4,89 ns delay

● Further optimization reaches other synthesis results– Synthesis will reach same efficient solution, but

requires more computer time


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Arithmetic operations

● Add, sub supported– Translates into full adder before simplified

– Operands are not extended

● Multiplication– Translated into combinational expressions

– Multiple possible structures: Wallace, Carry Save array.

– Constant values usually produces add and shift implementations (simplified multiplications)

● Division usually not supported

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2 TSTE12 Design of Digital Systems Friendly reminder · when "0110" => GE