2-Fundamentals on ADCs-Part 1

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Fundamentals on ADCs: Part I Jose Silva-Martinez

FUNDAMENTALS OF ANALOG TO DIGITALCONVERTERS PART I 1ONVERTERS: PART I 1

-Amesp02.tamu.edu/~jsilva

Many of these slides were provided by

Dr. Sebastian Hoyos

Amesp02.tamu.edu/~hoyos

January 2011

Texas A&M University 1 Spring, 2011


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Outline Fundamentals of Analog-to-Digital Converters

Introduction

Sampling and Quantization

Quantization noise and distort ion

INL and DNL

ys em m a ons

Linear Range

Stability

Potential realizations

ADC architectures SAR

pe ne me n er eave Sigma-Delta

Folding

Flash



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R. Walden, 1999


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What is an AnalogWhat is an Analog--toto--Digital Converter (ADC)?Digital Converter (ADC)?Analog Digital

0100101100101001010101010

0100100100100101100110010

10100100101001001010

Continuous wi th no apparentdiscontinuities

The way we interpret our

Discrete with limi ted range;based on binary numbers with

limited number of bi ts.ADCsurroundings: sound, light,temperature etc

The way we mathematicallyrepresent and process our worldusing electronic brain power



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How does an ADC work?How does an ADC work?Analog Digital1001010010100101100101001010101010

1001100101

1001010

0100100100100101100110010

10100100101001001010

Continuous wi th no apparentdiscontinuities

The way we interpret our ADC

Discrete with limi ted range;based on binary numbers with

limited number of bi ts.

surroundings: sound, light,temperature etc

The way we mathematicallyrepresent and process our worldusing electronic brain power



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How does an ADC work?How does an ADC work?x(t)

Analog DigitalADC

t

100101001

010010100

1001100101

Quantizationnoise

x(n)

(n)nTS

eve sseparated

by 1LSB,

1LSB =

VFS* / 2N


nTS* VFS = full scale range, Vmax-Vmin


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ADCs: Yesterday vs. TodayExample: Digital photography (8-12b ADCs)

Yesterday: 2000 Today: 2009

DSP(balance control, black level

compensation, imagestabilization, exposure levels,noise reduction, lens shading

correction, encoding...etc)

AMP

CCD/

CMOSImage

Array

ADC

0.5-0.8m CMOS with 5V supply (moderate gate density

and speed in DSPs)

2M pixel CCD sensor (low pixel scanning speed)

90nm-180nm CMOS with 1.2-1.8V supplies (high gate

density and speed in DSPs)

12M pixel CCD sensor (high pixel scanning speed)

ADCs are indispensable, butnow need to handle smaller

-

~ 2.5mV / LSB

-

~ 0.5mV / LSB

Faster DSPs capable ofperforming numerous complex

ADCs are becoming thebottleneck for advancement, and


s gna s a g er spee s wsimilar or higher resolutions.

unc ons are eve ope an sto advanced CMOS technologies.

new es gn ec n ques nee obe developed.


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ADCs: Tomorrow?ADCs: Tomorrow?ADC IEEE l iterature survey: 2006-2008

18

20

Pipeline ADC Applications

Today

10

1214

16

lution(b

its)

-

2

4

6

8

Res

Pipelined

Flash

Tomorrow

Pipeline ADC is currently most published architecture

Pipeline ADC is breaking the trend set by Sigma-Delta

.

Signal Bandwidth (MHz)

.

Pipeline ADC is breaking the trend set by Sigma-Delta

and Flash ADCs Pipeline ADC is expected to be a key ADC architecture in

future applications

The develo ment of new desi n techni ues for hi h s eed low volta e and low

15M?20M?

From 1080P to4K (2160P)?

4G?HDTV?

and Flash ADCs, and driven by consumer electronics


power Pipeline ADCs is crucial to stay on the future applications roadmap


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Fundamentals on ADCs: Part I Jose Silva-MartinezDesign Challenges of Pipeline ADCs inDesign Challenges of Pipeline ADCs inAdvanced CMOS Technologies (Summary)Advanced CMOS Technologies (Summary)

High Speed Low Voltage Low Power

DSP(balance control, black level

compensation, imagestabilization , exposure levels,

noise reduction, lens shading

AMP

CCD/

CMOS

Image

Arr ay

ADC

Digital Camera Example

, ...

With the added speed of Reduction of Device size Many applications are,

ADC is becoming the

bottleneck for overall system

speed

in addition to increased

,

but device reliability dictate

lower supply voltages

Reduced supplies means

reduced si nal ran e which

battery

As a potentially power

hungry component, the ADC

ower needs to be reduced

speed, the DSP ability toperform more complex tasks

will require higher ADC

resolutions

requires a higher ADCaccuracy for the same number

of bits

to help prolong battery life



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The Smartphone marketThe Smartphone market

Anticipated global unit sales to approach 400 millions in 2013

(market research report from Forward Concepts Co)


Projected revenue in 2012: $32.2 bill ion

(source: In-Stat Group)


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-- Multiple services

Reuse circuits as much as possible Power

Area

Competitiveness

Smaller Cell phone,

stronger function,

longer battery duration

Use of digital (analog unfriendly)


nanometric tecnologies


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-- Exponential growth in mobile computing and broadband wireless

Major need for high dynamic range, wide-bandwidth, low power ADCs.



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Bandwidth requirements for higher connectivityBandwidth requirements for higher connectivity

Higher flexibi lity on operational frequency and bandwidth,,

Receiver Architectures:

- - -


, , , ,Radio


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Su er-heterod ne Receiver

Invented by Armstrong in 1918

Hardware specific radio architectureExtensive filtering to relax ADC specs


Suitable for narrow-band applications


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Desi n issues for multi-standard solutionsLimited by flicker

Not flexible

Hardware intensive

Excessive power at the front-end (Linearity issues)

Extensive down conversions: LO and mixers increase

ot no se an power consumpt on Extensive filtering: Area, Power and Noise issues



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--Antenna

Receiver for standard 1 Minimum sharing of

BPF LNA BPFVGA

RF(1-2 GHz) (100-200 MHz) blocks

Area and ower

LO2LO1

consumption overhead

RFSwitch

BPF LNA BPFVGA

RF(1-2 GHz)

IF(100-200 MHz)

Limited number of

LO2LO1

accommodated



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Efficient radio transceiver: Direct ConversionAntenna

16-Channel MultibandDigital Receiver

Frequency

Synthesizer

RFsignal

SoftwarePlatform

LNA & VGARF Filter 1 ADC 1

IF Filt er 180 MHz

4-

channel

digitalreceiver

4-

channel

Mixer

DSP

or

FPGAs

digital

receiver

ADC 2IF Filter 2

4-

channel

digital

Antenna

RFsignal

LNA & VGARF Filter 2

Optional

Mixer

4-

channel

digitalreceiver

Direct conversion + broadband ADC (1 receiver per service) Lowpass filter is required (~ 50-100 mW)

13-14 bits 80 MHz Low ass ADC 500 mW from ADI


Bank of receivers, fi lters and ADCs


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Recent A roaches to Broadband ReceiversRecent A roaches to Broadband Receivers Sample rate, downsampling and f ilteringR. Crochiere and L. Rabiner, Multirate Digital Signal Processing. Englewood Cliffs, NJ:

Prentice Hall, 1983.

Sampling with built-in anti-aliasingY. S. Poberezhskiy et.al. Sampling and signal reconstruction circuits performing internal

transmitters, TCASI, Jan. 2004.

A discrete-time RF sampling receiver. . , . . - -

Bluetooth radio in 130-nm CMOS, IEEE J. Solid-State Circuits, Dec. 2004.

SDR receiver

bidi, The path to so tware-de ined radio receiver, IEEE J , May 2007

Frequency-domain-sampling receiversS. Hoyos and B. M. Sadler, Ultra-wideband analog to digital conversion via signal


expansion, IEEE Transactions on Vehicular Technology, Sept. 2006.


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UCLA SDR receiverUCLA SDR receiver

Direct conversion with tunable LO in the freq. range 800 MHz to 6 GHz.

Cascade of sincN filters followed by decimation to achieve the initializing

needed.

Good for narrowband signals as a single ADC can handle the bandwidth. But

SDR should also be good for wideband and ultra-wideband signals. Need parallelADC to sample at a fraction of Nyquist rate. Parallelization of the front-end will be

needed if want to keep the ADC sampling rate down.


A. Abidi, The path to software-defined radio receiver, IEEE JSSC, May 2007


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FrequencyFrequency--Domain ADC Based on Fourier CoefficientsDomain ADC Based on Fourier Coefficients

( )r t 0R

0R( 1) c

c

m T

mTdt

1

Tc

F0 F1 FN-1F2

02j F t

e

R

1R2R

( 1) cc

m T

mTdt

0R1NR

e

Mixers and integrators. No signal reconstruction. Parallel

ower requency samp e anhold requirements. g a process ng. Optimal bit allocation minimizes

quantization error. Some

sam les ma not be uantized at all.


S. Hoyos and B. M. Sadler, Ultra-wideband analog to digital conversion via signal expansion, IEEE

Transactions on Vehicular Technology, Sept. 2006.


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Roadma for hi hRoadma for hi h--resolution Receiversresolution Receivers

How much RF processing should be done before the ADC?


-


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The sin leThe sin le--chi Transceiver Paradi mchi Transceiver Paradi m

22

Modern technologies:Modern technologies:

-- --

Chip (SOC) environmentChip (SOC) environmentScaling of transistor dimensions in digital

ec no og es

Increased intra-die variability from device

scaling e ec ens es ncrease n newertechnologies

Yields decrease as SOC chip sizes increase

e mpac on ana og spec ca ons ea sto process corner-based overdesignto allow for analog parameter variations


Critical Analog components must be minimizedCritical Analog components must be minimized

M. Onabajo, 2011


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Fast CMOS ADCs: State of the artFast CMOS ADCs: State of the art

pecturm

Trends:

Extensive use of parallelism

Freq (GHz)

S

5.42.421.91.00.05 0.8

Time interleaved

Reduced supply voltages make

analog more challenging

16

14

Pipeline

Headroom for amplifiers

Little room for cascoding

Poor devices if VDS is

Immediate Goal

12

10

8

Pipeline Interleavedfurther reduced

Use techniques that take

advantage of digital trends

6

4

10 MS/s 100MS/s 1GS/s 10GS/s 100GS/s

Flash Digital circuitry is cheap and fast

Tendency is Digitally Assisted

Analo Circuits


Sampling rate


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Introduction to AnalogIntroduction to Analog--toto--Digital ConvertersDigital Converters

Analog-to-Digital Converters (ADC) are necessary to

their digital equivalents for easy processing. Common applications for ADCs are communication

systems, TV receivers, Digital Oscilloscopes, Audio

applications..

Analog



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Software radio transceiver: Desi n IssuesSoftware radio transceiver: Desi n Issues

-

architecture?

Bandwidth required?

ynam c range requ re DTV SNRsignal=25 dB; Blockers > 45 dB; Crest factor > 20 dB

LNA+VGA+ADC Dynamic Range over 90 dB (practical ?)


Can you use tracking filters? (back to the past)


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Software radio transceiver: Ultimate oalSoftware radio transceiver: Ultimate oal

Concept introduced in 1991 Modulation/demodulation waveforms in software


Flexible multi-standard software architecture


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Data Converters: The main issueData Converters: The main issue

The quantized signal

of output values that areassociated with digital



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Texas A&M University 28 Spring, 2011R. Walden, 1999


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Where we were in 99? Where we are?

WiMAX



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F d t l ADC P t I J Sil M ti


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F d t l ADC P t I J Sil M ti


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Bandwidth (Nyquist in pipeline) vs. SNDR

+

1.E+11ISSCC 1997-2009

VLSI 1997-2009

1.E+08

1.E+09

.

z]

ISSCC 2009

Jitter=1psrmsJitter=100fsrms

1.E+06

1.E+07

BW[

1.E+04

1.E+05

.

10 20 30 40 50 60 70 80 90 100 110 120

SNDR [dB]


B. Murmann, "ADC Performance Survey 1997-2010, http://www.stanford.edu/~murmann/adcsurvey.html.

Fundamentals on ADCs: Part I Jose Silva Martinez


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Ener er conversion at N uist rate1.E+07

1.E+04

1.E+05

.

pJ]

1.E+02

1.E+03P/f

s

1.E+00

1.E+01

ISSCC 1997-2009

VLSI 1997-2009

FOM=100fJ/conv-step

FOM=10fJ/conv-step1.E-01

10 20 30 40 50 60 70 80 90 100 110 120

SNDR [dB]


B. Murmann, "ADC Performance Survey 1997-2010, http://www.stanford.edu/~murmann/adcsurvey.html.



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What the roblem is?




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Issues: Sam lin Holdin and conversionIssues: Sam lin Holdin and conversion

The quantized signal

of output values that areassociated with digital




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Properties of the Fourier SeriesProperties of the Fourier Series




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Pro erties of the Fourier SeriesPro erties of the Fourier Series

Texas A&M University 40 Spring, 2011Convolution in timeConvolution in time



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Relevant ro erties of the Fourier SeriesRelevant ro erties of the Fourier Series




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Relevant ro erties of the Fourier SeriesRelevant ro erties of the Fourier Series




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Additional ro erties of the Fourier SeriesAdditional ro erties of the Fourier Series




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Define the roblem: Sam lin O eration




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Si nal Sam lin TheoremSi nal Sam lin Theorem

TimeTime

domaindomain

samplingsampling

FrequencyFrequency

SpectrumSpectrum




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Si nal Sam lin em lo in a train ofSi nal Sam lin em lo in a train of

pulsespulsesTime domain sampling withTime domain sampling withpulsespulses

SpectrumSpectrum




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Sam lin O eration:Sam lin O eration: N uistN uist RateRate

According to the sampling theorem: If noalias issues, then

Ideal sampling does notIdeal sampling does not

a s or on ua s or on ureplicas of the originalreplicas of the original


spec rumspec rum



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Alias issue ifAlias issue if undersam linundersam lin




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Under-sam lin of a broadband si nal




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S/H and Quantization errorsS/H and Quantization errors

The sampling and Held operations generate aliasfrequency components and (sinc) signal distortion,

Error is an odd function (no even harmonic distortions,why?)

Quantization generates harmonic distortion componentswhen sinusoidal input signals are used

tErr ortStS qi n




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Distortion due to uantization errorsDistortion due to uantization errors




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ADCADC metrics: Quantization errormetrics: Quantization error

Signal is sampled at given instants

Signal is encoded to a limited number of codes resulting inquantization noise (random signals) and distortion (periodic signals)




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Mapping anMapping aninfiniteinfiniteresolutionresolution

analog signalanalog signalinto a digitalinto a digital

resolutionresolutionrepresentationrepresentation



Q ti ti i f R d (R ) i t i lQ ti ti i f R d (R ) i t i l


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Quantization noise for Random (Ramp) input signalQuantization noise for Random (Ramp) input signal




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ADCADC t i SQNRt i SQNR


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ADCADC metrics: SQNRmetrics: SQNR

The maximum Signal-to-Quantization Noise

dB.N.

//APS NR

Nsignal

761026222

22

-

/PP noisenoise 12

or an w a measure , e e ec ve

number of bits is defined as:

02.676.1)dB(SNDRENOB



Quantization noise densityQuantization noise density


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Quantization noise densityQuantization noise density

The dynamic range of a system is equal to the signal to noise ratio measuredThe dynamic range of a system is equal to the signal to noise ratio measuredover a bandwidth equal to half of the sampling (over a bandwidth equal to half of the sampling (NyquistNyquist) frequency) frequency

Then,Then,

2

212q

Is the total while the quantization noise densityIs the total while the quantization noise density(quantization noise measured in a bandwidth of 1 Hz)(quantization noise measured in a bandwidth of 1 Hz)

ss f6

q

f

2densityNoi se


fs/2-fs/2



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Di ital to Analo ConvertersDi ital to Analo Converters


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Practical DefinitionsPractical Definitions


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Practical DefinitionsPractical Definitions




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Practical LimitationsPractical Limitations


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Usually not a ma or ssue u te cr t cal ssueUsually not a ma or ssue u te cr t cal ssue



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Practical Limitations: Absolute AccuracPractical Limitations: Absolute Accurac


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Analo to Di ital ConvertersAnalo to Di ital Converters


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Usually the effectsUsually the effects

offsets can beoffsets can be

minimized throughminimized through

calibration orcalibration or

accounted inaccounted indigital domaindigital domain





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must e sma er or equa tomust e sma er or equa to




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Offset Volta esOffset Volta es


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2-Fundamentals on ADCs-Part 1