11ISPD'03ISPD'03

Process Variation Aware Process Variation Aware Clock Tree RoutingClock Tree Routing

Bing LuBing LuCadenceCadence

Jiang HuJiang HuTexas A&M UnivTexas A&M Univ

Gary EllisGary EllisIBM CorpIBM Corp

Haihua SuHaihua SuIBM CorpIBM Corp

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OutlineOutline

• Introduction• Previous work• Problem formulation• Minimum skew violation clock tree• Experimental results• Extension to bounded skew clock tree• Conclusion

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Process VariationProcess Variation

T

S

W

H

Ground plane

tox

Junction depth

Gate width

Gate lengthEtching errors

Mask misalignment

Spot defects

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Impact to Clock SkewImpact to Clock Skew

• 20-30% variation on clock skew, mostly due to clock buffers ( Zanella, et al., TCAD 12/2000 )

• Interconnect variations may cause up to 25% variation on clock skew( Y. Liu, et al., DAC 2000 )

• Undesired skew bottleneck of clock frequency

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OutlineOutline

• Introduction• Previous work• Problem formulation• Minimum skew violation clock tree• Experimental results• Extension to bounded skew clock tree• Conclusion

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Previous Work Previous Work

• Buffer insertion/sizing [Chung and Cheng, ICCAD 94] [Xi and Dai, DAC 95]

• Wire sizing [Pullela, Menezes and Pillage, DAC 93]

• Non-tree topology [Lin and Wong, ICCAD 94][Su and Sapatneker, ICCAD 01]

• Abstract topology [Velenis, Friedman and Papaefthymiou, ISCAS 01]

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Focus on Clock Tree RoutingFocus on Clock Tree Routing

• Interconnect variation is significantly important

• Unlike transistors, worst case skew from interconnect variation is not at corner points

• Result can be applied as a sub-network in buffered/non-tree clock network

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Wire Width Variation ModelWire Width Variation Model

-3 -2 -1 +1 +2 +3Ws

68.26%95.44%99.74%

WuWl

Wire width: w = Ws + Ws = W0 + • x + • y Lower limit: Wl = Ws - 3 Upper limit: Wu = Ws + 3 : standard deviation = = 3 dmax

dmax max dist between sinks

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OutlineOutline

• Introduction• Previous work• Problem formulation• Minimum skew violation clock tree• Experimental results• Extension to bounded skew clock tree• Conclusion

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Problem FormulationProblem Formulation

• Permissible range for sink si and sj

[ LPRij, UPRij ]

• Skew violationmax ( LPRij – skewij, skewij – UPRij )

• Minimizing Skew Violation ( MinSV ):Given a set of clock sinks { s1, s2, …, sn }, skew

permissible ranges for all pairs of sinks, [Wl, Wu], find a clock routing tree such that the max skew violation among all sink pairs is minimized

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AssumptionsAssumptions

• Elmore delay model• Given abstract topology

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OutlineOutline

• Introduction• Previous work• Problem formulation• Minimum skew violation clock tree• Experimental results• Extension to bounded skew clock tree• Conclusion

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DME Based FrameworkDME Based Framework

• Deferred Merge Embedding (DME)– Bottom-up, find merging segments– Top-down, find locations for internal nodes

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Find Merging LocationsFind Merging Locations• For particular z value

– Skew range [ skew ij, min, skew ij, max ]

• z , range shifts to greater values• z , range shifts to smaller values• Adjust z such that

center of skew range is aligned to center of permissible range

• In DME, adjust z such thatskew ij = 0 si sj

ni nj

n

z

Dij

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Align Skew RangeAlign Skew Range

si sj

ni nj

n

z

Dij

Permissible range

Skew range z = 0

Skew range z = Dij

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When Snaking NecessaryWhen Snaking Necessary

si sj

ni

njn

Dij

Permissible range

Skew range z = 0

Skew range z = Dij

Permissible range

Skew range z = 0

Skew range z = Dij

si sj

ni nj

nDij

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Worst Case Skew EstimationWorst Case Skew Estimation

• skew ij,min = t i,min – t j,max

• skew ij,max = t i,max – t j,min

• Need to estimate min and max delay to a sink under process variation

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Worst Case Delay Estimation: Worst Case Delay Estimation: Single SinkSingle Sink

• Wire capacitance clw• Wire resistance rl/w• t = rcl2/2 + rl C/w• tmin = rcl2/2 + rl C/WU

• tmax = rcl2/2 + rl C/WL

l

C

w

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Worst Case Delay Estimation: Worst Case Delay Estimation: Multiple SinksMultiple Sinks

• t pi,min – Width of path np -> si is WU

– Width of wires not on np->si is WL

• t pi,max – Width of path np -> si is WL

– Width of wires not on np->si is WU

si

sj

sknp

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How to Choose Sink PairHow to Choose Sink Pair• How to choose si in left subtree and sj in right

subtree?• Ideally, need to evaluate all sink pairs between

left and right subtree– Greatly increase computation cost

• Heuristic: pick the most critical pairCriticalityij = dij dmax + PRmin PRij

dmax: max sink pair distance

PRmin: min permissible rangesi sj

ni nj

n

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OutlineOutline

• Introduction• Previous work• Problem formulation• Minimum skew violation clock tree• Experimental results• Extension to bounded skew clock tree• Conclusion

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ExperimentsExperiments

• Benchmark circuits r1-r5• SUN Blade-100 workstation, 512M memory• Compare with extended DME

– Align nominal skew to center of permissible range• S: permissible range LPR, UPR symmetric wrt 0• NS: LPR, UPR asymmetric wrt 0

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Number of Skew ViolationsNumber of Skew Violations

0

200

400

600

800

1000

1200

r1-S r1-NS

r2-S r2-NS

r3-S r3-NS

r4-S r4-NS

r5-S r5-NS

DMEMinSV

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Maximum Skew ViolationMaximum Skew Violation

0200400

600800

1000

120014001600

r1-S r1-NS

r2-S r2-NS

r3-S r3-NS

r4-S r4-NS

r5-S r5-NS

DMEMinSV

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OutlineOutline

• Introduction• Previous work• Problem formulation• Minimum skew violation clock tree• Experimental results• Extension to bounded skew clock tree• Conclusion

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Pair-wise Bounded Skew RoutingPair-wise Bounded Skew Routing

• Minimizing Wirelength s.t. Skew Constraints:Given a set of clock sinks { s1, s2, …, sn }, skew permissible ranges

for all pairs of sinks, find a clock routing tree such that the total wirelength is minimized while all permissible range are satisfied

• Find merging regions instead of merging segments• Similar to Bounded Skew Clock Routing

[Cong, et al., ACM TODAES 98]

• Pair-wise skew permissible range vs. global skew bound• More wirelength reduction

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OutlineOutline

• Introduction• Previous work• Problem formulation• Minimum skew violation clock tree• Experimental results• Extension to bounded skew clock tree• Conclusion

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ConclusionConclusion

• Wire width variation needs to be considered in clock tree routing

• Worst delay variation can be estimated given the wire width variation range

• Our MinSV method significantly improves tolerance to wire width variation

• Our method can be extended to pair-wise bounded skew routing to further reduce the total wire length

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Thank you!Thank you!