IEEE Communications Magazine • September 200646 0163-6804/06/$20.00 © 2006 IEEE

TOPICS IN RADIO COMMUNICATIONS

INTRODUCTION

The Coordinate Rotation Digital Computer(CORDIC) was introduced in 1959 by Volder [1].It is an easy-to-implement and versatile algorithmwidely used for digital signal processing applica-tions. It computes iteratively the rotation of atwo-dimensional vector using only add and shiftoperations. CORDIC has been traditionally usedfor hardware implementations. In [2] several algo-rithms which admit efficient implementationusing CORDIC were reviewed: linear transforms,digital filtering, and matrix based DSP computingalgorithms. It was shown that CORDIC-basedarchitectures are a very appealing alternative toconventional multiply-and-add hardware. Howev-er, CORDIC may be also applied to implementdifferent communication subsystems found in adigital radio: direct digital synthesizers; amplitudemodulation (AM), phase modulation (PM), andfrequency modulation (FM) analog modulators;amplitude shift keying (ASK), phase shift keying(PSK), and frequency shift keying (FSK) modula-tors, up-/downconverters of in-phase and quadra-ture signals, full mixers for complex signals, andphase detection for synchronizers.

This article shows how to use CORDIC in soft-ware defined radios (SDR). First, CORDIC isintroduced as a computational resource that isable to rotate a vector by an angle, and convertfrom Cartesian to polar coordinates; also shown isa generic scheme suitable for implementing thedifferent tasks required in communication systems.Second, several applications are commented on:direct digital synthesis; frequency, phase, andamplitude modulation; up-/downconversion; and

frequency and phase synchronization for quadra-ture amplitude modulation (QAM) and orthogo-nal frequency-division multiplexing (OFDM)systems. Third, the CORDIC algorithm is exposed,and some implementation issues to improve itsperformance are included: how to enhance thespurious free dynamic range (SFDR) in direct dig-ital synthesizers (DDS); how to avoid the π/2 mul-tiplier of the phase accumulator; and how tosimplify the computation of the scaling factor.

A FUNCTIONAL LOOK AT CORDICFor an easy understanding of how to use theCORDIC algorithm in the implementation ofdigital intermediate frequency (IF) communica-tions systems, CORDIC is presented in this sec-tion only as a computational resource with threeinputs (X0, Y0, and Z0) and three outputs (XN,YN, and ZN) that allows performing the followingoperations (illustrated in Fig. 1):• Rotation of a vector (I,Q) by an angle θ

when it is operating in rotation mode (RM);the rotated output vector is multiplied by aconstant value K

• Cartesian-to-polar conversion, when it isoperating in vectoring mode (VM); themodulus of the vector is also scaled by KA generic scheme that shows how to use RM

CORDIC to implement different digital commu-nication tasks is illustrated in Fig. 2. The schemeis composed of an RM CORDIC where signals Iand Q are connected into Xo and Yo inputs, andthe phase term θ connected into Zo input is θ =(Σ[fc + fm]) + φm) ⋅ π. This phase term is com-posed of the accumulation, at a sample period ofTs, of two frequency terms, fc and fm, and a phaseterm, φm. The additions involved in its computa-tion are signed modulo-1 (limited to the interval[–1,1]), and the frequency and phase terms fc, fmand φm are normalized to 1. The CORDIC Zoinput needs a phase input that takes values in theinterval [–π, π], so a multiplication by π isrequired to extend the interval of the normalizedterm θ to the interval required by CORDIC.

CORDIC IN SDRCOMMUNICATIONS SYSTEMS

This section shows how CORDIC algorithm is usedto perform several tasks needed in SDR systems.

Javier Valls, Trini Sansaloni, Asun Pérez-Pascual, Vicente Torres, and Vicenç Almenar,

Universidad Politécnica de Valencia

ABSTRACT

CORDIC is a versatile algorithm widely usedfor VLSI implementation of digital signal process-ing applications. This article presents a tutorial ofhow to use CORDIC to implement differentcommunication subsystems that can be found in asoftware defined radio. Specifically, it shows howto use CORDIC to implement direct digital syn-thesizers, AM, PM, and FM analog modulatorsand ASK, PSK and FSK modulators, up-/down-converters of in-phase and quadrature signals, fullmixers for complex signals, and phase detectionfor synchronizers. The article also shows sometricks to efficiently implement the algorithm.

The Use of CORDIC in Software Defined Radios: A Tutorial

VALLS LAYOUT 8/21/06 1:39 PM Page 46

IEEE Communications Magazine • September 2006 47

This includes direct digital synthesis; FM, PM, andAM; ASK, PSK, and FSK; up-/downconversion ofin-phase and quadrature signals; and frequencyand phase synchronization subsystems.

DIRECT DIGITAL SYNTHESISDirect digital synthesis is a method to generatewaveforms directly in the digital domain. In ourcase study of communications systems the targetwaveforms are the sine and cosine ones. A DDS iscomposed of a phase accumulator and a phase-to-amplitude converter [3], as shown in Fig. 3a. In aconventional DDS based on lookup tables (LUTs)the phase accumulator is an integer N-bit accumu-lator (an unsigned modulo-2N accumulator),whose output directly addresses the LUT wherethe amplitude values of sine or cosine waves arestored. The maximum value of the accumulator(2N–1) represents the phase 2π of the sine orcosine wave. The accumulator generates a rampsignal when it is incremented by a fixed value, dueto its unsigned modulo-2N property; hence, a peri-odic waveform is obtained at the output of thephase-to-amplitude converter (Fig. 3b).

The CORDIC algorithm configured in RMcan behave as a quadrature phase-to-amplitudeconverter that directly generates sine and cosinewaveforms [4]. The main advantage of usingCORDIC-based DDS with respect to LUT-based methods is that it can achieve both highphase resolution and high precision with lowerhardware cost [5]. A difference between bothmethods is that the phase accumulator generatesan integer value that addresses an LUT in theLUT-based method, while it generates an anglein CORDIC-based DDS. Thus, in the last case aramp signal in the interval [–π,π,] must beobtained by the accumulator, as shown in Fig.3c. This accumulator is easily implemented withan N-bit adder. A two’s complement fractionalnumeric format (only one integer bit) is consid-ered; hence, a ramp in the interval [–1,1] is gen-erated, and a multiplier by π is introduced toachieve the desired range.

To generate sine and cosine waveforms of adigital frequency fc with the scheme based onCORDIC of Fig. 2, the parameters fm, φm, andQ must be zero and I = 1/K. The oscillation fre-quency is controlled by giving a fixed value to fc.In such a case CORDIC generates directly thecosine and sine waveforms (si(n) = cos(fc ⋅ π ⋅ n)and sq(n) = sin(fc ⋅ π ⋅ n)) through XN and YNoutputs, respectively.

The maximum synthesized frequency isobtained by taking the value fc = 1 (which isequivalent to analog frequency of fs/2); and theminimum frequency is achieved with fc = 2–(N–1),where N is the word-length of the accumulator.

FREQUENCY, PHASE ANDAMPLITUDE MODULATORS

The CORDIC scheme of Fig. 2 can be used todirectly generate in the digital domain at IF theanalog modulations AM, PM, and FM, or thebinary modulations ASK, PSK, and FSK.

Considering m(n) as the modulator signal, AMcan be implemented by choosing in Fig. 2 a carri-er IF fc, using the input Xo as modulator signal I= m(n)/K, and leaving to zero fm, φm, and Q. In

such a case the AM signal (s(n) = m(n) ⋅ cos(fc ⋅π ⋅ n)) is generated through XN CORDIC output.

If PM is desired, the terms fm and Q of Fig. 2are zeroed, the input Xo is fixed to I = 1/K, andthe phase modulator signal is fm = m(n). Thenthe PM signal (s(n) = cos(fc ⋅ π ⋅ n + m(n) ⋅ π))is obtained with a carrier frequency fc, throughthe XN output.

An FM signal can be generated with thescheme of Fig. 2 if the frequency modulator signalis fm = m(n), the carrier frequency is a fixed valuefc, the terms φm, and Q are zero and the X0 inputis I = 1/K. The FM signal (s(n) = cos(fc ⋅ π ⋅ n +(Σm(n)) ⋅ π)) is also obtained by the output XN.

In an AM, PM, or FM modulator, it isrequired to up-sample the base-band modulatorsignal m(n) up to the sampling rate (fs) of theCORDIC processor and DAC. As this signalusually is a narrow band one, a Cascade-Integra-tor-Comb filter (CIC) [6] is a very low hardwarecost solution to perform this task.

n Figure 1. a) Rotation mode CORDIC; b) vectoring mode CORDIC.

a) b)

I K•[I•cos(θ)–Q•sin(θ)]

Q K•[I•sin(θ)+Q•cos(θ)]

q 0

X0 XN

Y0 YN

Z0 ZNRM C

ORD

IC I

Q 0

0 atan(Q/I)

X0 XN

Y0 YN

Z0 ZNVM

CO

RDIC K•√I2+Q2

n Figure 2. Generic scheme to use CORDIC in RM.

+ Z-1

θ=(Σ[fc + fm] + φm)•π

fc

fm

+

φm

+

π

x

I K•[I•cos(θ)–Q•sin(θ)]

Q K•[I•sin(θ)+Q•cos(θ)]

θ 0

X0 XN

Y0 YN

Z0 ZNRM C

ORD

IC

n Figure 3. a) DDS block diagram; b) waveforms of the LUT-based method;c) waveforms of the CORDIC-based method.

π 2π 3π

π 2π 3π

2N-1

0

a)

b)

Phaseaccumulator

fo Phaseto

amplitude

Waveform

π

-π

0

c)

VALLS LAYOUT 8/21/06 1:39 PM Page 47

Digital modulations ASK, PSK, and FSK canalso be generated with the scheme of Fig. 2 asAM, PM, and FM are, respectively, if the modu-lator signal m(n) is the digital symbol stream. Insuch a case, the baseband modulator signal doesnot need to be upsampled, but needs to keep aconstant value during the symbol time.

UP-/DOWNCONVERSION: DIGITAL MIXERS INQUADRATURE MODULATIONS

Digital up-/downconversion to/from an IF is atypical solution in SDR systems. In QAMa bit-stream is grouped in symbols, and symbols aredivided into their in-phase and quadrature com-ponents that are pulse shaped and interpolatedup to the mixer rate. In an SDR receiver, thesampled received signal is mixed, and the over-sampled in-phase and quadrature branches aredecimated and filtered by the matched filter.

The upconversion mixer, shown in Fig. 4a,can be implemented with the CORDIC RMscheme of Fig. 2. Parameters fm and φm must bezero, and the baseband in-phase and quadraturesignals si(n) and sq(n) are connected to X0 andY0 from the output XN, a scaled-by-K version ofthe mixed signal (s(n) = K ⋅ [si(n) ⋅ cos(fc ⋅ π ⋅ n)– sq(n) ⋅ sin(fc ⋅ π ⋅ n)]) is obtained.

In the receiver side, after sampling, the IFsignal is mixed. This operation, depicted in Fig.4b, can again be implemented using a CORDICRM: the received signal r(n) must be connectedto Y0, and X0 must be zeroed. The scaled-by-Kversion of the in-phase and quadrature over-sampled received signals (ri(n) = K ⋅ r(n) ⋅ cos(fc

⋅ π ⋅ n) and rq(n) = –K ⋅ r(n) ⋅ sin(fc ⋅ π ⋅ n)) areobtained from YN and XN, respectively.

Digital downconversion based on the Hilberttransform, and carrier and frequency synchro-nization are situations where complex mixing(Fig. 4c) of quadrature signals is required. Thismixing can be seen as a multiplication of a com-plex signal (I + jQ) by a complex exponentialejω: if this frequency is positive (like in up-con-version) the in-phase signal I1 is connected toX0, and the quadrature signal Q1 to Y0, and theirrespective in-phase and quadrature outputs (I2= K ⋅ [I1 ⋅ cos(fc ⋅ π ⋅ n) – Q1 ⋅ sin(fc ⋅ π ⋅ n)] andQ2 = K ⋅ [I1 ⋅ sin(fc ⋅ π ⋅ n) + Q1 ⋅ cos(fc ⋅ π ⋅ n)])are obtained from XN and YN, respectively.

When the frequency is negative (as in down-conversion) the in-phase signal I1 is connectedinto Y0 and the quadrature Q1 into X0, being thein-phase and quadrature output signals (I2 = K ⋅[Q1 ⋅ sin(fc ⋅ π ⋅ n) + I1 ⋅ cos(fc ⋅ π ⋅ n)] and Q2 =K([Q1 ⋅ cos(fc ⋅ π ⋅ n) – I1 ⋅ sin(fc ⋅ π ⋅ n)])obtained from YN and XN, respectively.

The main advantage of using CORDIC as adigital mixer with respect to the conventionalscheme of Fig. 4 (LUT-based DDS and multipli-ers) is that the multipliers and the ROM to storethe sine and cosine waveforms are avoided. Theextreme case is given by the complex mixer inwhich four multipliers and the LUT-based DDSis replaced by a single RM CORDIC.

FREQUENCY AND PHASE SYNCHRONIZATIONFirst, we deal with single-carrier modulations. InFig. 5 a block diagram of a digital IF receiver forQAM signals is shown. This scheme allows fre-quency and phase synchronization to be per-formed in baseband at a lower samplingfrequency; thus, less hardware resources areneeded. In downconversion it is usual to employfree-running oscillators (i.e., an RM CORDIC);this solution usually leaves some carrier frequencyoffset (CFO). The CFO correction is done by aquadrature complex mixer that again can beimplemented using an RM CORDIC [7]. Finally,in order to drive the complex mixer it is necessaryto estimate the CFO, which can be done by meansof a VM CORDIC at the output of the phasedetector [8]. Then the estimated CFO feeds theloop filter that controls the complex mixer.

Next, let us see how CORDIC can be used forfrequency synchronization in IEEE 802.11a wire-

IEEE Communications Magazine • September 200648

n Figure 4. a) Half mixer upconverter; b) half mixer downconverter; c) complex mixer up-/downconverter.

x

x

+

si(n)s(n)

sq(n)

DDS

a)

cos(fc•π•n) -sin(fc•π•n)

x

x

x

x

–

x

+

x

ri(n)Il(n)

Ql(n)

I2(n)

Q2(n)

r(n)

rq(n)

DDS

DDS

b) c)

cos(fc•π•n)

cos(fc•π•n)

-sin(fc•π•n)

-sin(fc•π•n) upconversionsin(fc•π•n) downconversion

n Figure 5. Scheme of a digital IF QAM receiver.

Phase detector

atan(Q/I)

VM CORDIC

Slicerr(n)

DDS

Filter anddecimation

X

RM CORDIC

DDS

Loopfilter

X

X *

RM CORDIC

VALLS LAYOUT 8/21/06 1:39 PM Page 48

IEEE Communications Magazine • September 2006 49

less LAN (WLAN)-OFDM receivers. In thisstandard data is transmitted in bursts, each pre-ceded by a preamble, and receivers can use thispreamble for frame, time, and frequency syn-chronization [9]. After downconversion to base-band, a maximum residual CFO of 200 kHz isallowed by the standard. This CFO must be esti-mated by the receiver, for example, if an autocor-relation scheme is employed to synchronize thereceiver: the position of the maximum indicateswhere each OFDM symbol begins, and its phaseis proportional to the CFO (a VM CORDIC canbe used to calculate the phase). Then an RMCORDIC can be used to correct the CFO fromthe OFDM signal (fc in the scheme of Fig. 2would be the estimated CFO). Once the CFO iscorrected, the receiver can perform a fast Fouriertransform (FFT) of each OFDM symbol to obtainthe transmitted data; to avoid errors caused by aresidual CFO from an incorrect estimation, eachOFDM symbol has four embedded pilot tones tocalculate the angle deviation [9]. This deviationcan be estimated again with a VM CORDIC andused in two ways: to rotate the 42 data pilotsfrom the current OFDM symbol, or to improveCFO correction using the estimated phase as φm(Fig. 2) in the pre-FFT RM CORDIC [10].

THE CORDIC ALGORITHMCORDIC computes a pseudo-rotation of a two-dimensional vector instead of a perfect rotation.This means that the original vector is rotated byan angle θ, and its magnitude is enlarged by aconstant factor K. The CORDIC algorithm itera-tively computes the pseudo-rotation by an angleθ with the following iterations:

Xi+1 = [Xi – di ⋅ 2–i ⋅ Yi]Yi+1 = [Yi + di ⋅ 2–i ⋅ Xi] (1)Zi+1 = Zi – di⋅ αi.

Instead of directly performing a rotation by theangle θ, CORDIC performs several microrotationsby the angles αi = ±atan(2–i). This means that therotation angle θ is broken down into a set of pre-defined angles αi, so after a number of iterationsthe angle θ is approximated by Σ(di ⋅ αi), where dibelongs to the set {–1,1}. CORDIC Eq. 1 admittwo operating modes, the rotation mode (RM)and the vectoring mode (VM) that compute theequations indicated in Fig. 1, which depend onhow the directions of the microrotations (di) arechosen: di = sign(Zi) for RM and di = –sign(Yi)for VM. A detailed explanation of how CORDICiterations are obtained can be found in [11].

IMPLEMENTATION OF CORDICThe CORDIC algorithm is easily implementedin both software and hardware. Figure 6a showsan example of CORDIC RM pseudo-code forsoftware implementation, and Fig. 6b an itera-tion stage for hardware implementation. To sat-isfy a P-bit precision CORDIC operation, P + 1iterations are needed. Furthermore, the lengthof the data path to compute the X and Y vari-ables has to be N = P + 2 + log2(P) bits, andfor the computation of Z only a precision of P +1 bits is needed in the operations.

In this section three implementation issues that

lead to enhanced performance via improving theSFDR of the generated waveform, or by reducing thecomputational load or hardware cost, are exposed.

ENHANCING THE SFDR IN DDSThe convergence range of the CORDIC algo-rithm implemented by the iterations indicated inEq. 1 is limited to the addition of all predefinedangles: ±Σα i ≈ ±1.7433. In order to useCORDIC as a phase-to-amplitude converter in aDDS the convergence range must be extendedto ±π, as shown in Fig. 3c. To accomplish thistask two approaches can be considered. The firstconsists of adding at the beginning an extra iter-ation by ±π/2, which is formulated as

X1 = –d0 ⋅ Y0,Y1 = d0 ⋅ X0,Z1 = Z0 ⋅ d0 ⋅ π/2. (2)

The second approach consists of using the fol-lowing trigonometric identities:

cos(Z – π) = –cos(Z),sin(Z – π) = –sin(Z), (3)

which allow computing an out-of-range angle bymeans of its complementary one. In such a casetwo extra two’s complementers are required afterconventional CORDIC operation together with asimple logic to detect an angle higher than ±π/2.

Although both approaches lead to the sameaim and exhibit similar computational load, thesecond achieves better SFDR than the first, dueto better CORDIC precision within convergencerange of ±1.7433. A DDS with 8-bit precisionachieves 60 dB of SFDR if the first method isused and 63 dB if the second is applied. Thisenhancement is even higher if the conventionalLUT-based quarter-wave symmetry method isutilized. A 12-bit-precision CORDIC-based DDSwith quarter-wave symmetry achieves 84 dB ofSFDR; using the second approach, it is 96 dB.

AVOIDING MULTIPLICATION BY π/2 OR πBesides the method to convert phase to ampli-tude, a difference between LUT-based and

n Figure 6. a) RM CORDIC pseudo code; b) hardware implementation of aCORDIC iteration.

±Zi+1

atan(2-1)

a) b)

for 1 = 0:P-1if z(I) >= 0

x(i+1) = x(i) – 2-i • y(i)y(i+1) = y(i) – 2-i • x(i)z(i+1) = z(i) – atan(2-i)

elsex(i+1) = x(i) + 2-i • y(i)y(i+1) = y(i) – 2-i • x(i)z(i+1) = z(i) + atan(2-i)

endend;

Zi

sign(Zi)

Xi

Yi

±Yi+1

±Yi+1

>> i

>> i

VALLS LAYOUT 8/21/06 1:39 PM Page 49

IEEE Communications Magazine • September 200650

CORDIC-based DDS is that in the first, thephase accumulator is an unsigned modulus-2N

accumulator (N-bit word length) whose outputdirectly addresses the LUT where the amplitudevalues are stored; in the second, the phase accu-mulator is a two’s complement modulus-π accu-mulator whose output directly generates thephases (in radians) that have to be converted toamplitudes by CORDIC. However, the two’scomplement modulus-π accumulator is imple-mented as a two’s complement modulus-1 accu-mulator followed by a multiplication by π [5] orby π/2, depending on if the first (Eq. 2) or sec-ond (Eq. 3) approach to extend the convergencerange is used. For clarity it is supposed that thesecond method is used. Then, in Eq. 1 each Zi isobtained as

Zi = Z′i ⋅ π/2, (4)

where Z′i is the output of the two’s complementmodulus-1 accumulator. By replacing Eq. 4 inEq. 1, the equation to compute angles remains

Z′i+1 = Z′i – diα′i,

where α′i = αi ⋅ 2/π. Therefore, now it is onlynecessary to change the set of predefined anglesto compute CORDIC, thus avoiding multiplica-tion by 2/π. An additional advantage of thismethod is that for precision lower than 15 bits,the error bound of CORDIC is reduced fromthat of the direct codification of angles.

SIMPLIFYING THECORRECTION FACTOR MULTIPLIER

As previously stated, each iteration in CORDICis not a perfect rotation since the length of thevector grows by a factor Ki = (1 + 2–2i)1/2 [12].Therefore, after N iterations its magnitude haschanged by a factor K = Π(1 + 2–2i)1/2 that con-verges to 1.6467. Therefore, in order to obtain aconstant vector length, the result has to be scaledby 1/K. CORDIC outputs can be scaled avoidinga full multiplication if the following approxima-tion is used: 1/K = 0.60725 ( 1/2((1 + 1/4) ≈ (1 –1/32)((1 + 1/256) ⋅ (1 – 1/1024), which approxi-mates the scaling factor with a precision of 16bits. Then the full multiplier can be replaced byonly four additions.

CONCLUSIONSA tutorial on how to use the CORDIC algorithmto implement different blocks found in commu-nications systems has been presented. Specifical-ly, we have shown how to use CORDIC toimplement direct digital synthesizers; AM, PM,and FM analog modulators, and ASK, PSK, andPSK modulators; up/down converters of in-phaseand quadrature signals; full mixers for complexsignals; and phase detection for synchronizers.We have also provided some tricks for efficientlyimplementing the algorithm.

ACKNOWLEDGMENTSThis research was supported by FEDER, theSpanish Ministerio de Educación y Ciencia,under grant no. TEC2005-08406-C03-01, andGeneratitat Valenciana, under Grant no.GV06/114.

REFERENCES[1] J. E. Volder, “The CORDIC Trigonometric Computing

Technique,” IRE Trans. Elect. Comp., vol. EC-8, no. 3,1959, pp. 330–34.

[2] Y. Hu, “CORDIC-based VLSI Architectures for Digital SignalProcessing,” IEEE Sig. Proc. Mag., July 1992, pp. 16–35.

[3] L. Cordness, “Direct Digital Synthesis: A Tool for Period-ic Wave Generation (Part 1),” IEEE Sig. Proc. Mag., vol.21, July 2004, pp. 50–54.

[4] J. Vankka, “Methods of Mapping from Phase to SineAmplitude in Direct Digital Synthesis,” IEEE Trans. Ultra-son. Ferroelect. Freq. Control, vol. 44, no. 2, Mar.1997, pp. 526–34.

[5] F. Cardells-Tormo and J. Valls, “Area-Optimized Imple-mentation of Quadrature Direct Digital Frequency Syn-thesizer on LUT-based FPGAs,” IEEE Trans. Circuits andSys. II: Analog and Digital Sig. Proc., vol. 50, no. 3,Mar. 2003, pp. 135–38.

[6] E. Hogenauer, “An Economical Class of Digital FiltersFor Decimation and Interpolation,” IEEE Trans. Acous-tics, Speech and Sig. Proc., vol. ASSP-29, Apr. 1981,pp. 155–62.

[7] F. Cardells et al., “Efficient FPGA-based QPSK Demodu-lation Loops: Application to the DVB standard,” LNCS,vol. 2438, Springer-Verlag, 2002, pp. 102–11.

[8] C. Dick, F. Harris, and M. Rice, “FPGA Implementationof Carrier Synchronization for QAM Receivers,” J. VLSISig. Proc., vol. 36, 2004, pp. 57–71.

[9] J. Heiskala and J. Terry, OFDM Wireless LANs: A Theo-retical and Practical Guide, SAM, 2001.

[10] M. Engels, Wireless OFDM Systems: How to MakeThem Work?, Kluwer, 2002.

[11] B. Parhami, Computer Arithmetic: Algorithmic andHardware Designs, Oxford Univ. Press, 2000.

ADDITIONAL READING[1] H. Myer, M. Moeneclaey, and S. Fechtel, Digital Com-

munication Receivers, Wiley, 1998.

BIOGRAPHIESJAVIER VALLS (jvalls@eln.upv.es) received his telecommunicationengineering degree from the Universidad Politecnica deCataluña, Spain, and his Ph.D. degree in telecommunicationengineering from the Universidad Politecnica de Valencia,Spain, in 1993 and 1999, respectively. He has been an associ-ate professor in the Department of Electronics at UniversidadPolitecnica de Valencia since 1996. His current research inter-ests include the design of FPGA-based systems, computerarithmetic, VLSI signal processing, and digital communications.

TRINI SANSALONI received her telecommunication engineeringand Ph.D. (telecommunication engineering) degrees fromthe Universidad Politecnica de Valencia in 1994 and 2001,respectively. She is an associate professor in the Depart-ment of Electronics at Universidad Politecnica de Valencia.Her current research interests include the design of FPGA-based systems and VLSI signal processing.

ASUN PÉREZ-PASCUAL received her telecommunication engi-neering and Ph.D. (telecommunication engineering) degreesfrom the Universidad Politecnica de Valencia, Spain, in 1997and 2002, respectively. She has been an associate professorin the Department of Electronics at Universidad Politecnicade Valencia since 2002. Her current research interestsinclude the design of FPGA-based systems, computer arith-metic, VLSI signal processing, and digital communications.

VICENTE TORRES received his telecommunication engineeringand Ph.D. (telecommunication engineering) degrees from theUniversidad Politecnica de Valencia in 1994 and 2001, respec-tively. He has been an associate professor in the Departmentof Electronics at Universidad Politecnica de Valencia since1995. His current research interests include the design ofFPGA-based systems, with a focus on digital communications.

VICENÇ ALMENAR received his telecommunication engineer andPh.D. degrees from the Universidad Politecnica de Valencia(UPV) in 1993 and 1999, respectively. In 2000 he spent fivemonths at the Centre for Communications Systems Research(CCSR), University of Surrey, United Kingdom, where he wasinvolved in research on digital signal processing for digitalcommunications. He is currently an associate professor inthe Department of Communications, UPV. His currentresearch interests include OFDM, MIMO, signal processing,and simulation of digital communications systems.

A DDS with 8-bit

precision achieves

60 dB of SFDR if the

first method is used,

and 63 dB if second

method is applied.

This enhancement is

even higher if the

conventional

LUT-based

quarter-wave

symmetry method

is utilized.

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