146444258 Ece III Analog Electronic Ckts 10es32 Notes

University Syllabus

PART – A

UNIT 1:

Diode Circuits: Diode Resistance, Diode equivalent circuits, Transition and diffusion capacitance, Reverse

recovery time, Load line analysis, Rectifiers, Clippers and clampers. (Chapter 1.6 to 1.14, 2.1 to 2.9)

6 Hours

UNIT 2:

Transistor Biasing: Operating point, Fixed bias circuits, Emitter stabilized biased circuits, Voltage divider

biased, DC bias with voltage feedback, Miscellaneous bias configurations, Design operations, Transistor

switching networks, PNP transistors, Bias stabilization. (Chapter 4.1 to 4.12)

7 Hours

UNIT 3:

Transistor at Low Frequencies: BJT transistor modeling, Hybrid equivalent model, CE Fixed bias

configuration, Voltage divider bias, Emitter follower, CB configuration, Collector feedback configuration,

Hybrid equivalent model. (Chapter 5.1 to 5.3, 5.5 to 5.17)

7 Hours

UNIT 4: Transistor Frequency Response: General frequency considerations, low frequency response, Miller effect

capacitance, High frequency response, multistage frequency effects. (Chapter 9.1 to 9.5, 9.6, 9.8,

9.9)

6 Hours

PART – B

UNIT 5:

(a) General Amplifiers: Cascade connections, Cascode connections, Darlington connections. (Chapter 5.19

to 5.27)

3 Hours (b) Feedback Amplifier: Feedback concept, Feedback connections type, Practical feedback circuits.

(Chapter 14.1 to 14.4) 3

Hours

UNIT 6:

Sub Code 10ES32 IA Marks 25

Hrs/ Week 04 Exam Hours 03

Total Hrs. 52 Exam Marks 100

Analog Electronic Circuits 10ES32

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Power Amplifiers: Definitions and amplifier types, series fed class A amplifier, Transformer coupled Class

A amplifiers, Class B amplifier operations, Class B amplifier circuits, Amplifier distortions. (Chapter 12.1 to

12.9)

7 Hours

UNIT 7: Oscillators: Oscillator operation, Phase shift Oscillator, Wienbridge Oscillator, Tuned Oscillator circuits,

Crystal Oscillator. (Chapter 14.5 to 14.11) (BJT version only)

6 Hours

UNIT 8: FET Amplifiers: FET small signal model, Biasing of FET, Common drain common gate configurations,

MOSFETs, FET amplifier networks. (Chapter 8.1 to 8.13)

7 Hours

TEXT BOOK:

1. ―Electronic Devices and Circuit Theory‖, Robert L. Boylestad and Louis Nashelsky, PHI/Pearson

Eduication. 9TH Edition.

REFERENCE BOOKS:

1. ‗Integrated Electronics‘, Jacob Millman & Christos C. Halkias, Tata - McGraw Hill, 1991 Edition

2. ―Electronic Devices and Circuits‖, David A. Bell, PHI, 4th Edition, 2004

3 Analog electronics circuits: A simplified approach— U B mahadevaswamy, pearson education 9 th edition.

Question Paper Pattern: Student should answer FIVE full questions out of 8 questions to be set each

carrying 20 marks, selecting at least TWO questions from each part.


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INDEX SHEET

SL.NO TOPIC PAGE NO.

1 University syllabus 04

PART A

UNIT – 1: Diode Circuits

1.1 Diode Resistance 07

1.2 Diode equivalent circuits 08

1.3 Transition and diffusion capacitance 09

1.4 Reverse recovery time 11

1.5 Load line analysis 14

1.6 Clippers and clampers 20

UNIT - 2: Transistor Biasing

2.1 Bipolar Transistor 57

2.2 Bipolar Stability 59

2.3 Fixed with Emitter 63

2.4 Voltage divider biased 64

UNIT - 3: Transistor at Low Frequencies

3.1 AC Analysis BJT transistor modeling 87

3.2 Hybrid equivalent model 90

3.3 CE Fixed bias configuration 95

3.4 Voltage divider bias 96

3.5 Emitter follower 98

3.6 CB configuration 100

UNIT - 4: Transistor Frequency Response

4.1 General frequency Response 112

4.2 Low frequency response 113

4.3 Miller effect capacitance 118

4.4 High frequency response 120

PART B

UNIT - 5: a) General Amplifiers

5.1 Amplifier Basics 132

5.2 Classification of Amplifier 133

5.3 Multistage Amplifier 134

5.4 RC couples Amplifier 140

UNIT - 5: b) Feedback Amplifiers

5.5 Feedback concept 140

5.6 Feedback connections type 142

UNIT - 6: Power Amplifiers

6.1 Definitions and amplifier types 180

6.2 Cass A amplifier 180

6.3 Transformer coupled Class A amplifiers 186

6.4 Class B amplifier operations 193

UNIT - 7: Oscillators


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7.1 Oscillator operation 209

7.2 Phase shift Oscillator 209

7.3 Wienbridge Oscillator 210

7.4 Tuned Oscillator circuits 211

7.5 Crystal Oscillator 212

UNIT - 8: FET Amplifiers

8.1 FET small signal model 222

8.2 Biasing FET 226


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Unit: 1 Hrs: 6

Diode Circuits: Diode Resistance, Diode equivalent circuits, Transition and diffusion capacitance, Reverse

recovery time, Load line analysis, Rectifiers, Clippers and clampers.

Recommended readings:

TEXT BOOK: 1. ―Electronic Devices and Circuit Theory‖, Robert L. Boylestad and Louis Nashelsky, PHI/Pearson


REFERENCE BOOKS: 1. ‗Integrated Electronics‘, Jacob Millman & Christos C. Halkias, Tata - McGraw Hill, 1991 Edition



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1.1 DIODE RESITANCE

As the operating point of a diode moves from one region to another, the resistance of the diode will also

change due to the nonlinear shape of the diode characteristic curve.

The type of applied voltage or signal will define the resistance level of interest.

Three different levels will be introduced.

DC or Static Resistance

The application of a dc voltage to a circuit containing a semiconductor diode will result in an

operating point on the characteristic curve that will not change with time.

The resistance of the diode at the operating point is simply the quotient of the corresponding levels of

VD and ID.

The dc resistance levels at the knee and below will be greater than the resistance levels obtained for the

vertical rise section of the characteristics.

The resistance levels in the reverse bias region will be high.

In general, the lower the current through a diode the higher the dc resistance level

AC Resistance

It is used to find the diode resistance when the small signal ac input voltage is applied across the

diode.

VD

ID

DC resistance Rd= VD / ID


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For small signal ac voltage, ID & VD changes around Q point which is fixed by large signal DC

voltage

The ac resistances is determined by

Drawing a tangent line at Q point

Then find the change in voltage and the current.

The ratio of this change in the voltage and the current is called ac resistance.

Average Resistance

It is used to find the diode resistance when the large signal ac input voltage is applied across the

diode.

For large signal, there is no Q point and limits of operation is large due large swing in current and

voltage.

Average resistance is ratio of change voltage to the change in current between two extreme points.

The average resistances is determined by

Drawing a straight line between two extreme voltages on characteristic curve

Then finding the difference in voltages and respective currents between the two

points.

1.2 Equivalent Circuits of Diode

Order of simplification:

Diode Characteristic Curve – Non linear graph

Ac resistance rd= ∆ Vd / ∆ Id

Q ∆ Id

∆ Vd


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Piecewise Linear Equivalent Circuit – approximate in to two lines, one horizontal and other with

slope 1/r

Simplified Equivalent Circuit – approximate in to two lines, one horizontal and other one vertical

Ideal Diode with zero voltage across diode during forward bias and zero current through diode during

reverse bias

1.3 Diode Capacitance

Ideal Equivalent circuit

Ideal diode

rave = 0, Vk =0

Simplified Equivalent Circuit

Ideal diode

rave = 0


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Two types of Diode Capacitance :

Transition Capacitance

Diffusion capacitance.

Effect of capacitance:

It is stray capacitance and has very low value

Diode becomes frequency sensitive, mainly at very high frequency.

At high frequency, Xc becomes low enough to introduce a low reactance shorting path.

Transition capacitance (CT):

Predominant effect in reverse bias condition.

Also called as ―Depletion region Capacitance or space charge capacitance

Basic capacitance eqn = ε A/d where

ε = permittivity of dielectric between the two plates

A =Area and d = distance between the plates.

Depletion region behaves like dielectric between two charged plates.

Depletion width ‗d‖ increases with increase in reverse bias.

So CT decreases as reverse bias increases.

Application Ex Schottky diode, varactor (Varicap) diodes….

CT is present in forward bias also, but is effect is neglected by the presence of larger CD

Diffusion capacitance (CD):

Predominant effect in forward bias condition.

Also called as ―Storage Capacitance‖.

Depends on rate at which charge is injected in to the PN region. (outside the depletion).

So as current increases, CD increases.

However increase in current reduces resistance. This helps in high frequency operation as T =

RC


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1.4 Reverse Recovery Time:-

Denoted by trr.

In forward bias, large number of free electrons in P region and holes in N region during conduction.

This results in minority carriers in each region

Sudden changing to reverse bias results into large reverse current due to large minority carriers. ( I

reverse = I forward)

Stays for initial storage time ts

After movement of minority carriers top other region Ir decreases to Is within time tt.

trr = ts +tt

Important in high speed switching applications

Normal value – few nanosec to 1us . Very low trr of picosecs are also available

-25 -20 -15 -10 -5 0 0.25 0.5

5

10

15

CT

Cpf

CT + CD ~ CD

CT

1uF

CD

1

D1

1N5402


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DIODE SPECIFICATIONS

Data provided by manufactures.

Must be included data :-

VF at specified temp and IF

IF max at specified temp.

IR at specified voltage and temp.

PIV or BR or PRV at specified temp

PD max = VDID

Capacitance levels

Reverse recovery time .. trr

Operating temp Range

Additional Data depends on application :-

Frequency range

Noise Level.

Switching time.

Thermal resistance levels

Peak repetitive values.

ID

t

IF

t1

ts

tt

Diode is reverse biased

Ir

Is

Desired response.

trr = ts + tt


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Diode Notation:- A & K Depends on application, manufactures, current/voltage rating

Testing can be done by using

DMM (Digital Multimeter)- with diode checking function

ohm meter

Curve Tracer

With diode checking :- Internal meter voltage is used

In one direction it shows 0.7 V as diode is forward biased

In other direction it is around 2.5V (depends on Vbattery)

With Ohm meter

One direction low resistance (RF)

Other direction it shows high resistance (RR)

With curve tracer

Characteristic curve of the diode is displayed.

Vertical axis is 1mA/div(Can be adjusted)

Horizontal axis is 100mV/div (can be adjusted)

Expensive and looks more complex.


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Load line Analysis:-

Load line - defined by the network

Characteristic curve – defined by device

V1 = VD+IDR

ID = V1/R at VD =0V

VD = V1/R at ID =0A

1. In any given circuit, check biasing of diode.

2. During forward bias (i.e diode is ON) replace diode by short for ideal diodes or with 0.7V

3. During reverse bias (i.e diode is OFF) replace diode with open circuit.

4. Do the ckt analysis and find the output voltage.

In a circuit, diode can be in Series, Parallel or Series and Parallel

Answers :-

Load line Analysis:-

R11k

+ V110V

D1

1N5402

10mA

V1

Q

Load line

Characteristic


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5.Determine the current I for each of the configurations of fig 2.150 using the approximate equivalent model

for the diode.

a) I = 0 mA; diode reverse-biased.

(b)V in loop of 20 = 20 V 0.7 V = 19.3 V (Kirchhoff‘s voltage law)

I = 19.3/20 = 0.965 A

(c)I = 10v/10 = 1 A; center branch open is open as one diode is forward biased and the other one is reverse

biased.


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6) Determine Vo and Id for the networks of fig.2.151

a)Diode forward-biased,

Kirchhoff‘s voltage law (CW):

5 V + 0.7 V Vo = 0

So Vo = 4.3 V

IR = ID = 4.3V/2.2K = 1.955 mA

(b)Diode forward-biased,

ID = (8-0.7)/ (1.2k+4.7k) = 1.24 mA

Vo = ID* 4.7 k + VD

= (1.24 mA)(4.7 k ) + 0.7 V = 6.53 V

7) Determine the level of Vo for each network of fig.2.152

a)Vo = (Vdc-VD1-VD2) = (20 V – 1 V)

= (19 V) = 9.5 V

b) I = (10-(-2)-0.7)/ (1.2+4.7)k

= (11.3/5.9) = 1.915 mA


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V = IR = (1.915 mA)(4.7 k ) = 9 V

Vo = V 2 V = 9 V 2 V = 7 V

8) Determine Vo and Id for the networks of fig.2.153.

a) Determine the Thevenin equivalent circuit for the 10mA source and 2.2 k resistor.

ETh = IR = (10 mA)(2.2 k ) = 22 V and RTh = 2.2k

So ID =22/(2.2+1.2) = 6.26 mA

Vo = ID(1.2 k ) = (6.26 mA)(1.2 k ) = 7.51 V

(b)Diode forward-biased,

ID = 20-(-5)-0.7 /6.8k= 3.57 mA

Kirchhoff‘s voltage law (CW):

Vo 0.7 V + 5 V = 0

Vo = 4.3 V

9) Determine Vo1 and Vo2 for the networks of fig.2.154.

(a)Vo1 = 12 V – 0.7 V = 11.3 V

Vo2 = 0.3 V


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(b) Vo1 = 10 V + 0.3 V + 0.7 V = 9 V

I = 9V/(1.2+3.3)k = 2 mA,

Vo2 = (2 mA)(3.3 k ) = 6.6 V

10) Determine Vo and Id for the netwoks of Fig.2.155.

(a) Both diodes forward-biased

(b) IR = (20-0.7)/4.7K = 4.106 mA

Assuming identical diodes:

ID = 4.106/2 = 2.05 mA,Vo = 20 V 0.7 V = 19.3 V

(b)Right diode forward-biased:

ID =15-(-5)-0.7 /2.2K =20/2.2 8.77 mA

Vo = 15 V 0.7 V = 14.3 V


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11) Determine Vo and I for the networks of Fig 2.156.

(a)Both diodes forward-biased

IR = (20-0.7)/4.7K = 4.106 mA

Assuming identical diodes:

ID = 4.106/2 = 2.05 mA

Vo = 20 V 0.7 V = 19.3 V

(b)Right diode forward-biased:

ID =15-(-5)-0.7 /2.2K

=20-.7/2.2 = 8.77 mA

Vo = 15 V 0.7 V = 14.3 V


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12) Determine Vo1 and Vo2 and I for the network of Fig.2.157.

Both diodes forward-biased:

Vsi = 0.7 V, Vge = 0.3 V

Vo1 = 20-0.7=19.3V Vo2 = 0.3V

Current through 1k resistor (I1)

= (20-0.7)I1 k 19.3/1k = 19.3 mA

Current through 0.7k resistor (I2)

13) Determine Vo and Id for the network of fig.2.158.

Both diodes are forward biased and parallel (in series with 2k ).

Thevinin‘s eqt circuit for this is 2k//2k with 0.7 V in series = 1kohm in series with 0.7V

So current through load resistor

= (10-0.7)/ (1+2)k = 3.1mA

ID = 3.1/ 2 = 1.55 m

Vo = 3.1mA* 2 K = 6.2V


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1.5 Clippers

A clipper is a circuit that is used to eliminate a portion of an input signal. There are two basic types of clippers: series

clippers and shunt/parallel clippers. As shown in Figure 4-1, the series clipper contains a diode that is in series with

the load. The shunt clipper contains a diode that is in parallel with the load.

FIGURE 4-1 Basic clippers.

The series clipper is a familiar circuit. The half-wave rectifier is nothing more than a series clipper. When the diode in

the series clipper is conducting, the load waveform follows the input waveform. When the diode is not conducting, the

output is approximately 0 V or fixed dc voltage which is connected in parallel. (Figure 4.2). The direction of the

diode determines the polarity of the output waveform. If the diode symbol (in the schematic diagram) points toward the

source, the circuit is a positive series clipper, meaning that it clips the positive alternation of the input. If the diode

symbol points toward the load, the circuit is a negative series clipper, meaning that it clips the negative alternation of

the input (Figure 4.11). With this di

Ideally, a series clipper has an output of when the diode is conducting (ignoring the voltage across the diode).

When the diode is not conducting, the input voltage is dropped across the diode, and .

Unlike a series clipper, a shunt clipper provides an output when the diode is not conducting. For example, refer to

Figure 4-1. When the diode is off (not conducting), the component acts as an open. When this is the case, and

form a voltage divider, and the output from the circuit is found using

When the diode in the circuit is on (conducting), it shorts out the load. In this case, the circuit ideally has an output of

. Again, this relationship ignores the voltage across the diode. In practice, the output from the circuit is

generally assumed to equal 0.7 V, depending upon whether the circuit is a positive shunt clipper or a negative shunt

clipper. The direction of the diode determines whether the circuit is a positive or negative shunt clipper. The series

current-limiting resistor ( ) is included to prevent the conducting diode from shorting out the source.

A biased clipper is a shunt clipper that uses a dc voltage source to bias the diode. A biased clipper is shown in Figure

4-2. (Several more are shown in Figures 4.9 and 4.10). The biasing voltage ( ) determines the voltage at which the

diode begins conducting. The diode in the biased clipper turns on when the load voltage reaches a value of .

In practice, the dc biasing voltage is usually set using a potentiometer and a dc supply voltage, as shown in Figure 4.10.


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FIGURE 4-2 A biased clipper.

Clippers are used in a variety of systems, most commonly to perform one of two functions:

1. Altering the shape of a waveform

2. Protecting circuits from transients

The first application is apparent in the operation of half-wave rectifiers. As you know, these circuits are series clippers

that change an alternating voltage into a pulsating dc waveform. A transient is an abrupt current or voltage spike of

extremely short duration. Left unprotected, many circuits can be damaged by transients. Clippers can be used to protect

sensitive circuits from the effects of transients, as illustrated in Figure 4.12.

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TE Department

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Syllabus:- Analog Electronic Circuit

Unit I /c:- Diode Applications - Clippers

OFF

ON,

Diode condition

Vo = VR =0V

Vo= Vin - Vd

Output voltage

IVinI < I0.7IVFor all values of Vin

Reverse Biased

IVinI > I0.7IVForward biased

Negative Cycle

Positive Cycle


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Vo

Vin0V+5V

-4.3V

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OFF

ON,

Diode condition

Vo = VR =0V

Vo= Vin – Vdc+ Vd

= 0 for +ive cycle

=-(Vin + 1.3V) in –ive

cycle

Output voltage

Vin >2V -0.7Reverse Biased

For all values of Vin

Vin <2V -0.7Forward biased

Negative Cycle

Positive Cycle


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OFF

ON,

Diode condition

Vo = VR =0V

Vo= Vin- (Vdc+0.7)

Output voltage

I Vin I<

Vdc+0.7

For all values

of Vin

Reverse

Biased

I Vin I > Vdc+0.7V

Forward biased

Negative Cycle

Positive Cycle

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Vo

Vin-5V

- 2.3V


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OFF

ON,

Diode condition

Vo = Vdc =2V

Vo= Vin- 0.7V

Output voltage

Vin> Vdc-0.7Reverse

Biased


Vin< Vdc-0.7V

Forward biased

Negative Cycle

Positive Cycle

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Vo

Vin-5V

- 4.3V

2V


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Vo

Vin

0V

+5V

4.93V

Staff: - KRS Session (Aug 08 – Dec08)

TE Department PESIT, Bangalore

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Syllabus: - Analog Electronic Circuit

Unit I /c: - Diode Applications - Clippers

OFF

ON,

Diode condition

Vo = VR =0V

Vo= Vin - Vd

Output voltage


Vin < 0.7V Reverse Biased

Vin > 0.7V Forward biased

Negative Cycle

Positive Cycle


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OFF

ON,

Diode condition

Vo = Vin.

Vo= Vd =0.7V

Output voltage

For all

values of Vin

Vin <0 .7VReverse

Biased

Vin >0.7VForward biased

Negative Cycle

Positive Cycle

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Vo

Vin

0.7V

-5V

-5V


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Vo

Vin

- 0.7V

+5V

-5V

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OFF

ON,

Diode condition

Vo = Vin

Vo= Vdc + Vd== 2+0.7 =2.7V

Output voltage


Vin < Vdc +0.7VReverse Biased

Vin > Vdc +0.7VForward biased

Negative Cycle

Positive Cycle


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Vo

Vin

2.7V

+5V

4.93V

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OFF

ON,

Diode

Vo = Vin.

Vo= -Vdc+Vd ==

-2 + 0.7 = -1.3V

Output voltage

IVinI > I(Vdc-0.7V)IReverse Biased

IVinI < I(Vdc-0. 7V)IFor all

values of Vin

Forw ard

biased

Negative CyclePositive

Cycle


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Vo

Vin

-1.3V

-5V

5V

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OFF

ON,

Diode

Vo = Vin.

Vo= Vdc- Vd == 2 -0.7

=1.3V

Output voltage


Vin > Vdc -0.7VReverse Biased

Vin < Vdc -0.7VForward biased

Negative CyclePositive Cycle


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Vo

Vin

+2.7V

-5V

-5V

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OFF

ON,

Diode

Vo = Vin.

Vo= -(Vdc+Vd)

== -2.7

Output voltage

IVinI< I(Vdc+0.7V) IFor all values of Vin

Reverse Biased

IVinI> I(Vdc+0.7V) IForward

biased



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Vo

Vin

-2.7V+5V

5V

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OFF

ON,

Diode

Vo = Vin.

Vo= -(Vdc+Vd)

== -2.7

Output voltage

IVinI< I(Vdc+0.7V) IFor all values of Vin

Reverse Biased

IVinI> I(Vdc+0.7V) IForward

biased



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Vo

Vin

-2.7V

2.7V

Clampers (DC Restorers)

A clamper is a circuit that is designed to shift a waveform above or below a dc reference voltage without altering the

shape of the waveform. This results in a change in the dc average of the waveform. Both of these statements are

illustrated in Figure 4-3. (The clamper has changed the dc average of the input waveform from 0 V to +5 V without

altering its shape.)

FIGURE 4-3 A clamper with its input and (ideal) output waveforms.

There are two basic types of clampers:

A positive clamper shifts its input waveform in a positive direction, so that it lies above a dc reference voltage.

For example, the positive clamper in Figure 4-3 shifts the input waveform so that it lies above 0 V (the dc

reference voltage).

A negative clamper shifts its input waveform in a negative direction, so that it lies below a dc reference

voltage.


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Both types of clampers, along with their input and output waveforms, are shown in Figure. The direction of the diode

determines whether the circuit is a positive or negative clamper.

Clamper operation is based on the concept of switching time constants. The capacitor charges through the diode and

discharges through the load. As a result, the circuit has two time constants:

For the charge cycle, and (where is the resistance of the diode)

For the discharge cycle, and (where is the resistance of the load)

Since is normally much greater than , the capacitor charges much more quickly than it discharges. As a result,

the input waveform is shifted as illustrated in Figure 4.16.

A biased clamper allows a waveform to be shifted above (or below) a dc reference other than 0 V. Several examples

of biased clampers are shown in Figure 4-4.

FIGURE Several biased clampers.

The circuit in Figure (a) uses a dc supply voltage (V) and a potentiometer to set the potential at the cathode of . By

varying the setting of , the dc reference voltage for the circuit can be varied between approximately 0 V and the

value of the dc supply voltage.

The zener clamper in Figure (b) uses a zener diode to set the dc reference voltage for the circuit. The dc reference

voltage for this circuit is approximately equal to . Note that zener clampers are limited to two varieties:

Negative clampers with positive dc reference voltages

Positive clampers with negative dc reference voltages


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Unit I /c:- Diode Applications - Clampers

First positive cycle:-

Diode is reverse biased and Vo= 0V.

First negative cycle:-

Diode is forward biased and capacitor is charging with very low time constant. At

negative peak, Vc=Vm.-Vdc After peak diode becomes reverse biased as

Vc>Vin.

Vo = Vin+Vc

Subsequent positive and negative cycles :- Time constant of Capacitor

discharge is very high.(=C*100k). In each negative cycle, Vc charges to max. value.

In both cycles Vo= Vin + Vc


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Positive clamper with waveform in negative side. Swing level decreases with increase in voltage. Swing level is max at

Vdc =0V. Swing level can be varied from 0V to Vm


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Diode is reverse biased and Vo= 0V.

First negative cycle:-

Diode is forward biased and capacitor is charging with very low time constant. At

negative peak, Vc=Vm.+Vdc After peak diode becomes reverse biased as

Vc>Vin.

Vo = Vin+Vc

Subsequent positive and negative cycles :- Time constant of Capacitor

discharge is very high.(=C*100k). In each negative cycle, Vc charges to max. value.

In both cycles Vo= Vin + Vc (Vin is +ivefor positve cycle and –ive for –ve cycle)


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Staff:- KRS


TE Department

PESIT, Bangalore

29



Positive clamper with waveform in positive side. Swing level increases with increase in voltage. Swing level is min at Vdc

=0V. Swing level can be varied from Vm to Vm+Vdc.


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Staff:- KRS


TE Department

PESIT, Bangalore

30




Diode is forward biased and capacitor is charging with very low time constant. At positive peak, Vc=Vm.-Vdc After peak,

diode becomes reverse biased as Vc>Vin.

Vo = Vin-Vc

Subsequent negative and positive cycles :- Time constant of Capacitor discharge is very high.(=C*100k). In each

positive cycle, Vc charges to max. value. In both cycles Vo= Vin – Vc. (Vin is +ive

for postive cycle and –ive for –ve cycle)


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Staff:- KRS


TE Department

PESIT, Bangalore

31



Negative clamper with waveform in positive side. Swing level decreases with increase in voltage. Swing level is max

Vdc =0V. Swing level can be varied from 0 to Vm


SJBIT/ECE Page 40

Staff:- KRS


TE Department

PESIT, Bangalore

32




Diode is forward biased and capacitor is charging with very low time constant. At positive peak, Vc=Vm.-Vdc After peak,

diode becomes reverse biased as Vc>Vin.

Vo = Vin-Vc

Subsequent negative and positive cycles :- Time constant of Capacitor discharge is very high.(=C*100k). In each

positive cycle, Vc charges to max. value. In both cycles Vo= Vin – Vc. (Vin is +ive

for positive cycle and –ive for –ve cycle)


SJBIT/ECE Page 41

Staff:- KRS


TE Department

PESIT, Bangalore

33



Negative clamper with waveform in negative side only. Swing level increases with increase in voltage. Swing level

is min Vdc =0V. Swing level can be varied from -Vm to -Vm +VDC).

Troubleshooting Diode Circuits

Because diodes are so common in the electronics industry, it is important to be able to troubleshoot and repair

systems that employ diodes.

Diode defects include:

• Anode-to-cathode short.

• Anode-to-cathode open.

• Low front-to-back ratio.

• Out-of-tolerance parameters.

• Tests that can performed on diodes to check for their operation are:

– Voltage measurements.

– Ohmmeter tests.

– Diode testers.

Instruments that used to measure the healthiness of diode are

Digital multimeter in diode mode

Ohm-meter ( multimeter in resistance mode)

Curve tracer


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Question paper with Solutions

Q. 1 What is the origin of diffusion capacitance. Obtain an expression for the diffusion capacitance in terms of current in a p-n diode.

(Jan 2004(6), July 2004 (6), Jan 2007 (7), July 2007 (5) ) Jan 2009 (7)

Sol.: In forward biased condition, the width of the depletion region decreases and holes from p side get diffused in 'n' side while

electrons from 'n' side move into the p-side the applied voltage increases, concentration of injected charged particles increases.

This rate of change of the injected charge with applied voltage is defined as capacitance called diffusion capaacitance.


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Q 2) Draw a double diode clipper which limits at two independent levels and explain its working. (Jan 2004(6), July 2004 (8), July 2005 (6), Jan 2007(6))


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Q. 3 Define the terms P.I.V and regulation as applied to rectifiers.

(July 2004 (4), Jan 2008 (4) , Jan 2009

Sol.: i) Peak Inverse Voltage (PIV) :

When the diode is not conducting, the reverse voltage gets applied across the diode. The peak value of such

voltage decides the peak universe voltage i.e. PIV rating of a diode.

Regulation of the output voltage:

As the load current changes, load voltage changes. Practically load voltage should remain constant So

concept of regulation is to study the effect of change in load current on the load voltage.

Q 4) Draw the piece-wise linear volt-ampere characteristics of a p-n diode. Give the circuit model for the

ON state and OFF state. Jan./Feb. – 2005, July

2007 (10).

Another way to analyse the diode circuits is to approximate the V-I characteristics of a diode using only

straight lines i.e. linear relationships. In such approximation, the diode forward resistance is neglected and

the diode is assumed to conduct instantaneously when applied forward biased voltage Vo is equal to cut-in

voltage Vy' And then it is assumed that current increases instantaneously giving straight line nahlre of V-I

characteristics. While in reverse biased condition


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when Vo < 0, the diode does not conduct at all.

Hence when diode forward resistance is assumed zero, the circuit model of diode is as shown in the

Fig. 1 (a). In reverse biased, the diode is open circuit as shown in the Fig. 1 (b). As the diode conducts at Vo

=Vy' the V-I characteristics with straight lines is as shown in the Fig. 1 (c). As the method models the diode

with the pieces of straight lines, the name given to such approximation is piecewise-linear method. The

characteristics of diode shown in the Fig. 1 (c) are called the piecewise linear diode characteristics.

Open circuit

For the clipping circuit shown incharacteristic. Assume ideal diode.

150 volts.

the following figure, obtain its transfer

The input varies linearly from 0 to(7)

Q 5) Sketch and explain the circuit of a double ended clipper using ideal p-n diodes which limit the output

between ± 10 V. (6) (July 2005(6) July 2007(10),

July 2008 (10))

Vin = Vim sin w t

During positive half cycle, the diode D becomes forward biased and conducts, only when Vin is greater

than battery voltage Vl' So as long as Vin is less that V1 both the diodes are reverse biased and output

follows input. When D1 conducts, D2 is OFF and hence the output is constant at V1 volts. This is shown in

the Fig. 2


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In case of negative half cycle, as long as Viis greater than V2' the diodes D1 and D2 both remain reverse

biased and the output follows input. Once input goes below V 2 then the diode D2 conducts and output

remains constant equal to V2' This is shown in the Fig. 3 (a) and (b).


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Q 6) Draw the bridge rectifier with capacitor filter and explain.

(July 2005(10), june 2008)


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Q 7) Explain the working of a full wove voltage doubler circuit. Jan./Feb. - 2004.Jan-

2006,July2008

Q 8) Design a power supply usinfS a FWR with capacitance filter to given an output voltage of 10V at 10mA from a 220

Hz, 50 Hz supply. The ripple factor must be less than 0.01. (Jan 2004(10))


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Q 9) For the clipping circuit shown in characteristic. Assume ideal diode.150 volts.the following figure, obtain its transferThe input

varies linearly from 0 to 7

Jan 2005 (10) July 2007 (10) Jan 2009 (10)


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Q 10) Design a full wave' rectifier with a capacitor filter to meet the following specifications.

DC output voltage = 15 volts, Load resistance = 1 kD. RMS ripple voltage on capacitor = < 1% of DC output

voltage. Assume the AC supply voltage as 230 Volts, 50 Hz. (8)


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Jan 2005(10)


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Recommended Questions

1. What do you understand by ―diffusion Capacitance? (Jan /Feb 2004, 6 marks)

2. Draw a doubl diode clipper, which limits at two independent levels and explain its operation

(Jan /Feb 2004, 6 marks)

3. what is the origin of diffusion capacitance? (July/ Aub 2004 – 6 marks)

4. Draw a double diode clipper which limits two independent levels and explain its workin?

(July/ Aub 2004 – 8 marks)

5. Draw a simple clamping circuit and explain its working?


6. Define the terms P.I.V and regulation as applied to rectifiers

(July/ Aub 2004 – 4marks)

7. Explain the validity of the piecewise linear approximation of the diode model


8. Draw the piece-wise linear volt-ampere characteristics of a p-n diode. Give the circuit model for the

ON state and OFF state.

9. Sketch and explain the circuit of a double ended clipper using ideal p-n diodes which limit the output

between +/- 10V (July / Aug 2005 – 6 marks)

10. Draw the circuit diagram ofa bridge rectifier. Plot its input and output waveforms.

(July / Aug – 2005- 10 Marks)

11. Explain diffusion capacitance? (Jan/Feb 2007, 6 marks)

12. Draw and explain a double diode clipper circuit, which limits the output at two independent levels?


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Unit: 2 Hrs: 7

Transistor Biasing: Operating point, Fixed bias circuits, Emitter stabilized biased circuits, Voltage divider

biased, DC bias with voltage feedback, Miscellaneous bias configurations, Design operations, Transistor

switching networks, PNP transistors, Bias stabilization.


TEXT BOOK:



REFERENCE BOOKS:




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2.1 Bipolar transistor biasing

DC Biasing is a static operation. It deals with setting a fixed level of the current which should flow through

the transistor with a devised fixed voltage drop across the transistor junctions.

Bias establishes the dc operating point for proper linear operation of an amplifier.

The proper flow of zero signal collector current and the maintenance of proper collector emitter voltage

during the passage of signal is known as transistor.

The purpose of dc biasing of a transistor is to obtain certain dc collector current at a certain dc collector

voltage. These values of current and voltage define the point at which transistor operates. This point is

known as operating point.

The transistor functions most linearly when it is constrained to operate in its active region. Once an operating

point Q is established, time-varying excursions of the input signal should cause an output signal of the same

wave form. If the output is not the one desired, i.e., the o/p does not suit the required conditions, the

operating point is unsatisfactory and should be relocated on the output characteristics.

Now, about choosing the operating point, we should note that the transistor cannot be operated everywhere in

the active region even if we have the liberty to choose the external circuit parameters. This is because of the

various transistor ratings which limit the range of operation. These ratings are maximum collector dissipation

Pcmax, maximum collector voltage V cmax, and maximum collector current Icmax & maximum emitter to base

voltage VEBmax.

Requirements upon biasing circuit

The operating point of a device, also known as bias point or quiescent point (or simply Q-point), is the DC

voltage and/or current which, when applied to a device, causes it to operate in a certain desired fashion.

http://en.wikipedia.org/wiki/Q-point


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1. For analog circuit operation, the Q-point is placed so the transistor stays in active mode (does not

shift to operation in the saturation region or cut-off region) when input is applied. For digital

operation, the Q-point is placed so the transistor does the contrary - switches from "on" to "off" state.

Often, Q-point is established near the center of active region of transistor characteristic to allow

similar signal swings in positive and negative directions.

2. Q-point should be stable. In particular, it should be insensitive to variations in transistor parameters

(for example, should not shift if transistor is replaced by another of the same type), variations in

temperature, variations in power supply voltage and so forth.

3. The circuit must be practical: easily implemented and cost-effective.

Note on temperature dependence

At constant current, the voltage across the emitter-base junction VBE of a bipolar transistor decreases about 2

mV for each 1°C rise in temperature. Oppositely, if VBE: is held constant and the temperature rises, IC

increases, also increasing the power consumed in the transistor, tending to further increase its temperature.

Unless steps are taken to control this positive feedback of increased temperature → increased current →

increased temperature, thermal runaway ensues. An electrical approach to avoid thermal runaway is to use

negative feedback, as described in conjunction with some of the circuits below. A different approach is to use

heat sinks that carry away the extra heat.

Comparison between various configurations for a given transistor sample

http://en.wikipedia.org/wiki/Bipolar_junction_transistor#Regions_of_operation

http://en.wikipedia.org/wiki/Thermal_runaway

http://en.wikipedia.org/wiki/Negative_feedback

http://en.wikipedia.org/wiki/Heat_sink


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2.2 BIAS STABILITY-

There are two reasons for the operating point to shift. Firstly, the transistor parameters such as β, VBE are not

the same for every transistor, even of the same type. Secondly, the

transistor parameters (β,IC0 , VBE ) are functions of temperature. It is

therefore, very important that biasing network be so designed that operating point should be independent of

transistor parameter variations.

The techniques normally used to do so maybe classified into-

1.Stabilization techniques

2. Compensation techniques

STABILITY FACTOR-

As Ic is a function of ICO , VBE, & β, it is convenient to introduce three partial derivatives of IC w.r.t these

variables. These are called stability factors S,S‘&S‘‘ and defined as follows:

S = (∂Ic / ∂ICO ) = (1+ β)[ (1+(Rb/Re))/(1+ β+(Rb/Re))]

S‘ = (∂Ic / ∂VBE ) = -β/Re [1+ β+(Rb/Re)]

S‘‘ = (∂Ic / ∂β) ≈ (Ic1/β1) [ (1+(Rb/Re))/(1+ β2+(Rb/Re))]

Types of bias circuit

The following discussion treats five common biasing circuits used with bipolar transistors:

1. Fixed bias

2. Collector-to-base bias

3. Fixed bias with emitter resistor

4. Voltage divider bias

5. Emitter bias


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Fixed bias (base bias)

Fixed bias (Base bias)

This form of biasing is also called base bias. In the example image on the right, the single power source (for

example, a battery) is used for both collector and base of transistor, although separate batteries can also be

used.

In the given circuit,

VCC = IBRB + Vbe

Therefore,

IB = (VCC - Vbe)/RB

For a given transistor, Vbe does not vary significantly during use. As VCC is of fixed value, on selection of

RB, the base current IB is fixed. Therefore this type is called fixed bias type of circuit.

Also for given circuit,

VCC = ICRC + Vce

Therefore,

Vce = VCC - ICRC

From this equation we can obtain Vce. Since IC = βIB, we can obtain IC as well. In this manner, operating

point given as (VCE,IC) can be set for given transistor.

Merits:

It is simple to shift the operating point anywhere in the active region by merely changing the base

resistor (RB).

Very few number of components are required.


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Demerits:

The collector current does not remain constant with variation in temperature or power supply voltage.

Therefore the operating point is unstable.

When the transistor is replaced with another one, considerable change in the value of β can be

expected. Due to this change the operating point will shift.

Usage:

Due to the above inherent drawbacks, fixed bias is rarely used in linear circuits, ie. those circuits which use

the transistor as a current source. Instead it is often used in circuits where transistor is used as a switch.

Collector-to-base bias

Collector-to-base bias

In this form of biasing, the base resistor RB is connected to the collector instead of connecting it to the battery

VCC. That means this circuit employs negative feedback to stabilize the operating point.

From Kirchhoff's voltage law, the voltage across the base resistor is

VRb = VCC - (IC + Ib)RC - Vbe.

From Ohm's law, the base current is

Ib = VRb / Rb.

The way feedback controls the bias point is as follows. If Vbe is held constant and temperature increases,

collector current increases. However, a larger IC causes the voltage drop across resistor RC to increase, which

in turn reduces the voltage VRb across the base resistor. A lower base-resistor voltage drop reduces the base

current, which results in less collector current, so increase in collector current with temperature is opposed,

and operating point is kept stable.

For the given circuit,

IB = (VCC - Vbe) / (RB+βRC).


http://en.wikipedia.org/wiki/Kirchhoff%27s_voltage_law

http://en.wikipedia.org/wiki/Ohm%27s_law


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Merits:

Circuit stabilizes the operating point against variations in temperature and β (ie. replacement of

transistor)

Demerits:

In this circuit, to keep IC independent of β the following condition must be met:

which is approximately the case if

β RC >> RB.

As β-value is fixed for a given transistor, this relation can be satisfied either by keeping RC fairly

large, or making RB very low.

If RC is of large value, high VCC is necessary. This increases cost as well as precautions

necessary while handling.

If RB is low, the reverse bias of the collector-base is small, which limits the range of collector

voltage swing that leaves the transistor in active mode.

The resistor RB causes an ac feedback, reducing the voltage gain of the amplifier. This undesirable

effect is a trade-off for greater Q-point stability.

Usage: The feedback also decreases the input impedance of the amplifier as seen from the base, which can

be advantageous. Due to the gain reduction from feedback, this biasing form is used only when the trade-off

for stability is warranted.

2.3 Fixed bias with emitter resistor

Fixed bias with emitter resistor


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The fixed bias circuit is modified by attaching an external resistor to the emitter. This resistor introduces

negative feedback that stabilizes the Q-point. From Kirchhoff's voltage law, the voltage across the base

resistor is

VRb = VCC - IeRe - Vbe.

From Ohm's law, the base current is

Ib = VRb / Rb.

The way feedback controls the bias point is as follows. If Vbe is held constant and temperature increases,

emitter current increases. However, a larger Ie increases the emitter voltage Ve = IeRe, which in turn reduces

the voltage VRb across the base resistor. A lower base-resistor voltage drop reduces the base current, which

results in less collector current because Ic = ß IB. Collector current and emitter current are related by Ic = α Ie

with α ≈ 1, so increase in emitter current with temperature is opposed, and operating point is kept stable.

Similarly, if the transistor is replaced by another, there may be a change in IC (corresponding to change in β-

value, for example). By similar process as above, the change is negated and operating point kept stable.


IB = (VCC - Vbe)/(RB + (β+1)RE).

Merits:

The circuit has the tendency to stabilize operating point against changes in temperature and β-value.

Demerits:



( β + 1 )RE >> RB.

As β-value is fixed for a given transistor, this relation can be satisfied either by keeping RE very large,

or making RB very low.

If RE is of large value, high VCC is necessary. This increases cost as well as precautions


If RB is low, a separate low voltage supply should be used in the base circuit. Using two

supplies of different voltages is impractical.

In addition to the above, RE causes ac feedback which reduces the voltage gain of the amplifier.


http://en.wikipedia.org/wiki/Kirchhoff%27s_voltage_law

http://en.wikipedia.org/wiki/Ohm%27s_law


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Usage:

The feedback also increases the input impedance of the amplifier as seen from the base, which can be

advantageous. Due to the above disadvantages, this type of biasing circuit is used only with careful

consideration of the trade-offs involved.

2.4 Voltage divider bias

Voltage divider bias

The voltage divider is formed using external resistors R1 and R2. The voltage across R2 forward biases the

emitter junction. By proper selection of resistors R1 and R2, the operating point of the transistor can be made

independent of β. In this circuit, the voltage divider holds the base voltage fixed independent of base current

provided the divider current is large compared to the base current. However, even with a fixed base voltage,

collector current varies with temperature (for example) so an emitter resistor is added to stabilize the Q-point,

similar to the above circuits with emitter resistor.

In this circuit the base voltage is given by:

voltage across

provided .

Also



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Merits:

Unlike above circuits, only one dc supply is necessary.

Operating point is almost independent of β variation.

Operating point stabilized against shift in temperature.

Demerits:



where R1 || R2 denotes the equivalent resistance of R1 and R2 connected in parallel.

As β-value is fixed for a given transistor, this relation can be satisfied either by keeping RE fairly

large, or making R1||R2 very low.

If RE is of large value, high VCC is necessary. This increases cost as well as precautions


If R1 || R2 is low, either R1 is low, or R2 is low, or both are low. A low R1 raises VB closer to

VC, reducing the available swing in collector voltage, and limiting how large RC can be made

without driving the transistor out of active mode. A low R2 lowers Vbe, reducing the allowed

collector current. Lowering both resistor values draws more current from the power supply

and lowers the input resistance of the amplifier as seen from the base.

AC as well as DC feedback is caused by RE, which reduces the AC voltage gain of the amplifier. A

method to avoid AC feedback while retaining DC feedback is discussed below.

Usage:

The circuit's stability and merits as above make it widely used for linear circuits.

Voltage divider with AC bypass capacitor

http://en.wikipedia.org/wiki/Series_and_parallel_circuits


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Voltage divider with capacitor

The standard voltage divider circuit discussed above faces a drawback - AC feedback caused by resistor RE

reduces the gain. This can be avoided by placing a capacitor (CE) in parallel with RE, as shown in circuit

diagram.

This capacitor is usually chosen to have a low enough reactance at the signal frequencies of interest such that

RE is essentially shorted at AC, thus grounding the emitter. Feedback is therefore only present at DC to

stabilize the operating point. Of course, any AC advantages of feedback are lost.

Of course, this idea can be used to shunt only a portion of RE, thereby retaining some AC feedback.

Emitter bias

http://en.wikipedia.org/wiki/Reactance_%28electronics%29


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When a split supply (dual power supply) is available, this biasing circuit is the most effective. The negative

supply VEE is used to forward-bias the emitter junction through RE. The positive supply VCC is used to

reverse-bias the collector junction. Only three resistors are necessary.

We know that,

VB - VE = Vbe

If RB is small enough, base voltage will be approximately zero. Therefore emitter current is,

IE = (VEE - Vbe)/RE

The operating point is independent of β if RE >> RB/β

Merit:

Good stability of operating point similar to voltage divider bias.

Demerit:

This type can only be used when a split (dual) power supply is available.

Stability factors

S (ICO) = ∆IC / ∆IC0

S (VBE) = ∆IC / ∆VBE

S (β) = ∆IC / ∆ β

Networks that are quite stable and relatively insensitive to temperature variations have

low stability factors.

The higher the stability factor, the more sensitive is the network to variations in that

parameter.

S( ICO)

• Analyze S( ICO) for

– emitter bias configuration

– fixed bias configuration

– Voltage divider configuration

For the emitter bias configuration, S( ICO) = ( β + 1) [ 1 + RB / RE] / [( β + 1) + RB / RE] If

RB / RE >> ( β + 1) , then

S( ICO) = ( β + 1)


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For RB / RE <<1, S( ICO) 1

Thus, emitter bias configuration is quite stable when the ratio RB / RE is as small as

possible.

Emitter bias configuration is least stable when RB / RE approaches ( β + 1) . Fixed bias configuration S( ICO) = ( β + 1) [ 1 + RB / RE] / [( β + 1) + RB / RE]

= ( β + 1) [RE + RB] / [( β + 1) RE + RB] By

plugging RE = 0, we get

S( ICO) = β + 1

This indicates poor stability.

Voltage divider configuration

S( ICO) = ( β + 1) [ 1 + RB / RE] / [( β + 1) + RB / RE]

Here, replace RB with Rth

S( ICO) = ( β + 1) [ 1 + Rth / RE] / [( β + 1) + Rth / RE]

Thus, voltage divider bias configuration is quite stable when the ratio Rth / RE is as small

as possible.

Physical impact

In a fixed bias circuit, IC increases due to increase in IC0. [IC = βIB + (β+1) IC0] IB is fixed by VCC and RB. Thus level of IC would continue to rise with temperature – a very unstable situation.

In emitter bias circuit, as IC increases, IE increases, VE increases. Increase in VE

reduces IB. IB = [VCC – VBE – VE] / RB. A drop in IB reduces IC.Thus, this

configuration is such that there is a reaction to an increase in IC that will tend to

oppose the change in bias conditions.

In the DC bias with voltage feedback, as IC increases, voltage across RC increases, thus

reducing IB and causing IC to reduce.

The most stable configuration is the voltage – divider network. If the condition βRE

>>10R2, the voltage VB will remain fairly constant for changing levels of IC. VBE = VB – VE, as IC increases, VE increases, since VB is constant, VBE drops making IB to fall, which will try to offset the increases level of IC.

S(VBE)


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S(VBE) = ∆IC / ∆VBE

For an emitter bias circuit, S(VBE) = - β / [ RB + (β + 1)RE]

If RE =0 in the above equation, we get S(VBE) for a fixed bias circuit as,

S(VBE) = - β / RB.

For an emitter bias,

S(VBE) = - β / [ RB + (β + 1)RE] can be rewritten as,

S(VBE) = - (β/RE )/ [RB/RE + (β + 1)]

If (β + 1)>> RB/RE, then

S(VBE) = - (β/RE )/ (β + 1) = - 1/ RE

The larger the RE, lower the S(VBE) and more stable is the system.

Total effect of all the three parameters on IC can be written as,

∆IC = S(ICO) ∆ICO + S(VBE) ∆VBE + S(β)∆β General conclusion: The ratio RB / RE or Rth / RE should be as small as possible considering all aspects of

design.


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Question paper with Solutions

Q 1) Desigh a self bias transistor circuit for a stability of s< 5. The give date is as follows: Jan 2004(8)


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Q 2) For a self bias circuit, derive an expression for the stability factor s.

July 2004(8)


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Q 4.

Jan 2005 (10) JAN2009(10)


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Q 5) In the circuit of Fig. 9 given below, Vcc = 10V, Rc = 1.5 kn, ICQ = 2 mA, VCE = 5V, VBE = 0.7 V, 0 = 50 and stability factor

S ~ 5. Find R] and R2.

July 2005 (9),July2009(9)


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Q. 6


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July 2006 (10)


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Recommended Questions

1. What are the causes of instability in a transistor? Explain them in brief.(Jan/Feb 2006, 5 marks)

2. Discuss the causes for bias instability in a transistor(July / Aug 2005, 5 marks)

3. What is meant by biasing of a transistor? List the different types of transistor biasing circuits.

4. What to do you mean by operating point of a transistor? Draw the output characteristic of transistor

with various limits of operation and explain it.

5. Differentiate the ―active region‖, ―saturating region‖ and cut off region of a transistor with the

requirement of biasing.

6. Analyze the fixed bias circuit operation and derive the expression for operating point (Iceq, Vceq)

Vce max and Ic max

7. Analyse the Emitter bias circuit operation and derive the expression for operating point (Iceq,

Vceq) Vce max and Ic max

8. What are the different areas of operation in the BJT Characteristic curve? And explain them.

9. Analyse the voltage divider bias circuit operation and derive the expression for operating point

(Iceq, Vceq) Vce max and Ic max (using both approximate and exact method)

10. List out the various types of biasing circuits and compare their merits and demerits.

11. What do you understand of designing the transistor bias circuit? List the parameters to be

calculated and list the parameters required to design.

12. What is meant by transistor switching circuit? Explain with the required biasing.

13. What do you mean by stabilization?

14. Give the essential requirements of stabilization

15. Differentiate between saturation, linear region & cutoff region of transistor operation & show this

in the characteristic curve

16. Explain the fixed bias of transistor with circuit diagram and output equations

17. What is meant by biasing of a transistor? List the different types of transistor biasing circuits

18. a) Draw the transistor amplifier with the fixed bias circuit using the given component values

Input coupling Capacitor C1 =10uF, RB= 240Kohm, RC = 22Kohm VCC= +12V Output coupling

capacitor C2 = 10uF, Beta = 50 Input signal is ac signal

b)Determining the following for the fixed bias transistor configuration

i)Ibq & Icq ii) Vceq iii) VB & Vc iv) VBC v)Ve

Recalculate for B =100 and compare the results

19. a) Draw the transistor amplifier with the Emitter bias circuit using the given component values

Input coupling Capacitor C1 =10uF, RB= 510Kohm, RC = 2.4Kohm, RE= 1.5K ohm VCC= +20V

Output coupling capacitor C2 = 10uF, Beta = 100 Input signal is ac signal

b)Determining the following for the Emitter bias transistor configuration



20. a) Draw the transistor amplifier with the voltage divider bias circuit using the given component

values

Input coupling Capacitor C1 =10uF, R1= 62Kohm, R2=9.1 kohm, RC = 3.9 k ohm, RE= 0.68 k

ohm VCC= +16V Output coupling capacitor C2 = 10uF, Beta = 80 Input signal is ac signal

b)Determining the following for the voltage divider bias transistor configuration



SJBIT/ECE Page 85


21. Explain the concept of Load line in case of transistors and thus discuss the biasing techniques

applied to NPN transistors

22. What do you mean by bias stabilization?

23. Define stability factor. Find the relationship between stability factor and Ib? What is its ideal

value?

24. Give the essential requirements of stabilization of transistor

25. Design the transistor inverter with Rb & RC , Vcc=5V to operate with saturation current of 8mA,

B=100. Use level of Ib equal to 120% Ibmax and standard resistor values.

26. Write short notes on Relay driver circuit using transistor.


SJBIT/ECE Page 86

Unit: 3 Hrs: 6

Transistor at Low Frequencies: BJT transistor modeling, Hybrid equivalent model, CE Fixed bias

configuration, Voltage divider bias, Emitter follower, CB configuration, Collector feedback configuration,

Hybrid equivalent model.


TEXT BOOK:



REFERENCE BOOKS:




SJBIT/ECE Page 87

3.1 AC Analysis of BJT transistors

Two types of analyses are usually used depending on the voltage and currents of the input ac signal

relative to the bias voltages and currents. They are small-signal analysis and large-signal analysis. In ac

analysis of BJT amplifier is done using small signal analysis,

Amplification in the AC domain

The transistor can be employed as an amplifying device. That is, the output sinusoidal signal is greater than

the input signal or the ac input power is greater than ac input power.

How the ac power output can be greater than the input ac power?

Conservation- output power of a system cannot be larger than its input and the efficiency cannot be greater

than 1.

The input dc plays an important role in the amplification and contributes in increasing its level to the ac

domain where the conversion will become as η=Po(ac)/Pi(dc)

The superposition theorem is applicable for the analysis and design of the dc & ac components of a BJT

network. It permits the separation of the analysis of the dc & ac responses of the system.

In other words, one can make a complete dc analysis of a system before considering the ac response.

Once the dc analysis is complete, the ac response can be determined by doing a complete ac analysis.

Important Parameters for the ac analysis

Zi, Zo, Av, Ai are important parameters for the analysis of the AC characteristics of a

transistor circuit.

Using equivalent circuit

Zi = Vi/Ii where Ii= (Vs-Vi)/Rsense

Where Rsense is very low value resistor

used to measure input current


SJBIT/ECE Page 88

Zo= Vo/Io where Io= (V-Vo)/Rsense

Where Rsense is very low value resistor

used to measure output current

Av = Vo/Vi

AVNL = Vo/Vi with RL = infinite

AVNL > AVLoad

Ai = Io/Ii

It also can be calculated as

Ai = -AvZi/RL

Phase Relationship

The phase relationship between input and output signal depends on the amplifier

Common – Emitter : 180 degrees

Common - Base : 0 degrees

Common – Collector: 0 degrees

AC analysis using equivalent circuit:-

Schematic symbol for the device can be replaced by this equivalent circuit. Basic methods of circuit analysis

are applied.

DC levels are important to determine the Q-point. Once determined, the DC level can be ignored in the AC

analysis of the network.

Coupling capacitors & bypass capacitor are chosen, to have a very small reactance at the frequency of

applications.

The AC equivalent of a network is obtained by:

Setting all DC sources to zero & replacing them by a short-circuit equivalent.

Replacing all capacitors by a short-circuit equivalent.

Removing all elements bypassed by short-circuit equivalent.

Redrawing the network.


SJBIT/ECE Page 89

The first step in modeling the ac behavior of the transistor is to determine its ac equivalent circuit and

use it to replace the transistor circuit symbol in the schematic. Normal circuit analysis is then performed.

To explain the transistor operation during small signal analysis, one of three models are usually used: the re

model, the hybrid π model, and the hybrid equivalent model. The re model is a reduced version of the

hybrid π model which is exclusively used for high frequency analysis.

Disadvantage

Re model- It fails to account the output impedance level of device and feedback effect from output to input.

Hybrid equivalent model-It is limited to specified operating condition in order to obtain accurate result.

A device model is a combination of properly chosen circuit elements that best approximates the

actual behavior of the device under specific operating conditions.

The subsequent figures shows an example of how a typical CE circuit is usually converted to its ac

equivalent circuit. This is achieve by setting all DC sources as ground potential (or ac ground) and capacitors

as ac shorts and with small signal ac modeling of a transistor circuit

Short out capacitors

Set Vdc to ac gnd

Re-arranging


SJBIT/ECE Page 90

3.2 The Hybrid π Model

The hybrid π model is used for high frequency modeling of the transistor. We will apply this to frequency

analysis discussions later on.

The re Model This model is more suitable for when transistor circuit is used at dc and low frequencies (e.g. audio). It‘s the

same as the hybrid π model except that the high frequency components are not included

Transistor Models

In this session, we will only be looking re model, and hybrid equivalent model..

The re transistor model

Common Base PNP Configuration

Transistor is replaced by a single diode between E & B, and control current source between B & C.

Collector current Ic is controlled by the level of emitter current Ie.

For the ac response the diode can be replaced by its equivalent ac resistance.


SJBIT/ECE Page 91

The ac resistance of a diode can be determined by the equation;

where ID is the dc current through the diode at the Q-point.

Input impedance is relatively small and output impedance quite high.

Input impedance ranges from a few Ω to max 50 Ω .

Typical values are in the M Ω .

The common-base characteristics

Voltage Gain

EI

mVre

26

CBi reZ

CBZo

re

RA

re

R

rI

RI

V

VA

rI

ZI

ZIV

RI

RI

RIV

LV

L

ee

Le

i

O

V

ee

ie

iii

Le

LC

Loo

:gain voltage

: ageinput volt

)(

: tageoutput vol


SJBIT/ECE Page 92

Current Gain

The fact that the polarity of the Vo as determined by the current IC is the same as defined by figure below.

It reveals that Vo and Vi are in phase for the common-base configuration.

Approximate model for a common-base npn transistor configuration

Example 1: For a common-base configuration in figure below with IE=4mA, =0.98 and AC signal of 2mV

is applied between the base and emitter terminal:

a) Determine the Zi b) Calculate Av if RL=0.56k

c) Find Zo and Ai

Solution:

1i

e

e

e

C

i

oi

A

I

I

I

I

I

IA

e

b b

c

ec I αI

IcI

e

common-base re equivalent cct

re

5.64

26

I

26mr Za)

E

ei

m

m

43.845.6

)56.0(98.0

r

R b)

e

Lv

kA

98.0

Ω Zc) o

i

oi

I

IA


SJBIT/ECE Page 93

Example 2: For a common-base configuration in previous example with Ie=0.5mA, =0.98 and AC signal of

10mV is applied, determine:

a) Zi b) Vo if RL=1.2k c) Av d)Ai e) Ib

Common Emitter NPN Configuration

Base and emitter are input terminals.

Collector and emitter are output terminals.

Substitute re equivalent circuit

Current through diode

Input impedance

The output graph

205.0

10 Za)

:Solution

i

m

m

I

V

e

i

88mV5

(1.2k)0.98(0.5m)

RIRI b) LeLcoV8.58

10

588A c) v

m

m

V

V

i

o

98.0A d) i

A

m

m

I

10

)98.01(5.0

)1(5.0

I-I

I-I e)

ee

ceb

bc II

bbe

bbbce

III

IIIII

)1(

ei

ei

b

ebi

eb

eei

b

be

i

ii

rZ

rZ

I

rIZ

rI

rIV

I

V

I

VZ

; 1an greater thusually

)1(

)1( that so

)1(

:ageinput volt

:impedanceinput


SJBIT/ECE Page 94

Output impedance Zo

Voltage Gain

Current Gain

re model for common-emitter

re model for common-emitter

Example 3: Given =120 and IE(dc)=3.2mA for a common- emitter configuration with ro= , determine:

a) Zi b)Av if a load of 2 k is applied c) Ai with the 2 k load

Example 4: Using the npn common-emitter configuration, determine the following if =80, IE(dc)=2 mA and

ro=40 k .

a) Zi b) Ai if RL =1.2k c) Av if RL=1.2k

bI

c

e

bIi=I

b

re model for the C-E transistor configuration

re

ro

e

0AbI

c

e

bI

i=I

b

re

ro

e

Vs=0V

= 0A

impedance)high cct,(open ΩZ

the thusignored is r if

o

o

oo rZ

e

LV

eb

Lb

i

o

V

eb

iii

Lb

Lco

Loo

r

RA

rI

RI

V

VA

rI

ZIV

RI

RIV

RIV

that so

:ageinput volt

: tageoutput vol

i

b

b

b

C

i

oi

A

I

I

I

I

I

IA

975)125.8(120

125.82.3

26

I

26mr a)

E

e

ei rZ

m

m

:Solution

15.246125.8

2

r

Rb)A

e

Lv

k

120I

IA c)

i

oi

bI

cbIi=I

b

re model for the C-E transistor configuration

re

ro

e

RL

Io

krZ

m

m

ei 04.1)13(80

132

26

I

26mr a)

E

e

:Solution

67.77

)80(2.140

40)(

)(

ib)

(cont)Solution

kk

k

Rr

r

I

Rr

Ir

A

Rr

IrI

I

I

I

IA

Lo

o

b

Lo

bo

i

Lo

boL

b

L

i

o


SJBIT/ECE Page 95

Common Collector Configuration

For the CC configuration, the model defined for the common-emitter configuration is normally applied rather

than defining a model for the common-collector configuration.

3.3 The re Transistor Model for the CE Fixed Biased Configuration

β and ro are given in spec sheet;

and re is determined from dc analysis

Ac analysis

Input impedance, Zi =Vi/Ii

From the figure, it is clear that, Ii = IRB+IB = Vi/RB+Vi/βre

= Vi(1/RB +1/βre)

Zi = Vi/Ii= (1/RB +1/βre)

i.e Zi = RB// βre Ω

6.8913

402.1vc)

kk

r

rRA

e

oL


SJBIT/ECE Page 96

Output impedance Zo=Vo/Io

By keeping Vi=0, Ii=0 So βIB =0 i.e open in output side.

Output current Io= Vo(1/ro+1/Rc)

So, Output impedance Zo = Vo/Io = Rc//ro ≈Rc when ro>>Rc or ro>10Rc

Voltage gain Av=Vo/Vi

Vo= -βIB(Rc//ro) = -β(Vi/ βre )(Rc//ro) by replacing IB= Vi/ βre

= -Vi Rc//ro /re

Av= Vo/Vi =-( Rc//ro)/re ≈ -Rc/re

-ive sign indicates the 1800 phase shift between input & output voltage signal

Current gain Ai =Io/Ii

Ii =Vi/Zi

Io=Vo/RL

Ai= Io/Ii = (Vo/RL)/(Vi/Zi)= -AvZi/RL

3.4 Ac analysis for Voltage divider circuit

Example

It is similar to that of fixed bias circuit with RB is replaced by R1//R2

So

Zi = R1//R2 //βre here R1//R2 is comparitely smaller value than that of RB in fixed n\bias. So it may not be

possible to ignore R1//R2 in calculation of Zi. So Zi with voltage divider is lesser than that of fixed bias

Zo =Rc//ro≈Rc Same as that of fixed bias.

Av =-(Rc//ro)/re ≈Rc/re Same as that of fixed bias

Hybrid Equivalent Model

The hybrid parameters: hie, hre, hfe, hoe are developed and used to model the transistor.

These parameters can be found in a specification sheet for a transistor.

• hi = input resistance

• hr = reverse transfer voltage ratio (Vi/Vo)

• hf = forward transfer current ratio (Io/Ii)


SJBIT/ECE Page 97

• ho = output conductance

General h-Parameters for any

Transistor Configuration

Vi =f1 (Ii, Vo) and Io =f2((Ii, Vo)

Vi = h11Ii+h12Vo

Io=h21Ii+h22Vo

Where

h11 = Vi/Ii with Vo=0 ie short circuit input resistance, unit Ω, & designated as hi

h12 = Vi/Vo with Ii=0 ie open circuit reverse transfer voltage ratio, unitless, & designated as hr

h21 = Io/Ii with Vo=0 ie short circuit forward transfer current ratio, unitless, & designated as hf

h22 = Vo/Io with Ii=0 ie open circuit output conductance, unit µSiemens & designated as ho

So hi,hr,hf & ho are called hybrid parameters

By placing second subscript as b for CB, c for CC and e for CE, we can get hybrid parameters for each

configuration.

Simplified General h-Parameter Model

The above model can be simplified based on these approximations:

hr =0 therefore hrVo = 0 and 1/ho = ∞

Common-Emitter h-Parameters

ac fe

hie =25mV/IBQ =hfeIBQ/IEQ

hfe =ßac


SJBIT/ECE Page 98

Common-Base h-Parameters

hib =25mV/IEQ

hib=-αac = -1

3.5 Common-Emitter (CE) Fixed-Bias Configuration

The input (Vi) is applied to the base and the output (Vo) is from the collector.

The Common-Emitter is characterized as having high input impedance and low output

impedance with a high voltage and current gain.

Determine hfe, hie, and hoe:

hfe and hoe: look in the specification sheet for the transistor or test the transistor using

a curve tracer.

hie: calculate hie using DC analysis:

hie =25mV/IBQ =hfe25mV/IEQ

Input impedance Zi = RB//hie≈ hie if RB > 10hie

Output impedance Zo= Rc//(1/ho) ≈ Rc if 10Rc << 1/ho


SJBIT/ECE Page 99

Voltage gain hie

hfeRc

hie

hohfeRcAv

)/1//(

if 1/ho>10Rc

Current gain Ai ≈hfe if RB>10hie & 1/ho>10Rc

Or Ai = -AvZi/Rc

Phase Relationship

The phase relationship between input and output is 180 degrees. The negative sign used in

the voltage gain formulas indicates the inversion.

CE – Voltage-Divider Bias Configuration

Input impedance Zi = R1//R2//hie


Voltage gain hie

hfeRc

hie

hohfeRcAv

)/1//(

if 1/ho>10Rc


SJBIT/ECE Page 100

Current gain Ai ≈hfe if RB>10hie & 1/ho>10Rc

Or Ai = -AvZi/Rc

Phase Relationship

A CE amplifier configuration will always have a phase relationship between input and

output is 180 degrees. This is independent of the DC bias.

CE Emitter-Bias Configuration

Unbypassed RE

Input impedance Zi = RB//hie+(1+hfeRE)


Voltage gain

EE

EEie

oefe

Rhfe

hie

Rc

hfeRhie

hfeRcAv

Rhfehie

hfeRc

Rhfeh

hRchAv

)1()1(

)/1//(

if 1/ho>10Rc, 1+hfe ≈hfe

Current Gain Ai =

ieCoe

oefe

hRRRh

hRRh

IiIo)2//1(()1(

1)2//1(/ = -AvZi/Rc

For Emitter follower circuit

Zi = RB//(1+ß)(re+RE) = RB// ßRE if RE > 10re & 10RE<RB ( hfe RE in hybrid eq circuit)

Zo = re//RE =re ( hie/hfe in hybrid eq ckt)

Av = RE /(re+RE) = RE/RE =1


SJBIT/ECE Page 101

3.6 For CB amplifier

Zi = RE//re =re ( hib in hybrid eq ckt)

Zo = Rc//ro=Rc

AV = Rc/re ( Rc/hib)

Effect of load resistance and source impedance:-

AvNL >AVL>AVs

Both load resistance & source impedance reduces the gain

If load resistance is very low compare to Zo, gain reduces drastically

If source impedance is very high compare to Zi gain reduces.

If we consider output equivalent circuit as voltage source with value AvNL , inseries with output

impedance Zo we can find the reduction factor as below

If AVNL is the no load gain, AVL is the gain with load RL, AVs is the gain with load and source resitance

rs

Then

RoR

R

rsZi

ZiAV

RoR

RAVAVs

rsZi

ZiAVAV

L

L

LN

L

LL

LNL


SJBIT/ECE Page 102

Question paper with solution:

Q.1 a) Draw the hybrid model of a transistor and explain the significance of each element.

Jan2004( 6),jan2006(5),july2006(5),jan2007(6)

Sol. :

hIe It is the short circuit input impedance

h 21- forward current gain

h 12 - Reverse Voltage gain

h22 - Output admittance


SJBIT/ECE Page 103


SJBIT/ECE Page 104

Q 2) State and prove Miller's theorem

(Jan2004[6],July2005(5),Jan2006,July2006,Jan2007)

Sol. : Statement: An impedance Z connected as a feedback element can be reflected towards the input port

and the output port This helps in the simplification of analysis.


SJBIT/ECE Page 105

4) Using h-parameter model for a transistor in C.E. configuration, Derive expressions for AI' Zi Av and Yo

of the amplifier.

( Jan2006(12)july2006(9),july2007(8),jun2008)

Ans. : Let us consider the h-parameter equivalent circuit for the amplifier, as shown in

the Fig. .


SJBIT/ECE Page 106


SJBIT/ECE Page 107


SJBIT/ECE Page 108

b) The transistor amplifier shown in Fig.IO uses a transistor whose h-parameters are hie = 1.1 kQ, hfe = 50,

h'e = 2.5x10-4 and l/hoe = 40 kQ. Calculate 1 Ai - -,0 Av, Avs , Ro and R

(July –Aug 2005);


SJBIT/ECE Page 109


SJBIT/ECE Page 110

Recommended Question:

1. List the three models used in small signal ac analysis of transistor and compare them.

2. Explain conversion efficiency.

3. What are the significances of transistor equivalent circuit/model?

4. Define the h-parameters and draw the small signal value for CE configuration

5. List out the various steps to get the ac equivalent circuit of transistor used in small

signal ac analysis.

6. Explain the hybrid equivalent model of transistor for both common emitter

configuration.

7. What are h-parameters? Explain them.

8. What is current gain? Derive its equation.

9. Explain the two- port systems Derive the Thevinin‘s equivalent parameters

10. Derive the Approximate and complete hybrid equivalent parameters for

i)fixed bias config

ii) Voltage divider config.

iii)Unbypassed emitter bias config

11. Compare the re model parameters and hybrid model parameters.

12. Write two port system notations for an operation amplifier with & without load.

13. State and explain the dual of Millers theorem? (Jan 2006 – 5 marks)

14. What are the advantages of h-parameters? (Jan 2006 – 5 marks)

15. Using Millers theorem, draw the equivalent circuit between C and E. Applying KcL

to the network, show that the above value of k is obtained?

16. Draw the hybrid small signal model of a transistor and explain the significance of

each component of the model?

17. Using h- parameter model for a transistor in C.E. configuration, derive expressions

for Ar, Zp, Av and Yo of the amplifier

18. Explain how h-parameter can be obtained from the static characteristics of a

transistor

19. The transistor amplifier shown in Fig.IO uses a transistor whose h-parameters are

hie = 1.1 kQ, hfe = 50, h'e = 2.5x10-4 and l/hoe = 40 kQ. Calculate 1 Ai - -,0 Av,

Avs , Ro and R


SJBIT/ECE Page 111

Unit: 4 Hrs: 6

Transistor Frequency Response: General frequency considerations, low frequency response, Miller

effect capacitance, High frequency response, multistage frequency effects.


TEXT BOOK:



REFERENCE BOOKS:




SJBIT/ECE Page 112

4.1 Frequency response:- is the study of amplifier performance over a wide range of frequencies. It is

observed that, at lower and higher frequencies, gain reduces gradually as shown below:

.

Why Av drop at lower & higher frequencies:- The decrease in gain at lower frequency is due to the effect

of network capacitors

Input coupling capacitor Ccs,

Output coupling capacitor Cco

Bypass capacitor CE

The reactance of the above capacitors is close zero at normal or higher frequencies, so considered as short

in ac analysis. However at lower frequencies, reactance is quite high compare to the resistances of the circuit

and hence can not be ignored. These reactances appear in the input, output and across emitter resistor reduces

the gain.

The reason for decrease in gain at higher frequencies is due to the interelectrode or parasitic or junction

capacitances between terminals of BJT. The value of these capacitors are very low compare to Ccs, Cco &

CE . They are in order of pF or nF. So at normal or lower frequencies, the reactance is very high and

considered as open. But at very high frequencies, the reactance decreases and appear parallel to input &

output capacitances and provides leakage path , hence voltage gain reduces.

The frequency at which gain is 1/√2 is corner frequency, break frequency or half power frequency. Lower

corner frequency is designated as f1 or fLand higher corner frequency is designated as f2 or fH. Difference

between f2 and f1 is called as bandwidth.

Semilog :- Normally we measure the amplifier gain and phase shift (on y-axis) with respect to wide range of

frequency (on x-axis). As the range of frequency is very large, log scale is used on x-axis as shown below.

Ex Range of 100 to 10

8 can be reduced to 0 to 8 if log value is considered.

• Verti

cal scale- linear scale with equal divisions


SJBIT/ECE Page 113

• The distance from log101=0 to log102 is 30% of the span.

• Important to note the resulting numerical value and the spacing, since plots will typically only have

the tic marks.

• Plotting a function on a log scale can change the general appearance of the waveform as compared to

a plot on a linear scale.

• Straight line plot on a linear scale can develop a curve on a log scale.

• Nonlinear plot on a linear scale can take on the appearance of a straight line on a log plot.

Identifying the numerical values of the tic marks

on a log scale.

Decibels:-

Term decibel is used as the fact that power and audio levels are related on a logarithmic basis. P1, P2 –

power levels.

Bel- too large unit of measurement for practical purpose. The terminal rating of electronic

communication equipment is commonly in decibels. Decibels- is a measure of the difference in

magnitude between two power levels.

Advantages of the logarithmic relationship, it can be applied to cascade stages.

In normalized graph, Y axis value is Gain / Mid band gain, so, the mid band Y value will be 1 and 0dB

if gain is taken in dB value, as shown in the following graphs.

4.2 Low frequency Analysis :- using high pass RC circuit

RC combination that will define a low-cutoff frequency.

ndBdBdBdBdB

1

210dB

600Ω

210dBm

1

210dB

1

210

G........GGGG

(dB) V

V20logG

1mW

P10logG

bel 1 dB 10 as (dB) P

P10logG and (bel)

P

PlogG

321T


SJBIT/ECE Page 114

At high frequencies,

At 0 Hz ,

So at high frequencies, Vo =Vi and at 0 Hz, Vo = 0V

A low frequency, the reactance of the capacitive becomes very large, so a significant portion of a signal

dropped across them. Then as the frequency approaches zero or at dc, the capacitive reactance approach

infinity or become an open circuit. As the frequency increases, the capacitive reactance decreases and

more of the input voltage appears across the output terminals.

At lower frequencies, as value of Xc can be ignored,

At frequency f1 Xc = R

Then

So at f1, Gain reduces by 0.707 of Av mid band.

At this frequency, f1 :-

By taking dB value

0ΩπfC2

1XC

ΩCπ(0)2

1

πfC2

1XC

XcR

RViVo

XcR

R

Vi

VoAv

22Av(mag)

CXR

RR

Xc1tanshift Phase

2

1

2Av(mag)@f

221

R

R

RR

R

RCf12

1Xc

RCfSo

2

11,

f

fshiftPhase

fffCRRXcXR

R

C

1tan

)/(1

1

)21(1

1

)(1

1ffAv(mag)at

1

2

1

22221

)/log(20ff vdB(mag)at,

/)/(1,f.....

])/(1log[10])/(1log[20)/(1

1log20fft AvdB(mag)a

11

111

2

1

2/12

12

1

1

ffAThen

fffffWhen

ffffff


SJBIT/ECE Page 115

Then draw two straight lines namely asymptotes

1) For f >f1, AvdB = 0dB Phase shift = 00

2) f ≤ f1 , find Avdb for various frequencies for f1 and below and draw the line

Frequency

Ratio f1/f AvdB=-20log f1/f Phase shift, θ= tan-1

f1/f

f1 1 0 450

f1/2 2 -6dB 63.430

f1/4 4 -12dB 75.960

f1/10 10 -20dB 84.280

f1/100 100 -40 dB 89.420

After drawing the two lines , locate -3dB point for f1 and draw the actual frequency response graph through

this -3dB point. The frequency response graph is as shown below:

The above plot is called Bode plot of the magnitude vs frequency. It is defined as the linear plot of the

asymptotes and associated break points.

A change in a frequency by a factor of 2 is one octave and a change in frequency by a factor of 10 is called

one decade.

From the table, it is clear that, as the frequency decreases, phase shift increases at lower frequencies and

approaches to 900 and for f>f1, phase shift is 0

0

Typical Bode plot for f1 = 318.5 Hz.

Steps to follow in drawing Bode plot for Av mag

1. Determine the break frequency using RC

f2

11

2. Plot f1 point on the log scale. 3. Draw straight-line segment (slope) from f1 point to -20dB at linear scale. 4. In the same figure, draw straight-line for the condition of 0dB. For f > f1 5. When f= f1 , there is a 3dB drop from the mid-band level. Plot this point.

6. Find the 3dB point corresponding to f1 and sketch the curve


SJBIT/ECE Page 116

Phase shift :- Even with the above RC circuit, phase shift

approaches to zero as f>>f1

450 when

f=f1

Approaches to 900 as f<<f1

Low frequency Response – BJT amplifier

At low frequencies Coupling capacitors (Cs, CC) and Bypass capacitors (CE) will have capacitive reactance

(XC) that affect the circuit impedances.

Coupling Capacitor - CS

→→

Cut of frequency, where,

Coupling Capacitor – CC

sis

Ls)CR(R2

1f

βre)||R||R(R 21i Rs


SJBIT/ECE Page 117

where

Bypass Capacitor - CE

Cut off frequency , where and

To find Lower corner frequency of the amplifier, f1 :- Let fLE > fLo > fLs

The Bode plot indicates that each capacitor may have a different cutoff frequency fLE, fLs, fLo

oCo r||RR)CoR(R2

1f

Lo

Lo

EeL

CR2

1f

E π )rβ

R(||RR e

sEe

21ss R||R||RR


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It is the device that has the highest of the low cutoff frequency (fL) that dominates the overall frequency

response of the amplifier (fLE).

The Bode plot not only indicates the cutoff frequencies of the various capacitors it also indicates the amount

of attenuation (loss in gain) at these frequencies.

The amount of attenuation is sometimes referred to as roll-off.

The roll-off is described as dB loss-per-octave or dB loss-per-decade.

dB/Decade refers to the attenuation for every 10-fold change in frequency. For Low Frequency Response

attenuations it refers to the loss in gain from the lower cutoff frequency to a frequency 1/10th the lower

cutoff frequency.

-dB/Octave refers to the attenuation for every 2-fold change in frequency.

For Low Frequency Response attenuations it refers to the loss in gain from the lower cutoff frequency to a

frequency 1/2 the lower cutoff frequency.

Draw the frequency response Bode plot for fLE ie. Highest frequency (among , fLE, fLs, fLo , ) by drawing

0dB line > fLE and -6db line < fLE , upto next higher frequency fLo .After this frequency , change the slope of

this line to -12dB/octave as shown in the given fig.above

Then identify -3dB point at fLE and draw a frequency response curve through this point.

4.3 Miller Effect Capacitance

Any P-N junction can develop capacitance. This was mentioned in the chapter on diodes.

In a BJT amplifier this capacitance becomes noticeable between:

the Base-Collector junction at high frequencies in CE BJT amplifier configurations and the Gate-Drain

junction at high frequencies in CS FET amplifier configurations.

It is called the Miller Capacitance. It effects the input and output circuits.

Derivation of CMi


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)1(2

1

11

)1/(

11)1(11

)11

(

21

AvCfandCfC

whereX

XRiAvXRiX

Av

RiZi

X

Av

Rivi

X

ViAvVi

Ri

Vi

X

VoVi

Ri

Vi

Zi

Vi

IIIi

Mi

Mi

CM

iCMfCfC

fCfCfC

The above expression indicates that, input capacitance is increased by (1-Av) of feedback capacitance. This

effect is more concern in inverting amplifier where Av is negative and then

CMi = (1-(-Av))Cf = (1+Av)Cf a bigger value. In non-inverting amplifier, CMi is –ive as Av>>1 So there is

no increase in input capacitance.

Derivation of CMo

))/1(1(2

1

11

)/11/(

11))/1(1(11

))/1(11

()/(

21

AvCfandCfC

whereX

XRoAvXRoX

Av

RoZo

X

Av

RoVo

X

AvVoVo

Ro

Vo

X

ViVo

Ro

Vo

Zo

Vo

IIIo

Mo

Mo

CMo

oCMfCfC

fCfCfC

From the above derivation, it is clear that, output capacitance is increased by Cf only as 1/Av <<1 so, 1-

(1/Av) ~ 1 irrespective of whether it is inverting or non inverting amplifier.

In BJT, note that the amount of Miller Capacitance is dependent on interelectrode capacitance from input to

output (Cf) and the gain (Av).

Capacitances that will affect the high-frequency response:


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• Cbe, Cbc, Cce – internal capacitances

• Cwi, Cwo – wiring capacitances

•

Ac equivalent circuit for high frequency response is as shown below

4.4 High-frequency ac equivalent model for the network

Thevenin equivalent circuit for the input circuits.

Thevenin equivalent circuits for the output circuits.

Cut-off frequency for input circuits:

Cut-off frequency for output circuits:

fvMi )CA(1C f

v

Mo )CA

1(1C

bcvbeWiMibeWi CACCCCCCi )1(

MoceWo CCCCo

iThi

HiCR2

1f

π

oTho

HoCR2

1f

π


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• fL – produce by coupling & bypass capacitor at low frequency.

• fH – produce by interelectrode capacitance at high frequency

• Dominant frequencies are referred to as the lower critical frequency fL and the upper critical

frequency fH

• fH and fL are also called the half-power frequencies because power at fH and fL are half of mid band

power as shown below.

midbandmiduencycornerfreq

midmid

uencycornerfreq

midmidband

PoViAvPo

RViAvViAv

Po

RViAvRVoPo

)2

1()*()

2

1(

/)*()2

1()

2

*(

/)*(/

2

22

2

22


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Question paper with solution

1) Draw the small signal high frequency CE significance of each component in' the model.

model for a transistor and explain the Jan 2004 (7), Jan 2008 (12)

2) Drive an expression for transistor transconductance gill and input conductance g b'e'

Jan 2004 (10), July 2007 (10)


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4 Draw hybrid-IT. model for C.E. transistor and explain the significance of each component in the model.

Jan2004 (6) Jan 2005 (6), July 2008 (6)


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5) Obtain an expression in terms of 'h' parameters for a transistor as a two-port network. Using the above

developed equations obtain the hybrid model of CE, CC and CB configurations July 2007(7),

Jan2009(6)


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6) A transistor is connected as a common emitter amplifier driving a load of 10 k. It is supplied by a source

of 1 kQ internal resistance. The 'h' parameters are hIe = 1.1 k July2007 (10)

,


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Recommended Questions:

1. Derive the low frequency analysis of transistor using bode plot. 2. What are the components determine the low frequency response.

Derive the low frequency response for loaded BJT amplifier. 3. Define the Miller effect capacitance and Derive the equation for it 4. List the factors which determine/effect the high frequency response of BJT amplifier.

Explain each


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Unit: 5 Hrs: 6

(a) General Amplifiers: Cascade connections, Cascode connections, Darlington connections.

3 Hours

(b) Feedback Amplifier: Feedback concept, Feedback connections type, Practical feedback circuits.

3 Hours


TEXT BOOK: 1. ―Electronic Devices and Circuit Theory‖, Robert L. Boylestad and Louis Nashelsky, PHI/Pearson


REFERENCE BOOKS: 1. ‗Integrated Electronics‘, Jacob Millman & Christos C. Halkias, Tata - McGraw Hill, 1991 Edition


5.1 AMPLIFIER BASICS:


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There are many situations wherein the signal picked up from a source (say a transducers) is too feeble to be

of any use and has to be magnified before it can have the capability to drive a system (say another

transducer). For example, the electrical signal produced by a microphone has to be magnified before it can

effectively drive a loudspeaker. This function of magnifying the amplitude of a given signal, without altering

its other properties is known as amplification. In any signal transmission system, amplification will have to

be done at suitable locations along the transmission link to boost up the signal level.

In order to realize the function of amplification, the transformer may appear to be a potential device.

However, in a transformer, though there is magnification of input voltage or current, the power required for

the load has to be drawn from the source driving the input of the transformer. The output power is always

less than the input power due to the losses in the core and windings. The situation in amplification is that the

input source is not capable of supplying appreciable power. Hence the functional block meant for

amplification should not draw any power from the input source but should deliver finite out power to the

load.

Thus the functional block required should have input power

Pi = Vi Ii = 0

And give the output

P0 = V0 I0 = finite

Such a functional block is called an ideal amplifier, which is shown in Fig.1 below.

Power gain is

G = P0/Pi


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The power gain of an ideal amplifier being infinite may sound like witchcraft in that something can be

produced from nothing. The real fact is that the ideal amplifier requires dc input power. It converts dc power

to ac power without any demand on the signal source to supply the power for the load.

5.2 CLASSIFICATION OF AMPLIFIERS:

Amplifiers are classified in many ways based on different criteria as given below.

I In terms of frequency range:

1. DC amplifiers. (0 Hz to 20 Hz)

2. Audio amplifiers (20 Hz to 20 KHz)

3. Radio frequency amplifiers (Few KHz to hundreds of KHz)

4. Microwave amplifiers (In the range of GHz)

5. Video amplifiers (Hundreds of GHz)

II In terms of signal strength:

1. Small signal amplifiers.

2. Large signal amplifiers.

III. In terms of coupling:

1. Direct coupling.

2. Resistance – capacitance (RC) coupling.

3. Transformer coupling.

IV. In terms of parameter:

1. Voltage amplifiers.

2. Current amplifiers.

3. Power amplifiers.

V. In terms of biasing condition:

1. Class A amplifier

2. Class B amplifier

3. Class AB amplifier

4. Class C amplifier.

VI. In terms of tuning:

1. Single tuned amplifier

2. Double tuned amplifier


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3. Stagger tuned amplifier.

DECIBEL NOTATION:

The power gain of an amplifier is expressed as the ratio of the output power to the input power. When we

have more than one stage of amplification i.e. when the output of one stage becomes the input to the next

stage, the overall gain has to be obtained by multiplying the gains of the individual stages. When large

numbers are involved, this calculation becomes cumbersome. Also, when we have passive coupling networks

between amplifier stages, there will be attenuation of the signal that is gain less than unity. To find the

overall gain of a typical multistage amplifier such as the one given

below We have to

multiply the various gains and attenuations. Moreover, when we wish to plot the gain of an amplifier versus

frequency, using large numbers for plotting is not convenient. Hence it has been the practice to use a new

unit called the decibel (usually abbreviated as dB) for measuring the power gain of a four terminal network.

The power gain in decibels is given by

G = 10 log10 P0 / Pi dB

This new notation is also significant in the field of acoustics as the response of the human ear to sound

intensity is found to be following this logarithmic pattern. The overall gain in decibel notation can be

obtained for the amplifier gain of the figure1 by simply adding the decibel gains of the individual

networks. If any network attenuates the signal, the gain will be less than the unity and the decibel gain

will be negative. Thus the overall gain for the amplifier chain shown above is given by

Overall gain = 10 – 6 + 30 – 10 + 20 = 44 dB

The absolute power level of the output of an amplifier is sometimes specified in dBm, i.e. decibels with

reference to a standard power power level, which is usually, 1 Mw dissipated in a 600 load. Therefore, if

an amplifier has 100 Mw, its power level in dBm is equal to 10 log 100/1 = 20 dBm

5.3 MULTISTAGE AMPLIFIERS:

In real time applications, a single amplifier can‘t provide enough output. Hence, two or more amplifier stages

are cascaded (connected one after another) to provide greater output Such an arrangement is known as

2


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multistage amplifier Though the basic purpose of this arrangement is increase the overall gain, many new

problems as a consequence of this, are to be taken care. For e.g. problems such as the interaction between

stages due to impedance mismatch, cumulative hum & noise etc.

MULTISTAGE VOLTAGE GAIN:

The overall voltage gain A of cascaded amplifiers as shown below, is the product of the individual gains.

(Refer to FIG.2) above.

AT = Av1 Av2 Av3 ------------------Avn

Where ‗n‘ is the number of stages.

P1: An amplifier has an input power of 5 W. The power gain of the amplifier is 40 dB.

Find the out power of the amplifier.

SOLN: Power gain in Db = 10log10 P0 / Pi = 40.

Hence P0 /Pi = antilog10 4 = 104

Output power P0 = Pi 104 = 5 10

4 W.

P2: An amplifier has at its input a signal power of 100 W and a noise power of 1 W. The amplifier has a

power gain of 20 dB. The noise contribution by the amplifier is 100 W. Find (i) the input S/N ratio (ii) out

S/N ratio (iii) noise power factor and

(iv) noise figure of the amplifier.

SOLN: Input S/N = 100/1 = 100

Power gain = 20 dB = ratio of 100

Hence output signal power = 100 100 W

Output noise power = input noise power power gain + noise of amplifier

= 1 100 + 100 = 200 W

S/N at output = 10000 / 200 = 50

Noise factor, F = (S/N)i / (S/N)0 = 100 / 50 = 2

Noise figure = 10 log F = 3 dB

DISTORTION IN AMPLIFIERS:

In any amplifier, ideally the output should be a faithful reproduction of the input. This is called fidelity. Of

course there could be changes in the amplitude levels. However in practice this never happens. The output


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waveform tends to be different from the input. This is called as the distortion. The distortion may arise either

from the inherent non – linearity in the transistor characteristics or from the influence of the associated

circuit.

The distortions are classified as:

1. Non – linear or amplitude distortion

2. Frequency distortion

3. Phase distortion

4. Inter modulation distortion

NON – LINEAR DISTORTION:

This is produced when the operation is over the non-linear part of the transfer characteristics of the transistor.

(A plot between output v/s input is called as the transfer characteristics). Since the amplifier amplifies

different parts of the input differently. For example, there can be compression of the positive half cycle and

expansion of the negative half cycle. Sometimes, the waveform can become clipped also. (Flattening at the

tips). Such a deviation from linear amplification produces frequencies in the output, which are not originally

present in the output. Harmonics (multiples) of the input signal frequency are present in the output. The

percentage harmonic distortion for the nth

Harmonic is given by

Dn = An (amplitude of the n the harmonic) 100%

A1(amplitude of the fundamental)

And the total harmonic distortion by

22

3

2

2 nT DDDD

Where 3,2 DD are harmonic components.

A distortion factor meter measures the total distortion. The spectrum or wave analyzer can be used to

measure the amplitude of each harmonic.

FREQUENCY DISTORTION:

A practical signal is usually complex (containing many frequencies). Frequency distortion occurs when the

different frequency components in the input signal are amplified differently. This is due to the various

frequency dependent reactances (capacitive & inductive) present in the circuit or the active devices (BJT or

FET).


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PHASE DISTRIBUTION:

This occurs due to different frequency components of the input signal suffering different phase shifts. The

phase shifts are also due to reactive effects and the active devices. This causes problems in TV picture

reception. To avoid this amplifier phase shift should be proportional to the frequency.

INTERMODULATION DISTORTION:

The harmonics introduced in the amplifier can combine with each other or with the original frequencies to

produce new frequencies to produce new frequencies that are not harmonics of the fundamental. This is

called inter modulation distortion. This distortion results in unpleasant hearing.

FREQUENCY RESPONSE OF AN AMPLIFIER:

Frequency response of an amplifier is a plot between gain & frequency. If the gain is constant (same) for all

frequencies of the input signal, then this plot would be a flat line. But this never happens in practice.

As explained earlier, there are different reactive effects present in the amplifier circuit and the active

devices used. Infact there are external capacitors used for blocking, capacitors etc. Also, in tuned amplifiers,

resonant LC circuits are connected in the collector circuits of the amplifier to get narrow band amplification

around the resonant frequencies.

Fig below shows a frequency response of a typical amplifier.

Where Amid = mid band voltage gain (in dB)

fL = Lower cut – off frequency. (in Hz)

fH = Upper cut - off frequency (in Hz)

3


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Usually the frequency response of an amplifier is divided into three regions. (i) The mid band region or flat

region, over which the gain is constant (ii) The lower frequency region. Here the amplifier behaves like a

high pass filter, which is shown below.

FIG .4

At high frequencies, the reactance of C1 will be small & hence it acts as a short without any attenuation

(reduction in signal voltage) (iii) In the high frequency region above mid band, the circuit often behaves like

the low pass filter as shown below.

FIG.5

As the frequency is increased, the reactance of C2 decreases. Hence more voltage is dropped across Rs and

less is available at the output. Thus the voltage gain of the amplifier decreases at high frequencies.

LOW FREQUENCY RESPONSE:

In the frequency below the mid band, the High pass filter as shown above can approximate the amplifier.

Using Laplace variable‗s‘ , the expression for output voltage can be written as:


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111

1

1

0 11

CRs

ssV

sCR

RsVsV i

i ----------- -(1)

For real frequencies (s = j = 2 f) , equation (1) becomes

AVL(jf) = 1 / (1 - jfL / f) ---------------------------------------------(2)

Where fL = 1 / (2 R1C1 ) ----------------------------------------------(3)

The magnitude of the voltage gain is given by

2

1

1

f

f

jfA

L

VL -------------------------------------------- (4)

The phase lead of the gain is given by

L = tan –1

(fL/f) -----------------------------------------------(5)

At f = fL, 707.02

1VLA

This is equal to 3 dB in log scale. For higher frequencies f >> fL, AL tends to unity. Hence, the magnitude of

AVL falls of to 70.7 % of the mid band value at f = fL, Such a frequency is called the lower cut-off or lower 3

dB frequency.

From equation (3) we see that fL is that frequency for which the resistance R1

Equals the capacitive reactance,

12

1

CfX

L

C

HIGH FREQUENCY RESPONSE:

In the high frequency region, above the mid band , the amplifier stage can be approximated by the low pass

circuit shown above.(fig 2 b). In terms complex variables, ‗s‘ , the output voltage is given by

sVCsR

sV

sCR

sCsV ii

22

2

2

20

1

1)(

1

1

)( -------------------- (6)

In terms of frequency (i.e s = j = 2 f) equation (2) becomes

2

2

0

1

1

H

fjSi

H

f

fsV

sVjfA -------------------- (7)


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Where 222

1

CRf H

The phase of the gain is given by

H = - arc tan (f / fH ) ------------------------------------(9)

At f = fH, AH = (1/ 2) AV = 0.707AV, then fH is called the upper cut off or upper 3 dB frequency. It also

represents the frequency at which the resistance R2 = Capacitive reactance of C2 = 1/ 2 fHC2.

Thus, we find that at frequencies fL & fH , the voltage gain falls to 1/ 2 of the mid band voltage gain. Hence

the power gain falls to half the value obtained at the mid band. Therefore these frequencies are also called as

half power frequencies or –3dB

Frequency since log (1/2) = -3dB.

FREQUENCY RESPONSE PLOTS:

The gain & phase plots versus frequency can be approximately sketched by using straight-line segments

called asymptotes. Such plots are called Bode plots. Being in log scale, these plots are very convenient for

evaluation of cascaded amplifiers.

BANDWIDTH:

The range of frequencies from fL to fH is called the bandwidth of the amplifier. The product of mid band gain

and the 3dB Bandwidth of an amplifier is called the Gain-bandwidth product. It is figure of merit or

performance measure for the amplifier.

5.4 RC COUPLED AMPLIFIER:


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Fig. (1) above shows a two stage RC coupled CE amplifier using BJTs where as fig.(2) shows the FET

version. The resistors RC & RB ( = R1R2 / (R1 + R2 ) and capacitors CC form the coupling network. Because of

this, the arrangement is called as RC coupled amplifier. The bypass capacitors CE (= CS) are used to prevent

loss of amplification due to –ve feedback. The junction capacitance Cj should be taken into account when

high frequency operation is considered.

When an ac signal is applied to the input of the I stage, it is amplified by the active device (BJT or FET) and

appears across the collector resistor RC / drain resistor RD. this output signal is connected to the input of the

second stage through a coupling capacitor CC. The second stage doesn‘t further amplification of the signal.

In this way, the cascaded stages give a large output & the overall gain is equal to the product of this

individual stage gains.

ANALYSIS OF TWO STAGE RC COUPLED AMPLIFIER:

This analysis is done using h parameter model. Assuming all capacitors are arbitrarily large and act as ac

short circuits across RE. The dc power supply is also replaced by a short circuit. Their h parameter

approximate models replace the transistors.

The parallel combination of resistors R1 and R2 is replaced by a single stage resistor RB.

RB = R1 || R2 = R1R2/ (R1 + R2)

For finding the overall gain of the two stage amplifier, we must know the gains of the individual stages.

Current gain (Ai2):

3


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Ai = - hfe / (1 + hoe RL)

Neglecting hoe as it is very small, Ai = -hfe

Input resistance (Ri2):

We know that Ri = hie + hreAi RL

Hence, Ri = hie and Ri2 = hie

Voltage gain (Av2):

We know that Av = Ai RL/ Ri

Av2 = - hfe RC2 / Ri2

Current gain (Ai1):

Ai1 = -hfe

Input resistance (Ri1):

Ri1 = hie

Voltage gain (Av1):

AV = Ai RL / Ri1

Here RL = RC1 || RB || Ri2

AV1 = - hfe (RC1 || RB || Ri2 ) / Ri1

Overall gain (Av ):

AV = AV1 X AV2

5.5 FEEDBACK AMPLIFIERS:

Feedback is a common phenomenon in nature. It plays an important role in electronics & control systems.

Feedback is a process whereby a portion of the output signal of the amplifier is feedback to the input of the

amplifier. The feedback signal can be either a voltage or a current, being applied in series or shunt

respectively with the input signal. The path over which the feedback is applied is the feedback loop. There

are two types of feedback used in electronic circuits. (i) If the feedback voltage or current is in phase with the

input signal and adds to its magnitude, the feedback is called positive or regenerative feedback.(ii) If the

feedback voltage or current is opposite in phase to the input signal and opposes it , the feedback is called

negative or regenerative feedback.

We will be more interested to see how the characteristics of the amplifier get modified with feedback.

5.6 CLASSIFICATION OF AMPLIFIERS:


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Before analyzing the concept of feedback, it is useful to classify amplifiers based on the magnitudes of the

input & output impedances of an amplifier relative to the sources & load impedances respectively as (i)

voltage (ii) current (iii) Tran conductance (iv) Tran resistance amplifiers.

1. VOLTAGE AMPLIFIER:

The above figure shows a Thevenin‘s equivalent circuit of an amplifier. If the input resistance of the

amplifier Ri is large compared with the source resistance Rs, then

Vi = Vs. If the external load RL is large compared with the output resistance R0 of the amplifier, then V0 =

AV VS .This type of amplifier provides a voltage output proportional to the input voltage & the

proportionality factor doesn‘t depend on the magnitudes of the source and load resistances. Hence, this

amplifier is known as voltage amplifier.

An ideal voltage amplifier must have infinite resistance Ri and zero output resistance.

2. CURRENT AMPLIFIER:

Above figure shows a Norton‘s equivalent circuit of a current amplifier. If the input resistance of the

amplifier Ri is very low compared to the source resistance RS, then Ii = IS. If the output resistance of the


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amplifier R0 is very large compared to external load RL, then IL = AiIi = Ai IS .This amplifier provides an

output current proportional to the signal current and the proportionally is dependent of the source and load

resistance. Hence, this amplifier is called a current amplifier.

An ideal current amplifier must have zero input resistance & infinite output resistance.

3. TRANSCONDUCTANCE AMPLIFIER:

The above figure shows the equivalent circuit of a transconductance amplifier. In this circuit, the output

current I0 is proportional to the signal voltage VS and the proportionality factor is independent of the

magnitudes of source and load resistances.

An ideal transconductance amplifier must have an infinite resistance Ri & infinite output

resistance R0.

4. TRANSRESISTANCE AMPLIFIER:

Figure above shows the equivalent circuit of a transconductance amplifier. Here, the output voltage V0 is

proportional to the signal current IS and the proportionality factor is independent of magnitudes of source

and loads resistances. If RS >>Ri , then Ii = IS , Output voltage V0 = RmIS .

An ideal transconductance amplifier must have zero input resistance and zero output resistance.


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THE FEEDBACK CONCEPT: In each of the above discussed amplifiers, we can sample the output voltage or current by means of a suitable

sampling network & this sampled portion is feedback to the input through a feedback network as shown

below.

All the input of the

amplifier, the feedback signal is combined with the source signal through a unit called mixer.

The signal source shown in the above figure can be either a voltage source VS or a current source.

The feedback connection has three networks.

(i) Sampling network

(ii) Feedback network

(iii) Mixer network

SAMPLING NETWORK:

There are two ways to sample the output, depending on the required feedback parameter. The output voltage

is sampled by connecting the feedback network in shunt with the output as shown in fig6.6 (a) below.

RL


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This is called as voltage sampling. If the output current is sampled by connecting feedback network in series

with the output (figure 6.6 (b)).

(ii) FEEDBACK NETWORK:

This is usually a passive two-port network consisting of resistors, capacitors and inductors. In case of a

voltage shunt feedback, it provides a fraction of the output voltage as feedback signal Vf to the input of the

mixer. The feedback voltage is given by

Vf = V0

Where is called feedback factor. It lies between 0 & 1.

(iii) MIXER:

There are two ways of mixing the feedback signal with the input signal with the input signal as shown in

figure . below.

When the feedback voltage is applied in series with the input voltage through the feedback network as shown

in figure 6.7 (a) above, it is called series mixing.

Otherwise, when the feedback voltage is applied in parallel to the input of the amplifier as shown in figure

(b) above, it is called shunt feedback.

GAIN OR TRANSFER RATIO:

The ratio of the output signal to the input signal of the basic amplifier is represented by the symbol A , with

proper suffix representing the different quantities.

Transfer ratio VAVi

V0 = Voltage gain


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Transfer ratio I

i

AI

I 0 = Current gain

Ratio m

i

GV

I 0 = Transconductance

Ratio m

i RI

V

0

= Transresistance

A suffix ‗f‘ is added to the above transfer ratios to get the corresponding quantities with feedback.

S

VfV

VA 0 = Voltage gain with feedback

S

IfI

IA 0 = Current gain with feedback

S

MfV

IG 0 = Transconductance with feedback

S

MfI

VR 0 = Transresistance with feedback

TYPES OF FEEDBACK:

Feedback amplifiers can be classified as positive or negative feedback depending on how the feedback signal

gets added to the incoming signal.

If the feedback signal is of the same sign as the incoming signal, they get added & this is called as positive

feedback. On the other hand, if the feedback signal is in phase inverse with the incoming signal, they get

subtracted from each other; it will be called as negative feedback amplifier.

Positive feedback is employed in oscillators whereas negative feedback is used in amplifiers.

FEATURE OF NEGATIVE FEEDBACK AMPLIFIERS:

1. Overall gain is reduced

2. Bandwidth is improved

3. Distortion is reduced

4. Stability is improved

5. Noise is reduced

ANALYSIS OF FEEDBACK AMPLIFIER:

The analysis of the feedback amplifier can be carried out by replacing each active element (BJT, FET) by its

small signal model and by writing Kirchoff‘s loop or nodal equations.


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Consider the schematic representation of the feedback amplifier as shown below.

The basic amplifier may be a voltage, transconductance, current or transresistance amplifier connected in a

feedback configuration as shown in figures below.


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The four basic types of feedback are:

5. Voltage –Series feedback

6. Current – Series feedback

7. Current – Shunt feedback

8. Voltage – Shunt feedback

1. GAIN WITH FEEDBACK:

Consider the schematic representation of negative feedback amplifier as shown in fig.6.8.The source

resistance RS to be part of the amplifier & transfer gain A (AV,Ai ,Gm ,

Rm ) includes the effect of the loading of the network upon the amplifier.The input signal XS, the output

signal X0, the feedback signal Xf and the difference signal Xd , each represents either a voltage or a current

and also the ratios A and as summarized below.

Table 1. Voltage and Current signals in feedback amplifiers

Signal or ratio Type of feed back

Voltage series Current series Current shunt Voltage shunt

X0

XS Xf Xd

A

β

Voltage

Voltage

AV

Vf / Vo

Current series

Voltage

Gm

Vf / Io

Current

Current

A1

If/Io

Voltage

Current

Rm

If / Vo

The gain, A = X0 / XS ---------------------------------------(1)

The output of the mixer,

Xd = Xs + (-Xf ) = Xi ----------------------------------- (2)


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The feedback ratio , = Xf / X0 ----------------------------------- (3)

The overall gain (including the feedback)

Af = X0 / XS ------------------------------------(4)

From equation (2), XS = Xi + Xf

Af = X0 / (Xi + Xf)

Dividing both numerator and denominator by Xi and simplifying, we get

Af = A / (1 + A) ----------------------------------------- (5)

Equation (5) indicates that the overall gain Af is less the open loop gain.

The denominator term (1 + A) in equation (5) is called the loop gain.

The forward path consists only of the basic amplifier, whereas the feedback is in the return path.

2.GAIN STABILITY:

Gain of an amplifier depends on the factors such as temperature, operating point

aging etc. It can be shown that the negative feedback tends to stabilize the gain.

The ratio of fractional change in amplification with feedback to the fractional change in without

feedback is called the sensitivity of the gain

Sensitivity of the gain =dA

dAf ------- (1)

Af = A

A

1 --------(2)

Differentiating equation (2) wrt A,

dAf = 2)1(

1)1(

A

AA dA =

2)1(

1

A

2)1(

1

AA

dA

f

Dividing both sides by Af , we get

2)1(

1

AA

dA

f

f.

fA

dA =

2)1(

1

A )1(

1.

)1/(( AA

dA

AA

dA --------------- (3)

i.e AA

dA

A

dA

f

f

1

1 ---------------------------- (4)

Where

f

f

A

dA = Fractional change in gain with feedback


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A

dA = Fractional change in gain without feedback.

Here A1

1 is sensitivity. The reciprocal of the sensitivity is called the desensitivity D.

The term desensitivity indicate the factor by which the gain has been reduced due to feedback.

Desensitivity, D = 1 + A ------------------------ (5)

Af = D

A

A

A

1-------------- (6)

If A >> 1, then Af = 1

------------------------(7)

Hence the gain may be made to depend entirely on the feedback network. If the feedback network contains

only stable passive elements, it is evident that the overall gain is stabilized.

The same thing can be said about all other type of feedback amplifiers.

3. REDUCTION IN FREQUENCY DISTORTION:

If the feedback network is purely resistive, the overall gain is then not a function of frequency even though

the basic amplifier gain is frequency dependent. Under such conditions a substantial reduction in frequency

& phase distortion is obtained.

4. NONLINEAR DISTORTION:

Negative feedback tends to reduce the amount of noise and non-linear distortion.

Suppose that a large amplitude signal is applied to an amplifier, so that the operation of the device extends

slightly beyond its range of linear operation and as a consequence the output signal is distorted. Negative

feedback is now introduced and the input signal is increased by the same amount by which the gain is

reduced, so that the output signal amplitude remains the same.

Assume that the second harmonic component, in the absence of feedback is B2. Because of feedback, a

component B2f actually appears in the output. To find the relationship that exists between B2f& B2, it is noted

that the output will contain the term –AβB2f , which arises from the component –βB2f that is feedback to the

input. Thus the output contains two terms: B2, generated in the transistor and –AβB2f , which represents the

effect of the feedback.

Hence B2 – AβB2f = B2f

B2f = D

B

A

B 22

1


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Thus, it is seen that, the negative feedback tends to reduce the second harmonic distortion by the factor

(1+βA).

5. NOISE:

Noise or hum components introduced into an amplifier inside the feedback loop are reduced by the feedback

loop. Suppose there are two stages of amplifier with gains A1 & A 2 and noise or hum pick-up is introduced

after the amplifier with gain A1 as shown in the fig. below

The output voltage can be expressed as

V0 = A 1 A2 VS + A2 N – A1 A2 Vf

= A1 A2 VS + A2N – A1 A2βV0

Hence V0 = NAVAAAA

S 221

21

(1

1

Therefore V0 = 121

21

1 A

NV

AA

AAS

The overall gain of the two stage amplifier is reduced by the factor 1 + A1A2β. In addition the noise output is

reduced by the additional factor A1 which is the gain that precedes the introduction of noise.

In a single stage amplifier, noise will be reduced by the factor 1/(1 + Aβ) just like distortion. But if signal-to-

noise ratio has to improve, we have to increase the signal level at the input by the factor (1 + Aβ) to bring

back the signal level to the same value as obtained without feedback. If we can assume that noise does not

further increase when we increase the signal input, we can conclude that noise is reduced by the factor

1/(1+Aβ) due to feedback while the signal level is maintained constant.

1.EFFECT ON BANDWIDTH:

The gain of the amplifier at high frequencies can be represented by the function

A =

H

mid

f

jf

A

1

--------------------------------------- (1)


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Where Amid is the mid and gain without feedback. Gain with feedback is given by

Af =

H

mid

H

mid

f

jf

A

f

jf

A

1

1

1

=

H

mid

mid

f

jfA

A

1

-------------- (2)

Dividing both numerator and denominator by (1+βAmid), we get

Af =

)1(1

1

)midH

mid

mid

Af

jf

A

A

=

Hf

midf

f

jf

A

1

----------------------------------- (3)

Where Amidf = mid band gain

= mid

mid

A

A

1 -------------------------------- (4)

And fHf = upper 3 dB frequency with feedback

= fH(1+βAmid) ------------------------------------- (5)

By a similar reasoning, we can show that the lower 3 dB frequency with feedback is given by

fLf = mid

L

A

f

1 ----------------------------------------------(6)

Thus fH is multiplied by (1+Aβ) and fL is divided by (1+Aβ).Hence the bandwidth is improved by the factor

(1+Aβ). Therefore negative feedback reduces the gain and increases the bandwidth by the same factor

(1+Aβ) resulting in a constant gain-bandwidth product. Thus one can employ negative feedback to trade gain

for bandwidth.

2. INPUT RESISTANCE:

The introduction of feedback can greatly modify the impedance levels within a circuit. If feedback signal is

added to the input in series with the applied voltage (regardless of whether the feedback signal is obtained by

sampling output current or voltage) it increases the input resistance. Since the feedback voltage V f opposes

VS, input current Ii is less than it would have been without feedback.


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On the other hand, if the feedback signal is added to the input in shunt with the applied voltage, it decreases

the input resistance. Since IS = Ii + If , then the current Ii is decreased from what it would be if thare was no

feedback current. Hence

Rif = S

i

I

V =

S

ii

I

RI is decreased because of feedback.

(A) VOLTAGE SERIES FEEDBACK

The topology of voltage series feedback is shown above, with the amplifier replaced by Thevenin‘s model.

Let AV be the open circuit voltage gain taking RS into account.

From the above figure, the input resistance with feedback is given as

Rif = i

S

I

V ---------------------------------------------------- --- (1)

Applying KVL to the input circuit, we get

VS = I i Ri + Vf

Since V f = βV0 , VS = Ii Ri + β V0 ----------------------------- (2)

But from the output circuit ,


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V0= L

LiV

RR

RVA

0

= AV Ii Ri ----------------------------------- -- (3)

= AV Vi

Where AV = L

LV

i RR

RA

V

V

0

0 ----------------------------------- (4)

Where AV is the voltage gain without feedback taking the load RL into account.

Input resistance with feedback is

Rif = i

S

I

V ------------------------------------------ ------------(5)

Substituting the value of VS from equation (2)

Rif = i

Oii

I

VRI

Since VO = AV Vi

Rif = i

iVii

I

VARI = Ri + βAVRi ------------------ (6)

Thus the negative feedback increases the Ri by a factor (1+βAV).

(B)CURRENT SERIES FEEDBACK:

The topology for this amplifier is shown above. The input resistance for this circuit is given by

Rif = i

S

I

V ------------------------------------ (1)

Applying KVL to the input circuit

VS = Ii Ri + Vf = Ii Ri + β I0 ---------------------- (2)

The output current is given by,

I0 = L

im

RR

RVG

0

0 = GMVi --------------------- (3)

Where GM = L

m

RR

RG

0

0 = iV

I 0 --------------------- (4)

Note that Gm is the short transconductance without feedback taking the load RL into account.

Input resistance with feedback is given by

Rif = i

S

I

V -------------------------------------- (5)

Substituting the value of VS from equation (2), we gat


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Rif = i

ii

I

IRI 0

Since I0 = GMVi

Rif = i

iMii

I

VGRI = Ri + βGM Ri

Rif = Ri(1+βGM) --------------------------------(6)

Hence for series mixing Rif > Ri

(C) CURRENT SHUNT FEEDBACK:

The topology

for this amplifier is shown above. Here the amplifier is replaced by by Norton‘s model .Let Ai represent

the short-circuit current gain taking RS into account.

Applying KCL to the input node

IS = Ii + If = Ii + βI0 ------------------------------------------------- (1)

Output voltage, V0 = L

ii

RR

RIA

0

0 = AIIi ---------------- (2)

Where AI = L

i

RR

RA

0

0 =

iI

I 0 ------------------------- (3)

Note that AI represents the current gain without feedback taking the load RL into account.

Input resistance with feedback is given by,

Rif = S

i

I

V --------------------------------------- (4)

Substituting the value of IS from equation (1)

Rif = 0II

V

i

i


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Since I0 = AIIi Rif =

I

i

A

R

1 ------------------------- (5)

(D) VOLTAGE- SHUNT FEEDBACK:

The topology for this configuration is shown above, in which the amplifier input circuit replaced by Norton‘s

model and output circuit replaced by Thevenin‘s model. Here Rm is the open circuit transresistance.

Applying KCL to the input node, we get

IS = Ii + If = Ii + βI0 -------------------------------- (1)

By voltage divider rule , the output voltage is given by

V0 = L

im

RR

RIR

0

0 ------------------------------------- (2)

= RM Ii ------------------------------------------- (3)

Where RM = L

m

RR

RR

0

0 = iI

I 0 ----------- ----------- (4)

is the transresistance without feedback ,taking the load RL into account.

Input resistance with feedback is given by

Rif = S

i

I

V ------------------------------------------------ (5)

Substituting the value of IS from equation (1)

Rif = 0II

V

i

i = iMi

i

IRI

V

(I0 = RMIi)


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Rif = Mi

i

RII

V

Thus Rif = M

i

R

R

1 ---------------------------------- (6)

Thus, it is evident from the above analysis that, for series configuration, the input resistance gets multiplied

by (1+ A), whereas for shunt configurations, the input resistance gets divided by (1+βA).

3. OUTPUT RESISTANCE:

It will be shown that the voltage feedback tends to decrease the output resistance whereas current feedback

tends to increase the output resistance.

(A) VOLTAGE-SERIES FEEDBACK:

In this topology, the output resistance can be measured by shorting the input source (i.e VS = 0) and looking

into the output terminals with RL disconnected as shown above.

Applying KVL to the output circuit,

AV Vi +IR0 – V = 0

Or I = 0R

VAV iV ----------------------------------------------- (1)

Since the input is shorted,

Vi = -Vf = -βV --------------------------------------------- (2)

Substituting the value of Vi = βV in equation (1), we get

I = 0R

VAV V = 0R

VAV V = 0

1

R

AV V ------------------- (3)

The the output resistance with feedback is given by

R0f = I

V

From equation (3) ,


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R0f = VA

R

1

0 ------------------------- (4)

Where AV is the open-circuit voltage gain.

The output resistance with feedback which includes RL as part of the amplifier is given by,

R‘0f = R0f I I RL = Lf

Lof

RR

RR

0

Substituting for Rof and simplifying we get,

R‘0f VA

R

1

0'

------------------------------ (5)

Where AV = L

LV

RR

RA

0


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OUTPUT RESISTANCE WITH FEEDBACK

(B) VOLTAGE SHUNT FEEDBACK:

In this topology, the output resistance can be measured by opening the input source (i.e. I0 = 0) and

looking into the output terminals with RL disconnected as shown above.

Applying KVL to the output circuit, we have

Rm Ii +IR0 = 0

0R

IRVI im ---------------------------------- (1)

Since the input is shorted

Ii = -If = -βV -------------------------------- (2)

Substituting the value of Ii in equation (1),we get

I = 0R

VRV m = 0R

VRV m = 0

1

R

RV m --------- (3)

The output resistance with feedback is given by

R = I

V

From equation (3) ,

Rof = mR

R

1

0 --------------------------- (4)

Rm is the open loop transresistance without taking RL into account.

The output resistance with feedback which includes RL as part of the amplifier is given by,


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R‘0f = Rof I I RL = Lf

Lf

RR

RR

0

0 --------(5)

From equation (4),

R‘0f = L

L

m

mR

RR

R

R

R

1

1

0

0

= mL

L

RRR

RR

10

0

Dividing Numerator and Denominator by (R0 +RL), we get

R‘0f =

L

Lm

L

L

RR

RR

RR

RR

0

0

0

1

Since R‘of = R0 I I RL is the output resistance without feedback

R‘0f =

L

Lm

RR

RR

R

0

0'

1

= MR

R

1

0'

------------------------------ (6)

Where RM = L

Lm

RR

RR

0

is the transresistance without feedback taking the load into account.

(C). CURRENT SHUNT FEEDBACK:


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In this topology, the output resistance can be measured by opening the input source .i.e. IS = 0 and looking

into the output terminals, with load RL disconnected as shown in the above figure.

Applying KCL to the output node,

I = 0R

V - Ai Ii ------------------------------ (1)

The input current is given by

Ii = -If = 0I ( 0SI )

But I = -I0 , Ii = I ------------------------(2)

Substituting the value of Ii in equation (1), we get

I = IAR

Vi

0

I(1+ iA ) = 0R

V ----------------------------(3)

Output resistance with feedback is given by ,

R0f = I

V

From equation (3)

Rof = R0 A1 ---------------------------- (4)

Ai is the short circuit gain without taking load RL into account.

The output resistance accounting for RL, is given by

R‘of = R0f I I RL = Lof

Lof

RR

RR -----------(5)

From equation (4),

R‘0f = Li

Li

RAR

RAR

1

1

0

0 = oiL

iL

RARR

ARR

0

0 )1(

Dividing Numerator and Denominator by (R0 + RL) , we get

R‘of =

L

i

L

Li

RR

RA

RR

RRA

0

0

0

0

1

1

Since R‘0 = R0 I I RL is the output resistance without feedback.


SJBIT/ECE Page 163

R‘of =

L

i

i

RR

RA

AR

0

0

0'

1

)1(

= I

i

A

AR

1

10'

---------------------------------(6)

Where AI = L

i

RR

RA

0

0 is the current gain without feedback taking the load RL into account.

(D) CURRENT SERIES FEEDBACK:

In this topology, the output resistance can be measured by shorting the input source (i.e VS = 0) and

looking into the output terminals with RL disconnected. As shown above.

Applying KCL to the output node

I = imVGR

V

0

-------------------------- (1)

The input voltage is given by

Vi = -Vf = 0I

Since I = -I0,Vi = I ------------------------------- (2)

Substituting the value of Vi from equation (2) in equation (1), we get

I = IGR

Vm

0


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or I(1+Gm ) = 0R

V ------------------(3)

The output resistance with feedback given by

R0f = I

V

From equation (3), Rof = Ro(1+ mG ) -----------------------(4)

Where Gm is the short circuit transconductance without taking RL into account.

The output resistance R‘of which includes RL as part of the amplifier is given by

R‘of = Rof I I RL = Lf

Lf

RR

RR

0

0 ---------------------(5)

From equation (4)

R‘0f = Lm

Lm

RGR

RGR

1

1

0

0

= 00

01

RGRR

RRG

mL

Lm

Dividing numerator and denominator by (R0 +RL), we get

R‘0f =

L

m

L

Lm

RR

RG

RR

RRG

0

0

0

0

1

1

Since R‘0f = R0 I I RL is the output resistance of the amplifier without feedback

R‘0f =

L

m

m

RR

RG

GR

0

0

'

0

1

1

= M

m

G

GR

1

10'

---------------------------------------------- (6)

Where GM =L

m

RR

RG

0

0 is the transconductance without feedback taking the load RL into account.


SJBIT/ECE Page 165

PROBLEMS

P1. An amplifier has an open loop gain of 500 and a feedback of 0.1.If open loop gain changes by 20%

due to change in the temperature, find the %change in the closed loop gain .

SOLN: Given A = 500, β= 0.1 & 20A

dA

Change in closed loop gain AA

dA

A

dA

f

f

1

1

= 20 X 1.05001

1

X = 0.3921 or 39.21%

P2. An amplifier has a voltage gain of 200.The gain is reduced to 50, when negative feedback is applied.

Determine the reverse transmission factor and express the amount of feedback in dB.

SOLN: Given A = 200, Af = 50

We know Af = A

A

1

i.e. 50 = 2001

200

015.0

Feedback factor in dB

N = 20 log10 A

A f = 20 log10

A1

1

= 20 log10 015.02001

1

X

= -12.042 dB.

P3.


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For the circuit shown above with RC = 4K , RL = 4K , RB = 20K , RS = 1K and the transistor

parameters are hie = 1.1 K , hfe = 50, hre = 2.5 X 10-4

and hoe = 24 µS. Find the (a) current gain (b) voltage

gain (c) transconductance (d) transresistance. (e) the input resistance seen by the source and (f) the output

resistance seen by the load. Neglect all capacitive effects.

SOLN: The ac equivalent circuit is shown below.

(a) From the above circuit,

Current gain Ai = S

L

I

I =

S

i

I

I.

i

b

I

I.

b

L

I

I

Where iS

S

S

i

RR

R

I

I

And input resistance

Ri = Rb I I hie = 20K I I 1.1 K

= 1.120

1.120X = 1.04 K

Then KK

K

I

I

S

i

04.11

1 =

04.2

1

ieB

B

i

b

hR

R

I

I = 0.95

LC

C

fe

b

L

RR

Rh

I

I = -50 X

44

4 = -25

Ai = 65.112595.004.2

1XX

I

I

S

L

RL


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(b)Voltage gain, AV = SV

V0 = SS

LL

RI

RI = Ai 6.46

1

465.11

K

K

R

R

S

L

(c) Transconductance:

Gm =LSSLS

L

RX

V

V

VR

V

V

I 11. 00

= AV X K

XRS 4

16.46

1

= -11.65 mA/V

(.d) Transresistance:

Rm = S

S

S

S

S V

VRV

V

R

I

V 0

0

0 ..

= 1K X (-46.6) = -46.6K

(e).Input resistance:

Ri = RB I I hie = 20K I I 1.4K = 1.04K

(f) Output resistance:

R0 = RC I I eh0

1 = 4K I I 40K = 3.64 K

P4. An amplifier with open loop voltage gain, AV = 1000 100 is available .It is necessary to have an

amplifier where voltage gain varies by no more than %1.0 .

Find the (a) feedback ratio and (b) the gain with feedback.

SOLN: Given AV = 1000 100 , %1.0f

f

A

dA

(a) A

dA

AA

dA

f

f

1

1

Substituting the values

10

1

1

1

1000

100

1

1

100

1.0X

AX

A

1001 A and 099.01000

99

(b) Voltage gain with feedback


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Af = 101000099.01

1000

1 XA

A

P5. An amplifier without feedback gives a fundamental output of 36 V with 7% second harmonic distortion

when the input is 0.028 V.

9. If 1.2% of the output is fedback to the input in a negative series feedback circuit , what is the output

voltage?

10. If the fundamental output is maintained at 36 V but the second harmonic distortion is reduced to 1%,

what is the input voltage?

SOLN: Given V0 = 36V, Vi = 0.028V

Vf = 1.2% , fD

D

0

=7

(a) Voltage gain, A = 1285028.0

360

iV

V

Feedback ratio, β = 012.0100

2.1

0V

V f

Af = 2.781285012.01

1285

1 XA

A

Output voltage, V0f = A fVS = 78.2 X 0.028 = 2.19V

(b)If the output is maintained constant at 36 V, then the distortion generated by

The device is unchanged. The reduction in the total distortion is due to feedback.

D0f = A

D

1

6A

Af = 7

1285

1 A

A

VS =

7

1285

360

fV

V = 0.196 V

710 fD

DA


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P.6 The output resistance of a voltage series feedback amplifier is 10 .If the gain of the basic amplifier is

100 and the feedback fraction is 0.01, what is the output resistance of the amplifier with out feedback ?.

SOLN: Given R0f = 10 A = 100, β = 0.01.

R0f = A

R

1

0

With out feedback, R0 = R0f (1+βA) = 10 (1+0.01 X 100) = 20 .

P7. The input and output voltages of an amplifier are 1mV& 1V respectively. If the gain with negative

feedback is 100 and input resistance without feedback (Voltage series feedback) is 2 K .Find the feedback

fraction and input resistance with feedback.

SOLN: Given VS = 1mV, V0=1V, Af = 100, Ri = 2K .

Open circuit voltage gain, A = 10001

10

mV

V

V

V

S

Gain with feedback, Af = A

A

1

(1+βA) = 10100

1000

fA

A

= 0.009

Input resistance with feedback, Rif = Ri(1+βA)

= 2K X 10 = 20

P8. If an amplifier has a bandwidth of 200 KHz and voltage gain of 80.What will be the new bandwidth

and gain if 5% negative feedback is introduced ?.

SOLN: Given BW = 200 KHz, A = 80, β = 5% = 0.05.

Af = 168005.01

80

1 XA

A

BWf = (1+βA) BW = (1+80X0.05)200 X 103 = 1MHz.

P9. An amplifier has a normal gain of 1000 and harmonic distortion of 10%. If 1% inverse feedback is

applied, find the gain with feedback and the distortion in the presence of feedback.

SOLN: Feedback factor, β= 01.0100

1


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Gain with feedback,Af = 9.9001.010001

1000

1 XA

A

Distortion with feedback, Df = A

D

1

= %909.0100001.01

10

X

P10. An amplifier gain changes by %10 .Using negative feedback, the amplifier is to be modified to yield a

gain of 100 with %1.0 variation. Find the required open loop gain of the amplifier and the amount of

negative feedback.

SOLN: We have A

XA

dA

A

dA

f

f

1

1

Improvement in gain stability = 1+βA = 100%1.0

%10

f

f

A

dAA

dA

Hence, Open loop gain = (Closed loop gain )(1+βA)

= (100)100 = 104

Amount of negative feedback required .0099.010

)11004A

A

P11. An amplifier with an open loop voltage gain of 2000 delivers 20 W of power at 10% second harmonic

distortion when input signal is 10 mV. If 40 dB negative voltage series feedback is applied and the out power

is to remain at 10W, determine the (a) required input signal (b) percentage harmonic distortion.

SOLN: (a) -40 A

dB1

1log20 10

= -20log10 A1

1001 A

20100

200

1 A

AA f

When the amplifier delivers 20W, it‘s output voltage is‘

V0 = A X VS = 2000 X (10 X 10-3

) = 20 W.


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If the output power is to remain at 10W, then the output voltage also must remain at 10W. Hence the

input signal required when feedback is applied will be‘

VS = VA

V

f

120

200

(b)The distortion of the amplifier with feedback will be reduced by the factor A1 .

Df = %1.0100

%10


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Question paper with solutions:

1) With a neat sketch, describe the concept of feedback in amplifiers. Jan2004 [5]

Sol.: Feedback is process where in a fast of output parameter is fed back either in series or in shunt with the

input parameter to have the advantage

2) Using the block diagram approach, derive an expression for i) input impedance of voltage series

feedback amplifie rii) out put impedance of current shunt feedback amplifier


SJBIT/ECE Page 173

Jan 2004(10), July 2005 (8), Jan 2008 (8)

Sol. : i) Input impedance of voltage series.

3) Draw a feedback amplifier in block diagram form. Identify each block and explain its


SJBIT/ECE Page 174

function. Jan 2006 (8)


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4) Derive an expression for the input resistance of a voltage series feedback topology.

July2004 (5) July 2005(5), Jan 2008 (6)

The voltage series feedback topology shown in Fig. 23 with amplifier is replaced by Thevenint's model.

Here, A y represents the open circuit voltage gain taking Rs into account. Since throughout the discussion of


SJBIT/ECE Page 176

feedback amplifiers we will consider Rs to be part of the amplifier and we will drop the subscript on the

transfer gain and input resistance (AV instead of A YS and Rjf instead of Rj f s). Look at Fig.23 the input

resistance with feedback is given as

5) If an amplifier has a bandwidth of 200 kHz and a voltage gain of 100, what will be the new band width

and gain if 5% negative feedback is introduced? What would be the amount of feedback if the bandwidth is

restricted to 1 MHz?

July2004

6) Derive an expression for the input resistance of i) Current series feedback amplifier ii) Voltage shunt

feedback amplifier. July 2004 (10), Jan 2005(10) Jan 2007(10)

Current series feedback : The current series feedback topology is shown in Fig. 6 with amplifier input

circuit is represented by Thevenin's equivalent circuit and output circuit by Norton's equivalent circuit.


SJBIT/ECE Page 177


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7) An amplifier without feedback gives a fundamental output of 36V with 7percent second harmonic

distortion when the input voltage is 0.028 V.i) .If 1.2 percent of the output is fed back into the input in a

negative voltage series feedback circuit, what is the output voltage ? ii) If the fundamental output is

maintained at 36V but the second harmonic distortion is reduced to 1 percent, what is the input voltage?

July 2005(10)


SJBIT/ECE Page 179

Recommended Question:

1. Write the difference between the capacitor coupled single stage amplifier and double

stage amplifier with respect to the out put voltage, component selection, frequency

response curve and an other parameters.

2. Explain the difference between cc coupled and direct coupled amplifiers.

3. Explain the difference between cascade & cascode connections.

4. Explain the 2 stage RC coupled BJT amplifier.

5. Explain the Darlington circuit and write the significance of it.

6. Explain how the weakest link in the cascaded system have major effect on the total gain

7. Shows cascading of an emitter follower circuit and a common base circuit. Find

8. i) The loaded gain of each stage

9. ii) The total gain for the system, Av and Ays.

10. iii) Thetotal cu:rrent gain for the system

11. iv) The total gain far the system if the emitter follower circuit were removed.(9M)

12. 13. Show that negative feedback increases the bandwidth of an amplifier. (06 Marks)

14. 15. Derive an expression for output resistance of a voltage series feedback amplifier (05M)

16. 17. Draw the cascade configuration and list the advantages of this circuit. (04 Marks)

18. 19. Determine Ai, Rj, Av and Ro for the circuit shown. Given h parameters

20. hie = 1.1 k ohm, hre= 2 X 10-4

21. hoe= 25 x 10-6 U, hfe= 50. (08 Marks)

22. List the advantages of negative feedback amplifier. Derive expressions for Zif and Zof for voltage

series

feedback amplifier. (08 Marks)

23. 24. With a neat sketch, describe the concept of feedback in amplifiers. Jan2004 [5]

25. 26. Using the block diagram approach, derive an expression for shunt feedback mplifier

27. 28. Draw a feedback amplifier in block diagram form. Identify each block and explain its function.

(Chapter-6) [8]


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Unit: 6 Hrs: 7

Power Amplifiers: Definitions and amplifier types, series fed class A amplifier, Transformer coupled Class

A amplifiers, Class B amplifier operations, Class B amplifier circuits, Amplifier distortions.


TEXT BOOK:



REFERENCE BOOKS:




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6.1 Introduction:

An amplifying system usually has several cascaded stages. The input and intermediate stages are small signal

amplifiers. Their function is only to amplify the input signal to a suitable value. The last stage usually drives

a transducer such as a loud speaker, CRT, Servomotor etc. Hence this last stage amplifier must be capable of

handling and deliver appreciable power to the load. These large signal amplifiers are called as power

amplifiers.

Power amplifiers are classified according to the class operation, which is decided by the location of the

quiescent point on the device characteristics. The different classes of operation are:

(i) Class A

(ii) Class B

(iii) Class AB

((iv) Class C

6.2 CLASS A OPERATION:

A simple transistor amplifier that supplies power to a pure resistive load RL is shown above. Let iC represent

the total instantaneous collector current, ic designate the instantaneous variation from the quiescent value of


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IC. Similarly, iB ,ib and IB represent corresponding base currents. The total instantaneous collector to emitter

voltage is given by vc and instantaneous variation from the quiescent value VC is represented by vc.

Let us assume that the static output characteristics are equidistant for equal increments of input base current

ib as shown in fig. below.

If the input signal ib is a sinusoid , the output current and voltage are also sinusoidal.Under these

conditions, the non-linear distortion is neglible and the power output may be found graphically as

follows.

P =VcIc = Ic2 RL ------------------------------ (1)

Where Vc & Ic are the rms values of the output voltage and current respectively.The numerical values

of Vc and Ic can be determined graphically in terms of the maximum and minimum voltage and

current swings.It is seen that

222

minmax IIII m

c ---------------------------- (2)

and

222

minmax VVVV m

c ------------------------- (3)

Power, Pac = L

mLmmm

R

VRIIV

222

22

----------------- (4)

This can also be written as,


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Pac = 8

minmaxminmax IIVV --------------(5)

DC power Pdc = VCC ICQ

CQCCdc

ac

IV

IIVV

P

P

8

minmaxminmax

MAXIMUM EFFICIENCY:

For a maximum swing, refer the figure below.

0& minmax VVV CC

0&2 minmax III CQ

%258

2max

CQCC

CQCC

IV

IV

SECOND HARMONIC DISTORTION: In the previous section, the active device (BJT) is treated as a perfectly linear device. But in general,

the dynamic transfer characteristics are not a straight line. This non-linearity arises because of the

static output characteristics are not equidistant straight lines for constant increments of input

excitation. If the dynamic curve is non-linear over the operating range, the waveform of the output

differs from that of the input signal. Distortion of this type is called non-linear or amplitude

distortion.

To investigate the magnitude of this distortion, we assume that the dynamic curve with

respect to the quiescent point ‗Q‘ can be represented by a parabola rather than a straight line as shown

below.


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Thus instead of relating the alternating output current ic with the input excitation ib by the equation ic

= Gib resulting from a linear circuit. We assume that the relationship between ic and ib is given more

accurately by the expression

ic = G1ib + G2ib2 -----------------------------------------(1)

where the G‘ s are constants.

Actually these two terms are the beginning of a power series expansion of ic as a function of ib.

If the input waveform is sinusoidal and of the form

ib = Ibm Cos t --------------------------------------------(2)

Substituting equation (3), into equation (2)‘

ic = G1Ibm Cos t + G2 Ibm2 Cos

2 t

Since tCostCos 22

1

2

12 , the expression for the instantaneous total current

reduces the form,

iC = IC + ic =IC +B0 + B1 Cos t + B2 Cos t2 ------------------------ (3)


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Where B‘s are constants which may be evaluated in terms of the G‘s.

The physical meaning of this equation is evident. It shows that the application of a sinusoidal signal on a

parabolic dynamic characteristic results in an output current which contains, in addition to a term of the

same frequency as the input, a second harmonic term and also a constant current. This constant term B0 adds

to the original dc value IC to yield a total dc component of current IC +B0.Thus the parabolic non-linear

distortion introduces into the output a component whose frequency is twice that of the sinusoidal input

excitation.

The amplitudes B0, B1 & B2 for a given load resistor are readily determined from either the static or the

dynamic characteristics. From fig. 7.2 above, we observe that

When ωt = 0, ic = Imax

ωt= π /2, ic = IC ---------------------------------------------------------------------------------(4)

ωt = π, ic = Imin

By substituting thase values in equation (4)‘

Imax = IC +B0 +B1+ B2

IC = IC + B0 –B2 ------------------------------------------------------- (5)

Imin = IC +B0 –B1+B2

This set of three equations determines the three unknowns B0, B1 & B2.

It follows from the second group that

B0 = B2 --------------------------------------------------------------------(6)

By subtracting the third equation from the first,

B1 = 2

minmax II --- -----------------------------------------------------(7)

Then from the first or last of equation (6),

B2 = B0 = 4

2minmax IcII ------------------------------------------- (8)

The second harmonic distortion D2 is defined as,

D2 = 1

2

B

B ------------------------------------------------------------ (9)

If the dynamic characteristics is given by the parabolic form & if the input contains two frequencies ω1 & ω2,

then the output will consist of a dc term & sinusoidal components of frequencies ω1, ω2, 2ω1,2ω2 , ω1+ω2

and ω1-ω2.The sum & difference frequencies are called intermodulation or combination frequencies.


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HIGHER ORDER HARMONIC GENERATION

The analysis of the previous section assumed a parabolic dynamic characteric.But this approximation is

usually valid for amplifier where the swing is small. For a power amplifier with a large input swing, it is

necessary to express the dynamic transfer curve with respect to the Q point by a power series of the form,

bbbc iGiGiGi 3

3

2

21 + ---------------------------------- (1)

If the input wave is a simple cosine function of time, then

tCosIi bmb --------------------------------------------- (2)

Then, tCosBtCosBtCosBBic 32 3210 (3)

Where B0, B2, B3 – are the coefficients in the Fourier series for the current.

i.e. the total output current is given by

cCQC iIi = tCosBtCosBBICQ 2210 (4)

Where ( 0BICQ is the dc component. Since Ci is an even function of time, the Fourier series in equation

(4) representing a periodic function possessing the symmetry, contains only Cosine terms.

Suppose we assume as an approximation that harmonics higher than the fourth are negligible in the above

Fourier series, then we have five unknown terms 4,321,0 &,, BBBBB .To evaluate those we need output

currents at five different value of .BI

Let us assume that tiCosiC 2 ----------------------------- (5)

Hence, tiCosII BQB 2 ----------------------------------- - (6)

At ,0t iII BQB 2 , maxIiC ------------------- (7)

At3

t , iII BQB , 2

1IiC ------------------- ---(8)

At 2

t , BQB II , CQC Ii -------------------- (9)

At3

2t , iII BQB ,

2

1IiC ---------------------(10)

At t , iII BQB 2 , minIiC ----------------------(11)

By combining equations (4) & (7) to (11), we get five equations & solving them, we get the following

relations,


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min

2

1

2

1max0 226

1IIIIB -

CQI ------------------------- (12)

min

2

1

2

1max13

1IIIIB ----------------------------------- (13)

minmax2 2

4

1IIIB CQ

--------------------------------------- (14)

min

2

1

2

1max3 226

1IIIIB ------------------------------ (15)

min

2

1

2

1max4 46412

1IIIIIB CQ -------------------- (16)

The harmonic distortion is defined as,

1

2

2B

BD ,

1

3

3B

BD ,

1

4

4B

BD -----------------------------(17)

Where nD represents the distortion of the thn harmonic. Since this method uses five points on the output

waveform to obtain the amplitudes of harmonics, the method is known as the five point method of

determining the higher order harmonic distortion.

POWER OUTPUT DUE TO DISTORTION

If the distortion is not negligible, the power delivered to the load at the fundamental frequency is given by

2

2

11

LRBP --------------------------------- (1)

The ac power output is,

2

2

3

2

2

2

1L

ac

RBBBP -------- (2)

= 1

2

3

2

21 PDD --------- (3)

Where 32 , DD etc are the second, third harmonic distortions.

Hence, 1

21 PDPac -------------------------------- (4)

Where D is the total distortion factor & is given by

2

4

2

3

2

2 DDDD --------- (5)

For e.g. if %10D of the fundamental, then


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1

21.01

PPac

101.1 PPac ---------------------------------------- (6)

When the total distortion is 10%, the power output is only 1%.higher than the fundamental power. Thus, only

a small error is made in using only the fundamental term 1P for calculating the output power.

6.3 THE TRANSFORMER COUPLED AUDIO POWER AMPLIER

The main reason for the poor efficiency of a direct-coupled classA amplifier is the large amount of dc

power that the resistive load in collector dissipates. This problem can be solved by using a transformer for

coupling the load.

TRANDFORMER IMPEDANCE MATCHING

Assume that the transformer is ideal and there are no losses in the transformer. The resistance seen

looking into the primary of the transformer is related to the resistance connected across the secondary .The

impedance matching properties follow the basic transformer relation.

2

2

11 V

N

NV and 2

1

21 I

N

NI ----------------------------------- (1)

Where

1V Primary voltage, 2V Secondary voltage.

1I Primary current, 2V Secondary current.

1N No. of turns in the primary.


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2N No. of turns in the secondary.

From Eq. (1)

2

2

2

2

1

2

1

2

2

2

1

1

1

I

V

N

N

IN

N

VN

N

I

V

2

2

2

1

1 1

I

V

nI

V --------------------------------------------- (2)

As both 2

2

1

1 &I

V

I

V are resistive terms, we can write

LLL RN

NR

nR

2

2

1

2

' 1 --------------------- (3)

In an ideal transformer, there is no primary drop.Thus the supply voltage CCV appears as the

collector-emitter voltage of the transistor.

i.e. CECC VV ------------------------------------ (4)

When the values of the resistance RB(= R1I I R2) and CCV are known, the base current at the operating

point may be calculated by the equation.

B

CC

B

BECC

BR

V

R

VVI ---------------------- (5)

OPERATING POINT:

Operating point is obtained graphically at the point of intersection of the dc load line and the

transistor base current curve.


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After the operating point is determined; the next step is to construct the ac load line passing through this

point.

AC LOAD LINE:

In order to draw the ac load line, first calculate the load resistance looking into the primary side of the

transformer. The effective load resistance is calculated using Eq.(3) from the values of the secondary load

resistance and transformer ratio. Having obtained the value of LR ' , the ac loads line must be drawn so that it

passes through the operating point Q and has a slope equal to LR '

1. The dc and the ac load lines along the

operating point Q are shown. In the above figure, two ac load lines are drawn through Q for different values

of LR ' .

For LR ' very small, the voltage swing and hence the output power ‗P‘, approaches zero.For LR ' very large,

the current swing is small and again ‗P‘ approaches zero.The variation of power & distortion wrto load

resistance is shown in the plot below.

EFFICIENCY:

Assume that the amplifier as supplying power to a pure resistance load. Then the average power input from

the dc supply ic .CCC IV The power absorbed by the output circuit is, ceCC VIRI 1

2, where ceC VI & are the

rms output current & voltage respectively & 1R is the static load resistance. If DP is the average power

dissipated by the active device, then by the principle of conservation.of energy,


SJBIT/ECE Page 191

DceCCCCC PVIRIIV 1

2 ------------ (1)

Since cceCCEQCC IVIVV , DP may be written in the form,

cceCCEQD IVIVP ---------------------- (2)

If the load is not pure resistance, then ece IV must be replaced by cce IV must be replaced by

CosIV cce , where Cos is the power factor of the load.

The above equation expresses the amount of power that must be dissipated by the active

device. If the ac output power is zero i.e. If no applied signal exists, then

CCED IVP -------------------------------- (3)

100,% Xutdcpowerinp

weracoutputpoEfficiency -------------- (4)

In general, %1002

1

0

'2

1

XBIV

RB

CCC

L

--------------- (5)

In the distortion components are neglected, then

CCC

mm

CCC

mm

IV

IVX

IV

IV

501002

1

% -------------------- (6)

MAXIMUM EFFICIENCY:


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An approximate expression for efficiency can be obtained by assuming ideal characteristic curves. Referring

to above fig., maximum values of the sine wave output voltage is,

2

minmax VVVm -------------------------- (7)

And CQm II ----------------------------------- (8)

The rms value of collector voltage,

222

minmax VVVV m

rms -------------- (9)

Similarly, 22

minmax III rms --------------------- (10)

The output power is,

22

.22

. minmaxminmax IIVVIVP rmsrmsac

8

. minmaxminmax IIVV----------------(11)

The input power is,

CQCCdc IVP .


SJBIT/ECE Page 193

CQCCdc

ac

IV

IIVV

P

P

8

minmaxminmax -------------(12)

The efficiency of a transformer coupled class A amplifier can also be expressed as,

%50minmax

minmax

VV

VV -------------------------- (13)

The efficiency will be maximum when 0minV , CQcc IIVVI 2&2,0 maxmaxmin , substituting these

values in eq.(12), we get

%50100.8

2.2max X

IV

IV

CQCC

CQCC ----------------- (14)

In practice, the efficiency of class A power amplifier is less than 50% due to losses in the transformer

winding.

DRAWBACKS:

(1) Total harmonic distortion is very high.

(2) The output transformer is subject to saturation problem due to the dc current in the primary.

PUSH-PULL AMPLIFIER:

The distortion introduced by the non-linearity of the dynamic transfer characteristic may be

eliminated by a circuit known as a known as push-pull configuration. It employs two active devices

and requires input signals 180 degrees out of phase with each other.

The above figure shows a transformer coupled push-pull amplifier. The circuit consists of two centre tapped

transformers T1 & T2 and two identical transistors Q1 and Q2.The input transformer T1 does the phase


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splitting. It provides signals of opposite polarity to the transistor inputs. The output transformer T2 is

required to couple the ac output signal from the collector to the load.

On application of a sinusoidal signal, one transistor amplifies the positive half-cycle of the input, whereas

the other transistor amplifies the negative half cycle of the same signal. When a transistor is operated as

class-B amplifier, the bias point should be fixed at cut-off so that practically no base current flows without an

applied signal.

Consider an input signal (base current of the form tCosIi bmb1 applied to Q1 .

The output current of this transistor is given as,

tCosBtCosBtCosBBIi C 32 32101 --------- (1)

The corresponding input signal to Q2 is

tCosIii bmbb 12

The output current of this transistor is obtained by replacing t by t in expression for 1i . i.e.

)()( 12 titi ------------------ (2)

tCosBBIi C 102

= tCosBtCosBtCosBBIC 32 3210 -- (3)

As illustrated in the above fig., the current 21 & ii are in opposite directions through the output transformer

windings. The total output current is the proportional to the difference between the collector currents in the

two transistors. i.e.

tCosBtCosBkiiki 32 3121 -------- (4)

This expression shows that a push-pull circuit cancels out all even harmonics in the output and will leave the third

harmonic as the principal source of distortion. This is true only when the two transistors are identical. If their

characteristics differ appreciably, the even harmonics may appear.

ADVANTAGES OF PUSH-PULL SYSTEM:

Because no even harmonics are present in the output of a push-pull amplifier ,such a circuit will give more

output per active device for given amount of distortion. Also, a push-pull arrangement may be used to obtain

less distortion for given power output per transistor.

It can be noticed that the dc component of the collector current oppose each other magnetically in the

transformer core. This eliminates any tendency towards core saturation and consequent non-linear distortion

that might arise from the curvature of the magnetization curve.


SJBIT/ECE Page 195

Another advantage of this system is that the effects of ripple voltages that may be contained in the power

supply because of inadequate filtering will be balanced out. This cancellation results because the currents

produced by this ripple voltage are in opposite directions in the transformer winding and so will not appear in

the load.

6.4 CLASS-B AMPLIFIER

The circuit for the class-B push pull system is the same as that for the class A system except that the devices

are biased approximately at cut-off. The above circuit (class A) operates in class B if R2 =0 because a silicon

transistor is essentially at cut –off if the base is shorted to the emitter.

ADVANTAGES OF CLASS B OPERATION

(1) It is possible to obtain greater power output

(2) Efficiency is higher

(3) Negligible power loss at no signal.

DRAWBACKS OF CLASS B AMPLIFIER

(1) Harmonic distortion is higher

(2) Self bias can‘t be used

(3) Supply voltage must have good regulation

POWER CONSIDERATION.

To investigate the power conversion efficiency of the system, it is assumed that the output

characteristics are equally spaces for equal intervals of excitation, so that the dynamic transfer curve

is a straight line. It also assumes that the minimum current is zero. The graphical construction from

which to determine the output current & voltage wave3shapes for a single transistor operating as a

class B stage is indicated in the above figure. Note that for sinusoidal excitation, the output is


SJBIT/ECE Page 196

sinusoidal during one half of each period and is zero during the second half cycle. The effective load

resistance is LL RN

NR

2

2

1'' where 1N represents the number of primary turn to the center tap.

The waveform illustrated in the above figure represents one transistor Q1 only. The

output of Q2 is, of course, a series of sine loop pulses that are 180 degrees out of phase with those of

Q1.The load current, which is proportional to the difference between the two collector currents, is

therefore a perfect sine wave for the ideal conditions assumed. The power output is

22

minVVIIIP CCmmm -------------------------- (1)

The corresponding direct collector current ion each transistor under load is the average value of the

half sine loop since m

dc

II for this waveform, the dc input power from the supply is,

CCmi

VIP 2 ----------------------- (2)

The factor 2 in this expression arises because two transistors are used in the push-pull system. From

equations (1) and (2) ,

%100144

100 min0 XV

V

V

VX

P

P

CCCC

m

i

Since CCVVmin

%5.78%1004

X ---------------------- (3)

The large value of results from the fact that there is no current in a class B system if there is no excitation,

where as there is a drain from the power supply in class A system even at zero signal.

POWER DISSIPATION

The power dissipation CP in both transistors is the difference between the ac power output and dc power

input.

0PPPPP iacdcC

= 2

2 mm

mCC

IVIV


SJBIT/ECE Page 197

= '

2

'2

2

L

m

L

m

CCR

V

R

VV ---------------------------- (5)

This equation shows that the collector dissipation is zero at no signal 0mV ,

Rises as mV is increases and passes through a maximum at CCm

VV

2.

MAXIMUM POWER DISSIPATION

The condition for maximum power dissipation can be found by differentiating eq.(5) wrt mV and equating it

to zero.

'

2

L

CC

m

C

R

V

dV

dP0

2

2'

L

m

R

V

''

2

L

CC

L

m

R

V

R

V

CCm VV2

----------------------------------- (6)

Substituting the value of mV in eq.(5), we get

P'

2

'max,2

1222

L

CCCC

L

CC

CR

XVVR

VP

= '

2

2'2

224

L

CC

L

CC

R

V

R

V =

'

2

2

2

L

CC

R

V ------------- (7)

Output power, '

2

02 L

m

R

VP

When CCm VV

'

2

max,02 L

CC

R

VP ----------------------------------------- (8)

Equation (7) can be written as

2max,

4CP max,02'

24

2P

R

V

L

CC

max,0max,02max, 4.04

PPPC ---------------------- (9)


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Equation (9) gives the maximum power dissipated by both the transistors and therefore the maximum power

dissipation per transistor is, 2

max,CP.

max,CP per transistor = max,0

max,0

22.0

2

4P

P ----- (10)

If, for e.g. 10W maximum power is to be delivered from a class B push-pull amplifier to the load, then power

dissipation ratio of each transistor should be 0.2 X 10W=2W.

HARMONIC DISTORTION

The output of a push-pull system always possesses mirror symmetry, so that minmax,0 IIIC &

2

1

2

1 II

We know that CIIIIIB min

2

1

2

1max0 226

1

min

2

1

2

1max13

1IIIIB

minmax2 24

1IIIB C

min

2

1

2

1max3 226

1IIIIB

min

2

1

2

1max4 46412

1IIIIIB C

When 2

1

2

1minmax &,0 IIIIIC , the above equations reduce to

0420 BBB ----------------------- (11)

2

1max13

2IIB ------------------------ (12)

2

1max3 23

1IIB ------------------------ (13)

Note that there is no even harmonic distortion. The major contribution to distortion is the third harmonic and

is given by ,


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%1001

3

3B

BD ------------------------- (14)

The output power taking distortion into account is given by

2

1

'2

12

30LRB

DP --------------------- (15)

SPECIAL CIRCUITS

Fig 3

A circuit that avoids using the output transformer is shown above. This configuration requires a power

supply whose centre tap is grounded. Here, high powered transistors are used. They have a collector to

emitter output impedance in the order of 4 to 8 .This allows single ended push-pull operation. The

voltage developed across the load is again due to the difference in collector currents 21 ii , so this is a true

push-pull application.

PROBLEMS

P1. Calculate the input power and efficiency of the amplifier shown below for an input Voltage resulting in

a base current of 10mA peak. Also calculate the power dissipated by the transistor.


SJBIT/ECE Page 200

SOLN: The Q point for the given circuit is determined as follows.

mAXR

VVI

B

BECC

B 3.19101

7.0203

mAmAXII BC 5.4823.1925

VXXRIVV CCCCCE 35.1020105.48220 3

mAmAXpeakIpeakI BC2501025)()(

WI

P CPEAK

ac 625.02

Input power, WXXIVP CCCdc 6.9105.48220 3

Efficiency, %48.6%10065.9

625.0X

P

P

dc

ac

Power dissipated by the transistor, WPPP acdcC 025.9625.065.9

P2: A class A power amplifier with a direct coupled load has a collector efficiency of

30% and delivers a power input of 10W.Find (a) the dc power input (b) the power

dissipation `of full output and (C) the desirable power dissipation rating of the BJT.

SOLN: Given 30.0%30,10WPac

(a) dc

ac

P

P


SJBIT/ECE Page 201

WP

P acdc 33.33

3.0

10

(b) Dissipation at full output, WPC 33.28533.33

(c) Dissipation at no output, WPP dcC 33.33'

BJT rating = 33.33W

P3: A BJT supplies 0.85 W to a 4K load. The zero signal dc collector current is

31 mA. Determine the percent second harmonic distortion.

SOLN: Given mAIWP ZeroC 31,85.0 ,

mAIkR signalCL 34,4 ,

Using the dynamic characteristics of the transistor,

bbc iGiGi 2

21 We have

nosignalIsignalIB CC0

=34-31=3mA

Power, L

L

R

PorB

RBP

2

2

2

1

2

1

62

1 104304

85.02X

K

XB

Or mAB 6.201

The second harmonic distortions,

%6.14%1006.20

3%100

1

2

2 XmA

mAX

B

BD

P4. Design a class B push pull circuit to deliver 200mW to a 4 load. Output transformer efficiency

is 70%., VCE=25V, average rating of the transistor to be used is 165Mw at C025 .Determine VCC ,

collector to collector resistance RCC‘

SOLN: Given Pac=200mW, RL=4 7.0, , VCE(max) =25V, Ptrans=165mW, at 250C,RE=10 .


SJBIT/ECE Page 202

Assume that the given power delivered to the load is maximum.

mWP

P acac 714.285

7.0

200max on primary of transformer.

Maximum voltage rating per transistor is 2VCC.

VCC =12.5V.

Let VCC=12V

L

CC

acprimaryR

VP

'2

12

25210714.285

12

2

1'

3

22

XX

P

VR

acprimary

CC

L

But LL

L RN

N

n

RR

2

2

1

2'

125.0252

4

'

2

L

L

R

Rn

82

1

N

N

P5: A single stage, class A amplifier has VCC=20V, VCEQ = 10V, ICQ= 600mA, and ac output current is

varied by mA300 with the ac input signal. Determine the (a) power supplied by the dc source to the

amplifier circuit (b) dc power consumed by the load resistor (c) ac power developed across the load resistor

(d) dc power delivered to the transistor (e) dc power wasted in the transistor collector (f) overall efficiency

(g) collector efficiency.

SOLN: Given VCC = 20V, VCEQ=10V, ICQ = 600Ma, RL = 16 , Imax= 300Ma

(a) Power supplied by the dc source to the amplifier circuit is given by

Pdc = VCC .ICQ=20X0.6=12W

(b) DC power consumed by the load resistor is given by

PLdc = (ICQ)2 RL = (0.6)

2X16 = 5.76 W

(c) AC power developed across the load resistor is Pac.

212.02

3.0

2

ImI

WRIP Lac 72.016212.022


SJBIT/ECE Page 203

(d) DC power delivered to the transistor‘

WPPP Ldcdcdctr 24.676.512

(e) DC Power wasted in the transistor collected is

WPPP acdctrdc 52.572.024.6

(f) Overall efficiency, %606.012

72.0

dc

ac

P

P

(g) Collector efficiency, %5.1124.6

72.0

dctr

ac

CP

P


SJBIT/ECE Page 204


1) How are amplifiers classified? Discuss them briefly. July 2005 (6)

Sol.: For an amplifier, a quiescent Q point is fixed by selecting the proper dc biasing to the transistors used.

The quiscent operating point is shown on the load line, which is plotted on the output characteristics of the

transistor. The position of the quiescent point on the load line decides the class of operation of the power

amplifier. The various classes of the power amplifier are

i) Class A

ii) Class B

iii) Class C

iv) Class AB

i) Class A amplifiers :

The power amplifiers is said to be class A amplifier if the Q point and the input signal are selected such that

the output signal is obtained for a full input cycle. For this, position of the Q point is approximately at the

mid points of the load line.

ii) Class B amplifiers:

The power amplifiers is said to be class B amplifier if the Q point and the input signal are selected, such that

the output signal is obtained only for one half cycle for a full input cycle. For this operation, the Q point is

shifted on x-axis that is transistor is biased to cut off.


SJBIT/ECE Page 205


SJBIT/ECE Page 206

2) Derive an expression for the maximum conversion efficiency of a class B push pull amplifier?

Jan2004(10), Jan2005(10) July 2008(10)


SJBIT/ECE Page 207


SJBIT/ECE Page 208

3) A single transistor ampltfier with transformer coupled load produces harmonic amplitudes in the output

as Jan 2005, July 2007 (10)Jan 2008 (10)


SJBIT/ECE Page 209

4) Calculate the peak power dissipation in each transistor and the maximum power output in a class B push

pull amplifier if Vcc = 10 V and R' L = 4.0. July2006 (8)


SJBIT/ECE Page 210


1 How are amplifiers classified? Discuss them briefly. ([6] july2005

2 Derive an expression for the maximum conversion efficiency of a class B push pull amplifier

lJan2004,Jan2005)

3 A single transistor ampltfier with transformer coupled load produces harmonic

amplitudes in the output as jan2005

4 Explain the working of a class B push pull amplifier. Prove that the maximum efficiency is 78.5%.

(10 Marks)

5 A single transistor amplifier with transformer coupled load produces harmonic amplitudes in the

output as Bo = 1.5 mA, B1 = 120 mA, B2 = 10 mA, B3 = 4 mA, B4 = 2 mA, Bs = 1 mA. i)

Determine the percentage total harmonic distortion Assume second identical transistor is used along

with suitable

transformer to provide push pull operation. Using the above harrmonic amplitudes, determine the

new total harmonic distortion. JULY2009(10 Marks)

6. With the help of a circuit diagram, explain the working of c1ass-B push pull amplifier. Obtain an

expression for maximum conversion efficiency of this amplifier. (09Marks)

7. Discuss the different types of power amplifiers. (05 Marks)

8. For distortion readings of D2 = 0.15, D3 = 0.01 arid D4 = 0.05 with II = 3.3 Rc = 40, Find - i) Total

harmonic distortion D, ii) Fundamental power component, iii) Total power. (06 Marks)

9. Show that even harmonics are absent in the out put of a push pull amplifier

10. Discuss how rectification may take place in a power amplifier.

11. What are the advantage of push pull amplifier.


SJBIT/ECE Page 211

Unit: 7 Hrs: 6

Oscillators: Oscillator operation, Phase shift Oscillator, Wienbridge Oscillator, Tuned Oscillator circuits,

Crystal Oscillator.


TEXT BOOK:



REFERENCE BOOKS:




SJBIT/ECE Page 212

7.1 Introduction:

Positive feedback drives a circuit into oscillation as in various types of oscillator circuits. A typical feedback connection is shown in Fig. 7.1. The input signal, Vs, is applied to a mixer network, where it is combined with a feedback signal, Vf. The difference of these signals, Vi, is then the input voltage to the amplifier. A portion of the amplifier output, Vo, is connected to the feedback network ( ), which provides a reduced portion of the output as feedback signal to the input mixer network

If the feedback signal is of opposite polarity to the input signal, as shown in Fig. 18.1, negative

feedback results. While negative feedback results in reduced overall voltage gain, a number of improvements are obtained, among them being:

1. Higher input impedance. 2. Better stabilized voltage gain. 3. Improved frequency response. 4. Lower output impedance. 5. Reduced noise. 6. More linear operation. .

The use of positive feedback that results in a feedback amplifier having closed-

loop gain |Af | greater than 1 and satisfies the phase conditions will result in operation as an oscillator circuit. An oscillator circuit then provides a varying output signal. If the output signal varies sinusoidally, the circuit is referred to as a sinusoidal oscillator. If the output voltage rises quickly to one voltage level and later drops quickly to another voltage level, the circuit is generally referred to as a pulse or square-wave oscillator.

consider the feedback circuit of Fig. 18.18. When the switch at the amplifier input is open, no oscillation occurs. Consider that we have a fictitious voltage at the amplifier input (Vi). This results in an output voltage Vo AVi after the amplifier stage and in a voltage Vf (AVi) after the feedback stage. Thus, we have a feedback voltage Vf AVi, where A is referred to as the loop gain. If the circuits of the base amplifier and feedback network provide A of a correct magnitude and phase, Vf can be made equal to Vi. Then, when the switch is closed and fictitious voltage Vi is removed, the circuit will continue operating since the feedback voltage is sufficient to drive the amplifier and feedback circuits resulting in a proper input voltage to sustain the loop operation. The output waveform will still exist after the switch is closed if the condition

A β = 1 is met. This is known as the Barkhausen criterion for oscillation.

7.2 PHASE-SHIFT OSCILLATOR


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An example of an oscillator circuit that follows the basic development of a feedback circuit is the phase-shift oscillator. An idealized version of this circuit is shown in Fig. Recall that the requirements for oscillation are that the loop gain, A, is greater than unity and that the phase shift around the feedback network is 180° (providing positive feedback). In the present idealization, we are considering the feedback network to be driven by a perfect source (zero source impedance) and the output of the feedback network to be connected into a perfect load (infinite load impedance). The idealized case will allow development of the theory behind the operation of the phase-shift oscillator. Practical circuit versions will then be considered.

If a transistor is used as the active element of the amplifier stage, the output of the feedback network is loaded appreciably by the relatively low input resistance (hie) of the transistor. Of course, an emitter-follower input stage followed by a common-emitter amplifier stage could be used. If a single transistor stage is desired, however, the use of voltage-shunt feedback (as shown in Fig. 18.21b) is more suitable. In this connection, the feedback signal is coupled through the feedback resistor R in series with the amplifier stage input resistance (Ri).

Analysis of the ac circuit provides the following equation for the resulting oscillator frequency:

fr = 1/2√π6RC

7.3 WIEN BRIDGE OSCILLATOR A practical oscillator circuit uses an op-amp and RC bridge circuit, with the oscillator frequency set by the R and C components. Figure 18.23 shows a basic version of a Wien bridge oscillator circuit. Note the basic bridge connection. Resistors R1 and R2 and capacitors C1 and C2 form the frequency-adjustment elements, while resistors R3 and R4 form part of the feedback path. The op-amp output is connected as the bridge input at points a and c. The bridge circuit output at points b and d is the input to the op-amp.


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R and C are used for frequency adjustment and resistors R1 and R2 form part of the feedback path.

If R3 = R4 =R, C1 = C2 = C, the resulting frequency is f = 1/2πRC and R2 / R1 = 2

7.4 TUNED OSCILLATOR CIRCUIT

Tuned-Input, Tuned-Output Oscillator Circuits

A variety of circuits can be built using that shown in Fig. 18.25 by providing tuning in both the input and output sections of the circuit. Analysis of the circuit of Fig. reveals that the following types of oscillators are obtained when the reactance elements are as designated:

Oscillator Type

Reactance Element

X1

X2

X3

Colpitts oscillator

Hartley oscillator

Tuned input, tuned output

C

L

LC

C

L

LC

L

C

—

Colpitts Oscillator

A transistor Colpitts oscillator circuit can be made as shown in Fig.


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Hartley Oscillator

Below figure shows a transistor Hartley oscillator circuit

7.5 CRYSTAL OSCILLATOR

A crystal oscillator is basically a tuned-circuit oscillator using a piezoelectric crystal as a resonant tank circuit. The crystal (usually quartz) has a greater stability in hold- ing constant at whatever frequency the crystal is originally cut to operate. Crystal oscillators are used whenever great stability is required, such as in communication trans- mitters and receivers.


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Characteristics of a Quartz Crystal

A quartz crystal (one of a number of crystal types) exhibits the property that when mechanical stress is applied across the faces of the crystal, a difference of potential develops across opposite faces of the crystal. This property of a crystal is called the piezoelectric effect. Similarly, a voltage applied across one set of faces of the crystal causes mechanical distortion in the crystal shape.

When alternating voltage is applied to a crystal, mechanical vibrations are set up—these vibrations

having a natural resonant frequency dependent on the crystal. Although the crystal has electromechanical resonance, we can represent the crystal action by an equivalent electrical resonant circuit as shown in Fig. 18.31. The inductor L and capacitor C represent electrical equivalents of crystal mass and compliance, while resistance R is an electrical equivalent of the crystal structure‘s internal fric- tion. The shunt capacitance CM represents the capacitance due to mechanical mount- ing of the crystal. Because the crystal losses, represented by R, are small, the equivalent crystal Q (quality factor) is high—typically 20,000. Values of Q up to almost 106 can be achieved by using crystals.

The crystal as represented by the equivalent electrical circuit of Fig. 18.31 can have two resonant frequencies. One resonant condition occurs when the reactances of the series RLC leg are equal (and opposite). For this condition, the series-resonant impedance is very low (equal to R). The other resonant condition occurs at a higher frequency when the reactance of the series-resonant leg equals the reactance of capacitor CM. This is a parallel resonance or antiresonance condition of the crystal. At this frequency, the crystal offers a very high impedance to the external circuit. The impedance versus frequency of the crystal is shown in Fig. 18.32. In order to use the crystal properly, it must be connected in a circuit so that its low impedance in the series-resonant operating mode or high impedance in the antiresonant operating mode is selected.

Electrical equivalent circuit of a crystal.


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Crystal impedance ersus frequency.


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1. Explain with the help of a circuit diagram, the working of an RC phase shift oscillator

. July 2008(8),jan2009(8)

The RC Phase Shift Oscillator:

At low frequencies (around 100 KHz or less), resistors are usually employed to determine the frequency

oscillation. Various circuits are used in the feedback circuit including ladder network.

Figure: Circuit diagram of RC phase shift Oscillator

It consists of a conventional single transistor amplifier and a RC phase shift circuit. The RC phase

shift circuit consists of three sections R1C1, R2C2, and R3C3.At some particular frequency f0 the phase

shift in each RC section is 600 so that the total phase shift produced by the RC network is 180

0. The

frequency of oscillation is given by

62

1

RCfo ---------------------------(6)

When the circuit is switched ON it produces oscillations of frequency determined by equation 1. The

output EO of the amplifier is feedback to RC feedback network. This network produces a phase shift

of 1800 and the transistor gives another 180

0 shift. Thereby total phase shift of the output signal when

fed back is 3600

Merits-


SJBIT/ECE Page 219

1. They do not require any transformer or inductor thereby reduce the cost.

2. They are quite useful in the low frequency range where tank circuit oscillators cannot be

used.

3. They provide constant output and good frequency stability.

Demerits –

1. It is difficult to start oscillations.

2. The circuit requires a large number of components.

3. They cannot generate high frequencies and are unstable as variable frequency generators.

2 With the help of Barkhousen criterion, explain the working of a BJT crystal oscillator.

July 2008

Barkhausen criterion.

We know that the active component in a feedback amplifier produces a voltage gain (Av)) while the

feedback network introduces a loss or attenuation (αv). In order for an oscillator to work properly, the

following relationship must be met:

Av αv = 1 Av

This relationship is called the Barkhausen criterion. If this criterion is not met, one of the following occurs:

1. If Av αv < 1 , the oscillations die out after a few cycles.

2. If Av αv > 1 , the oscillator drives itself into saturation and cutoff clipping.

The Barkhausen criterion for oscillations can be summarized as follows :

In order to make a circuit to work as an oscillator it should satisfy the following Barkhausen criterion

1.The total phase shift around a loop should be 0 or 360°.

4) With the help of a neat circuit diagram, explain transistor colpitts oscillator. Write the

expression for the frequency of oscillation.

July 2008 (08)

The Colpitts Oscillator: The Colpitts oscillator is a discrete LC oscillator that uses the tank circuit described

above.A pair of tapped capacitors and an inductor is used to produce regenerative feedback. A Colpitts

oscillator is shown in Figure -5. The operating frequency is determined by the tank circuit. By the formula:


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The key to understanding this circuit is knowing how the feedback circuit produces its 180° phase shift and

the other 180° is produced from the inverting action of the CE amplifier. The feedback circuit produces a

180° voltage phase shift as follows:

1. The amplifier output voltage is developed across .

2. The feedback voltage is developed across .

3. As each capacitor causes a 90° phase shift, the voltage at the top of (the output voltage) must be

180° out of phase with the voltage at the bottom of (the feedback voltage).

The first two points are fairly easy to see. is between the collector and ground. This is where the output is

measured.

is between the transistor base and ground, or in other words, where the input is measured. Point three is

explained using the circuit in Figure -6.

FIGURE -6

Figure 6 is the equivalent representation of the tank circuit in the Colpitts oscillator. Let‘s assume that the

inductor is the voltage source and it induces a current in the circuit. With the polarity shown across the

inductor, the current causes potentials to be developed across the capacitors with the polarities shown in the

figure. Note that the capacitor voltages are 180° out of phase with each other. When the polarity of the

inductor voltage reverses, the current reverses, as does the resulting polarity of the voltage across each

capacitor (keeping the capacitor voltages 180° out of phase).


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The value of the feedback voltage is determined (in part) by the of the circuit. For the Colpitts oscillator,

is defined by the ratio of . By formula:

Av = XC2/X C1 or C 1/C 2

As with any oscillator, the product of A β must be slightly greater than 1. As mentioned earlier

and . Therefore:

Av = Vout/Vf = C2/C1

As with any tank circuit, this one will be affected by a load. To avoid loading effects (the circuit loses some

efficiency), the output from a Colpitts oscillator is usually transformer-coupled to the load, as . Capacitive

coupling is also acceptable so long as:

where is the total capacitance in the feedback network

5) With the help of new circuit diagram of Crystal oscillator, explain briefly

July 2008 (10)

Figure: Circuit diagram of Transistor crystal oscillator


SJBIT/ECE Page 222

Figure shows the transistor crystal oscillator. The crystal will act as parallel –tuned circuit. At parallel

resonance, the impedance of the crystal is maximum. This means that there is a maximum voltage

drop across C2. This in turn will allow the maximum energy transfer through the feedback network.

The feedback is +ve. A phase shift of 1800 is produced by the transistor. A further phase shift of 180

0

is produced by the capacitor voltage divider. This oscillator will oscillate only at fp.

Where fp = parallel resonant frequency ie the frequency at which the vibrating crystal behaves as a

parallel resonant circuit.

m

m

T

T

p

CC

CCCwhere

LCf

2

1

Advantages

1. Higher order of frequency stability

2. The Q-factor of the crystal is very high.

Disadvantages

1. Can be used in low power circuits.

2. The frequency of oscillations cannot be changed appreciably.


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1. Explain with the help of a circuit diagram, the working of an RC phase shift oscillator(08 Marks)

2. With the help of Barkhousen criterion, explain the working of a BJT crystal oscillator.(08 Marks)

3 Calculate the frequency of a Wien Bridge oscillator circuit when R = 12 k ohm and

C = 2400 pf. (04 Marks)

4. What is Barkhausen criterion? Explain how oscillations start in an oscillator. (07 Marks)

5. With the help of a neat circuit diagram, explain transistor colpitts oscillator. Write the expression for the

frequency of oscillation. (08 Marks)

6 A quartz crystal has L = 0.12 H, C = 0.04 pF CM = pF and R = 9.2 kQ. Find i) Series resonant

frequency, ii) Parallel resonant frequency.

7 Write the short notes on LC ,RC &Hartely oscillator


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Unit: 8 Hrs: 7

FET Amplifiers: FET small signal model, Biasing of FET, Common drain common gate configurations,

MOSFETs, FET amplifier networks.


TEXT BOOK:



REFERENCE BOOKS:




SJBIT/ECE Page 225

8.1 Field Effect Transistor (FET)

The FET is a three terminal device like the BJT, but operates by a different principle. The three terminals are

called the source, drain, and gate. The voltage applied to the gate controls the current flowing in the source-

drain channel. No current flows through the gate electrode, thus the gate is essentially insulated from the

source-drain channel. Because no current flows through the gate, the input impedance of the FET is

extremely large (in the range of 1010

–1015

Ω). The large input impedance of the FET makes them an

excellent choice for amplifier inputs.

The two common families of FETs, the junction FET (JFET) and the metal oxide semiconductor FET

(MOSFET) differ in the way the gate contact is made on the source-drain channel.

In the JFET the gate-channel contact is a reverse biased pn junction. The gate-channel junction of the JFET

must always be reverse biased otherwise it may behave as a diode. All JFETs are depletion mode devices—

they are on when the gate bias is zero (VGS = 0).

In the MOSFET the gate-channel contact is a metal electrode separated from the channel by a thin layer of

insulating oxide. MOSFETs have very good isolation between the gate and the channel, but the thin oxide is

easily damaged (punctured!) by static discharge through careless handling. MOSFETs are made in both

depletion mode (on with zero biased gate, VGS = 0) and in enhancement mode (off with zero biased gate).

In this class we will focus on JFETs.

Schematic symbols. Two versions of the symbols are in common use. The symbols in the top row depict

the source and drain as being symmetric. This is not generally true. Slight asymmetries are built into the

channel during manufacturing which optimize the performance of the FET. Thus it is necessary to

distinguish the source from the drain. In this class we will use the asymmetric symbols found on the bottom

row, which depict the gate nearly opposite the source. The designation n-channel means that the channel is n

doped and the gate is p doped. The p-channel is complement of n-channel.


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Common Nomenclature (n-channel FET example).

Regions of JFET operation:

Cut-off region: The transistor is off. There is no conduction between the drain and the source when the

gate-source voltage is greater than the cut-off voltage. (ID = 0 for VGS > VGS,off)

Active region (also called the Saturation region): The transistor is on. The drain current is controlled by

the gate-source voltage (VGS) and relatively insensitive to VDS. In this region the transistor can be an

amplifier.

In the active region:

Ohmic region: The transistor is on, but behaves as a voltage controlled resistor. When VDS is less than in

the active region, the drain current is roughly proportional to the source-drain voltage and is controlled by the

gate voltage.

In the ohmic region:

Common Specifications.

IDSS is the drain current in the active region for VGS = 0. (ID source shorted to gate)

VGS,off is the minimum VGS where ID = 0. VGS,off is negative for n-channel and positive for p-channel..


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gm is the transconductance, the change in ID with VGS and constant VDS.

Common Circuit Applications:

Voltage Controlled Switch. For the on state the gate voltage VGS = 0 and for the off state |VGS| > |VGS,off| (of

greater magnitude than VGS,off and with the same sign). The sign of the voltage depends on the type of FET,

negative for n-channel and positive for p-channel.

Current Source. The drain current is set by RS such that VGS = IDRS. Any value of current can be chosen

between zero and IDSS (see the ID vs VGS graph for the JFET).

Source Follower. The simple source follower is shown below. The improved version is shown at the right.

The lower JFET forms a current source. The result is that VGS is held constant, removing the defects of the

simple circuit.


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Voltage-Controlled Resistor. VGS must be between zero and

VGS,off.

JFET Diode. The JET pn gate junction can be used as a diode by connecting the source and the drain

terminals. This is done if very low reverse leakage currents are required. The leakage current is very low

because the reverse leakage current scales with the gate area. Small gate areas are designed into JFETs

because it decreases the gate-source and the gate-drain capacitances

.

Unlike BJTs, thermal runaway does not occur with FETs, as already discussed in our blog. However, the

wide differences in maximum and minimum transfer characteristics make ID levels unpredictable with

simple fixed-gate bias voltage. To obtain reasonable limits on quiescent drain currents ID and drain-source

voltage VDS, source resistor and potential divider bias techniques must be used. With few exceptions,

http://www.circuitstoday.com/characteristics-of-jfets


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MOSFET bias circuits are similar to those used for JFETs. Various FET biasing circuits are discussed

below:

8.2 Fixed Bias.

DC bias of a FET device needs setting of gate-source voltage VGS to give desired drain current ID . For a

JFET drain current is limited by the saturation current IDS. Since the FET has such a high input impedance

that no gate current flows and the dc voltage of the gate set by a voltage divider or a fixed battery voltage is

not affected or loaded by the FET.

Fixed dc bias is obtained using a battery VQG. This battery ensures that the gate is always negative with

respect to source and no current flows through resistor RG and gate terminal that is IG =0. The battery

provides a voltage VGS to bias the N-channel JFET, but no resulting current is drawn from the battery VGG.

Resistor RG is included to allow any ac signal applied through capacitor C to develop across RG. While any

ac signal will develop across RG, the dc voltage drop across RG is equal to IG RG i.e. 0 volt.

The gate-source voltage VGS is then

VGS = - vG – vs = – vGG – 0 = – VGG

The drain -source current ID is then fixed by the gate-source voltage as determined by equation.

This current then causes a voltage drop across the drain resistor RD and is given as VRD = ID RD and output voltage, Vout

= VDD – ID RD

Self-Bias.

http://www.circuitstoday.com/jfet-junction-field-effect-transistor


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This is the most common method for biasing a JFET. Self-bias circuit for N-channel JFET is shown in figure.

Since no gate current flows through the reverse-biased gate-source, the gate current IG = 0 and, therefore,vG =

iG RG = 0

With a drain current ID the voltage at the S is

Vs= ID Rs

The gate-source voltage is then

VGs = VG - Vs = 0 – ID Rs = – ID Rs

So voltage drop across resistance Rs provides the biasing voltage VGg and no external source is required for

biasing and this is the reason that it is called self-biasing.

The operating point (that is zero signal ID and VDS) can easily be determined from equation and equation

given below :

VDS = VDD – ID (RD + RS)

Thus dc conditions of JFET amplifier are fully specified. Self biasing of a JFET stabilizes its quiescent

operating point against any change in its parameters like transconductance. Let the given JFET be replaced

by another JFET having the double conductance then drain current will also try to be double but since any

increase in voltage drop across Rs, therefore, gate-source voltage, VGS becomes more negative and thus

increase in drain current is reduced.


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Potential-Divider Biasing.

.

fet-potential-divider-biasing

A slightly modified form of dc bias is provided by the circuit shown in figure. The resistors RGl and RG2 form

a potential divider across drain supply VDD. The voltage V2 across RG2 provides the necessary bias. The

additional gate resistor RGl from gate to supply voltage facilitates in larger adjustment of the dc bias point

and permits use of larger valued RS.

The gate is reverse biased so that IG = 0 and gate voltage

VG =V2 = (VDD/R G1 + R G2 ) *RG2

And


SJBIT/ECE Page 232

VGS = vG – vs = VG - ID Rs

The circuit is so designed that ID Rs is greater than VG so that VGS is negative. This provides correct bias voltage.

The operating point can be determined as

ID = (V2 – VGS)/ RS

And


Figure 3-51 shows a basic common-source amplifier circuit containing an N-channel JFET. The

characteristics of this circuit include high input impedance and a high voltage gain. The function of the

circuit components in this figure is very similar to those in a triode vacuum tube common-cathode amplifier

circuit. C1 and C3 are the input and output coupling capacitors. R1 is the gate return resistor and functions

much like the grid return resistor in a vacuum tube circuit. It prevents unwanted charge buildup on the gate

by providing a discharge path for C1. R2 and C2 provide source self-bias for the JFET, which operates like

cathode self-bias. R3 is the drain load resistor, which acts like the plate or collector load resistor. Figure 3-

51.—JFET common source amplifier. The phase shift of 180 degrees between input and output signals is

the same as that of common- cathode vacuum tube circuits (and common-emitter transistor circuits). The

reason for the phase shift can be seen easily by observing the operation of the N-channel JFET. On the

positive alternation of the input signal, the amount of reverse bias on the P-type gate material is reduced, thus

increasing the effective cross-sectional area of the channel and decreasing source-to-drain resistance. When

resistance decreases, current flow through the JFET increases. This increase causes the voltage drop across

R3 to increase, which in turn causes the drain voltage to decrease. On the negative alternation of the cycle,

the amount of reverse bias on the gate of the JFET is increased and the action of the circuit is reversed. The

result is an output signal, which is an amplified 180-degree-out-of-phase version of the input signal. A

second type of field-effect transistor has been introduced in recent years that has some advantages over the

JFET. This device is the metal oxide semiconductor field effect transistor (MOSFET). The MOSFET has an

even higher input impedance than the JFET (10 to 100 million megohms). Therefore, the MOSFET is even

less of a load on preceding circuits. The extremely high input impedance, combined with a high gain factor,

makes the MOSFET a highly efficient input device for RF/IF amplifiers and mixers and for many types of

test equipment. The MOSFET is normally constructed so that it operates in one of two basic modes: the

depletion mode or the enhancement mode. The depletion mode MOSFET has a heavily doped channel and

uses reverse bias on the gate to cause a depletion of current carriers in the channel. The JFET also operates in

this manner.


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Question paper with solution:

1) Discuss the differences between FET and BJT.

Jan 2008 (2)

BJT & FET parameters are temperature dependent. In BJT the collector junction resistance decreasing (

collector current increasing) with temperature raise.Due to the higher temperature & current...

2) Derive the expressions for Zj, 20 and Ay for common source JFET amplifier.

July 2008 (09 )

JFET Amplifier

Small signal amplifiers can also be made using Field Effect Transistors or FET's. These devices have the

advantage over bipolar devices of having an extremely high input impedance along with a low noise output

making them very useful in amplifier circuits using very small signals. The design of an amplifier circuit

based around a JFET (n-channel FET for this example) or even a MOSFET is exactly the same principle as

that for a bipolar device and for a Class A amplifier as we looked at in the previous tutorial. A suitable

Quiescent point still needs to be found for the correct biasing of the amplifier circuit with amplifier

configurations of Common Source, Common Drain and Common Gate available for FET devices. In this

tutorial we will look at the JFET Amplifier as a common source amplifier as this is the most widely used

design. Consider the Common Source JFET Amplifier circuit below.

Common Source JFET Amplifier


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The circuit consists of an N-channel JFET, but the device could also be an equivalent N-channel Depletion-

mode MOSFET as the circuit diagram would be the same, just a change in the FET. The JFET Gate voltage

Vg is biased through the potential divider network set up by resistors R1 and R2 and is biased to operate

within its saturation region which is equivalent to the active region of the BJT. The Gate biasing voltage Vg

is given as:

Note that this equation only determines the ratio of the resistors R1 and R2, but in order to take advantage of

the very high input impedance of the JFET as well as reducing the power dissipation within the circuit, we

need to make these resistor values as high as possible, with values in the order of 1 to 10MΩ being common.

The input signal, (Vin) is applied between the Gate terminal and 0v with the Drain circuit containing the load

resistor, Rd. The output voltage, Vout is developed across this load resistance. There is also an additional

resistor, Rs included in the Source lead and the same Drain current also flows through this resistor. When the

JFET is switched fully "ON" a voltage drop equal to Rs x Id is developed across this resistor raising the

potential of the Source terminal above 0v or ground level. This voltage drop across Rs due to the Drain

current provides the necessary reverse biasing condition across the Gate resistor, R2. In order to keep the

Gate-source junction reverse biased, the Source voltage, Vs needs to be higher than the gate voltage, Vg.

This Source voltage is therefore given as:

Then the Drain current, Id is also equal to the Source current, Is as "No Current" enters the Gate terminal and

this can be given as:

This potential divider biasing circuit improves the stability of the common source JFET circuit when being

fed from a single DC supply compared to that of a fixed voltage biasing circuit. Both Resistor, Rs and

Capacitor, Cs serve basically the same function as the Emitter resistor and capacitor in the Common Emitter

Bipolar Transistor amplifier circuit, namely to provide good stability and prevent a reduction in the signal

gain. However, the price paid for a stabilized quiescent Gate voltage is that more of the supply voltage is

dropped across Rs.

3) With the help of circuits and equations, show different biasing arrangements for depletion

type MOSFET. July 2008 (08)

Fixed Bias.


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DC bias of a FET device needs setting of gate-source voltage VGS to give desired drain current ID . For a

JFET drain current is limited by the saturation current IDS. Since the FET has such a high input impedance

that no gate current flows and the dc voltage of the gate set by a voltage divider or a fixed battery voltage is

not affected or loaded by the FET.

Fixed dc bias is obtained using a battery VQG. This battery ensures that the gate is always negative with

respect to source and no current flows through resistor RG and gate terminal that is IG =0. The battery

provides a voltage VGS to bias the N-channel JFET, but no resulting current is drawn from the battery VGG.

Resistor RG is included to allow any ac signal applied through capacitor C to develop across RG. While any

ac signal will develop across RG, the dc voltage drop across RG is equal to IG RG i.e. 0 volt.

The gate-source voltage VGS is then

VGS = - vG – vs = – vGG – 0 = – VGG

The drain -source current ID is then fixed by the gate-source voltage as determined by equation.

This current then causes a voltage drop across the drain resistor RD and is given as VRD = ID RD and output voltage,

Vout = VDD – ID RD

Self-Bias.


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This is the most common method for biasing a JFET. Self-bias circuit for N-channel JFET is shown in figure.

Since no gate current flows through the reverse-biased gate-source, the gate current IG = 0 and, therefore,vG =

iG RG = 0

With a drain current ID the voltage at the S is

Vs= ID Rs

The gate-source voltage is then

VGs = VG - Vs = 0 – ID Rs = – ID Rs

So voltage drop across resistance Rs provides the biasing voltage VGg and no external source is required for

biasing and this is the reason that it is called self-biasing.

The operating point (that is zero signal ID and VDS) can easily be determined from equation and equation

given below :


Thus dc conditions of JFET amplifier are fully specified. Self biasing of a JFET stabilizes its quiescent

operating point against any change in its parameters like transconductance. Let the given JFET be replaced

by another JFET having the double conductance then drain current will also try to be double but since any

increase in voltage drop across Rs, therefore, gate-source voltage, VGS becomes more negative and thus

increase in drain current is reduced.

Potential-Divider Biasing.

FET-potential-divider-biasing


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A slightly modified form of dc bias is provided by the circuit shown in figure. The resistors RGl and RG2 form

a potential divider across drain supply VDD. The voltage V2 across RG2 provides the necessary bias. The

additional gate resistor RGl from gate to supply voltage facilitates in larger adjustment of the dc bias point

and permits use of larger valued RS.

The gate is reverse biased so that IG = 0 and gate voltage

VG =V2 = (VDD/R G1 + R G2 ) *RG2

And

VGS = vG – vs = VG - ID Rs

The circuit is so designed that ID Rs is greater than VG so that VGS is negative. This provides correct bias voltage.

The operating point can be determined as

ID = (V2 – VGS)/ RS

And


Recommeded questions:

1. Discuss the differences between FET and BJT. (04 Marks)

2. Derive the expressions for Zj, 20 and Ay for common drain JFET amplifier. (09 Marks)

3. A de analysis of source follower network shown in Fig. Q8(c) results in VGsQ= -2.86 V

and IDQ= 4.56 mA. Determinei) gm, ii) rd, ii) Zi, iv) Zo with and without rd, v) Ay with and

without rd.IDss= 16mA, VI' = -4V, Yos = 25 j.lS.Fig.

4 Determine Zj, Zo and Av for the circuit shown in Fig.Q8(a), if Yfs = 3000 l.lS andYos = 50 Jls.)

Fig.Q8(a)

5. Determine Zj, Zo, and Av ifrd = 40 kQ for fig.Q8(b). (06 Marks)

6. With the help of circuits and equations, show different biasing arrangements for depletion

type MOSFET.


SJBIT/ECE Page 238

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