Advanced High-K Gate Dielectric for High-Performance Short-Channel In0.7Ga0.3As Quantum Well Field Effect Transistors on Silicon Substrate for Low

Power Logic Applications

M. Radosavljevic, B. Chu-Kung, S. Corcoran, G. Dewey, M. K. Hudait, J. M. Fastenau*, J. Kavalieros, W. K. Liu*, D. Lubyshev*, M. Metz, K. Millard, N. Mukherjee, W. Rachmady, U. Shah,

and Robert Chau Intel Corporation, Technology and Manufacturing Group, Hillsboro, OR 97124, USA

* IQE Inc, Bethlehem, PA 18015, USA Contact: robert.s.chau@intel.com

Abstract

This paper describes integration of an advanced composite high-K gate stack (4nm TaSiOx-2nm InP) in the In0.7Ga0.3As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (tOXE) and low gate leakage (JG) and (ii) effective carrier confinement and high effective carrier velocity (Veff) in the QW channel. The LG=75nm In0.7Ga0.3As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750μS/μm and high drive current of 0.49mA/μm at VDS=0.5V.

Introduction In0.7Ga0.3As QWFET is a promising transistor candidate for future high-speed low-power logic applications due to its excellent drive current performance at low voltage, and its demonstrated integration onto the silicon substrate [1]. However at present the InGaAs QWFET uses a Schottky gate with no gate dielectric and is subjected to large gate leakage (JG) with scaling of the upper InAlAs barrier thickness above the quantum well (QW) (Fig. 1). For further transistor scaling, there are significant challenges in identifying a suitable high dielectric constant (K) gate dielectric and its integration into the III-V transistor, which will need to simultaneously decrease tOXE (electrical gate oxide thickness), reduce JG, achieve good interface properties while retaining high carrier mobility in the transistor channel. In this work, we demonstrate a composite high-K TaSiOx-InP gate stack and its integration into the In0.7Ga0.3As QWFET, resulting in high-performance short-channel In0.7Ga0.3As QWFETs on silicon substrate with significantly decreased tOXE and reduced JG.

Materials Growth and Characterization In order to retain the high carrier mobility of the QWFET, the high-K gate dielectric is deposited on the upper barrier of the QW stack rather than directly on the In0.7Ga0.3As QW channel. Two upper barrier materials, In0.52Al0.48As and InP, with identical lattice constants and similar K-values are evaluated for high-K gate dielectric integration. Figs. 2a-b show the gate capacitance (C) versus gate bias (VG) for Al2O3 capacitors on In0.52Al0.48As and InP respectively. Al2O3-InP

capacitors exhibit lower frequency dispersion than Al2O3-In0.52Al0.48As capacitors, suggesting InP is a more suitable upper barrier material for high-K integration. Further improvements can be made to the high-K-InP capacitors by replacing Al2O3 with TaSiOx which has higher K and similar frequency dispersion, as shown in Fig. 3.

Fig. 4 shows a schematic of the new In0.7Ga0.3As QWFET for this work with 2nm InP upper barrier layer and a 4nm TaSiOx high-K gate dielectric, which form a composite TaSiOx-InP gate stack on top of the QW. The thickness of these layers is chosen to provide a thin tOXE while maintaining carrier confinement in the QW. Fig. 5 shows the band diagram of the In0.7Ga0.3As QW structure with 2nm InP upper barrier obtained using Schrödinger-Poisson simulation, which indicates good carrier confinement in the In0.7Ga0.3As QW layer. Figs. 6a-b show the TEM micrographs of the entire In0.7Ga0.3As QWFET stack on silicon by MBE and the active device layers with 2nm InP upper barrier, respectively. The effectiveness of the 2nm InP layer as an upper barrier is confirmed in Fig. 7 which shows QW electron mobility of 10,000 cm2/Vs at 300K with no parallel conduction.

Device Fabrication and Characterization The TEM in Fig. 8 shows the In0.7Ga0.3As QWFET with physical gate length (LG) of 75nm and the composite 4nm TaSiOx-2nm InP gate stack. The high-K TaSiOx dielectric was deposited using ALD, and the metal gate electrode consists of TiN/Pt/Au. Fig. 9a shows the C-VG measured on the In0.7Ga0.3As QWFET with the composite TaSiOx-InP gate stack. The composite gate stack has tOXE of 22Å determined from the measured intrinsic gate capacitance, and also good stability with minimal C-VG hysteresis. Included is C-VG of the Schottky-gate QWFET (extracted at RF due to high JG) with tInAlAs=5nm and tOXE=33Å. Fig. 9b shows JG as a function of VG for the In0.7Ga0.3As QWFET with (i) composite TaSiOx-InP gate stack versus (ii) Schottky gate. Insertion of high-K gate dielectric into the In0.7Ga0.3As QWFET decreases tOXE by 11Å while simultaneously reducing the gate leakage by a factor of >1000.

Fig. 10 shows drain current (ID) versus gate voltage (VGS) of LG=180nm In0.7Ga0.3As QWFET with the composite TaSiOx-InP gate stack. The device shows both excellent subthreshold slope (SS) of 85mV/decade and drain induced

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barrier lowering (DIBL) of 35mV/V at VDS12 show the ID-VGS and the ID-VDrespectively of the LG=75nm In0.7Ga0.3As Qcomposite gate stack. The drive curtransconductance (Gm) of this LG=75n0.49mA/μm and 1750μS/μm (Fig. 13) respecof 0.5V. These performance values are reported for III-V QWFET with high-K gat14 shows the measured effective electron the In0.7Ga0.3As QWFETs with composite stack is >3.5X higher than that in strained SThis demonstrates that despite the insertionhigh-K gate stack, the intrinsic advantageQWFET over strained Si MOSFET is still 15-16 show the Gm and SS respectively as for the In0.7Ga0.3As QWFETs with compversus those of the state-of-the-art III-V tranK gate dielectrics reported in literature [3-6]the transistors of this work have significanand higher Gm for all LG due to thinner tOXE agate stack properties.

Conclusions An advanced composite high-K gate sta2nm InP) has been integrated in the In0.7Ga0silicon substrate to enable both (i) thin tOXE(ii) effective carrier confinement and highchannel. The LG=75nm In0.7Ga0.3As QWcomposite high-K gate stack achieves high Gand high drive current of 0.49mA/μm at VD>3.5X improvement in Veff over strained Si same DIBL. Compared to the state-of-the-arwith high-K gate dielectrics reported in liteshows significantly improved SS and highdue to thinner tOXE and better high-K gate sta

References

[1] M.K. Hudait et al., IEDM Tech. Dig., pp.625 (2007)[2] G. Dewey et al., IEEE Electron Device Lett., 29, pp.[3] D.A.J. Moran et al., ESSDERC Tech. Dig., pp.466 (2[4] Y. Sun et al., IEDM Tech. Dig., pp.367 (2008). [5] Y. Xuan et al., IEDM Tech. Dig., pp.371 (2008). [6] S. Koveshnikov et al., DRC Tech. Dig., pp.43 (2008

Fig. 1: Gate leakage current (JG) versus In0.52Al0.48A(tInAlAs) between the metal gate electrode and In0.7Ga0.3

due to thin tInAlAs and the low band offset between channel.

S=0.5V. Figs. 11-S characteristics QWFET with the rrent and peak nm device are ctively at low VDS the highest ever te dielectric. Fig. velocity (Veff) in TaSiOx-InP gate

Si MOSFETs [2]. n of a composite e of In0.7Ga0.3As maintained. Figs. a function of LG

posite gate stack nsistors with high-]. The data shows ntly improved SS and better high-K

ack (4nm TaSiOx-0.3As QWFET on E and low JG and

h Veff in the QW WFET with this Gm of 1750μS/μm DS=0.5V, and also MOSFETs at the

rt III-V transistors erature, this work her Gm for all LG ack properties.

. .1094 (2008). 2007).

).

As barrier thickness 3As QW. High JG is the barrier and the

Fig. 2(a): Gate capacitance (C) versus In0.52Al0.48As capacitors as a function of meas

Fig. 2(b): Gate capacitance (C) versus gcapacitors as a function of measurement freexhibit lower frequency dispersion (7%/deccapacitors (27%/decade), indicating InP is high-K integration.

Fig. 3: Gate capacitance (C) versus gate b40Å Al2O3 dielectrics on InP. TaSiOx showsAl2O3 due to its higher dielectric constantfrequency dispersion (7%/decade).

gate bias (VG) for Al2O3-surement frequency.

gate bias (VG) for Al2O3-InP equency. Al2O3-InP capacitors cade) than Al2O3-In0.52Al0.48As

a more suitable material for

ias (VG) for 40Å TaSiOx and s higher gate capacitance than t. Both systems show similar

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Drainn++-InGaAs : 20 nm

In0.7Ga0.3As QW channel : 10 nm

4o(100) Offcut Si substrate

In0.52Al0.48As bottom barrier : 100 nm

InxAl1-xAs buffer (x=0-0.52) : 0.7 μm(overshoot of In (0.52…0.7))

GaAs nucleation and buffer layer : 0.7μm

InP etch stop : 6 nm

In0.52Al0.48As : 3 nmInP layer : 2 nm

In0.52Al0.48As : 3 nm

Source

Gat

e

TaSiOx

Si δ-doping

In0.53Ga0.47As cap

InP etch stop

In0.52Al0.48As spacer/barrier

InP barrier layer

In0.7Ga0.3As QW

In0.52Al0.48As bottom barrier10nm

(b)

Fig. 4: Schematic of In0.7Ga0.3As QWFET on silicon with 2nm InP upper barrier layer and a 4nm TaSiOx high-K gate dielectric, which form a composite TaSiOx-InP gate stack.

FiwiSccaInan

FiveInshIn

Fig. 6(b): High-resolution TEM micrograph of In0.7Ga0.3As QW stack with 2nm InP top barrier layer. All III-V layers were grown using MBE.

Fig. 9(a): C-VG measured on the In0.7Ga0.3As QWFET with the composite 4nm TaSiOx-2nm InP gate stack showing minimal hysteresis and tOXE=22Å. Included is C-VG of the Schottky-gate QWFET (extracted at RF due to high JG) with tInAlAs=5nm and tOXE=33Å.

FwS

90GaAs nucleatiand buffer lay

Graded InAlAs

Si substrate

(a)In0.7Ga0.3A

40Å TaSiOx/20Å InPcomposite gate stack

G

ig. 5: Band diagram of In0.7Ga0.3As QW stack ith 2nm InP top barrier obtained using chrödinger-Poisson simulation, indicating arrier wave-function confinement in the

0.7Ga0.3As QW. Conduction band (EC), heavy nd light hole bands and Fermi level are shown.

Fig. 6(a): Cross-seIn0.7Ga0.3As QW stacksubstrate via 1.5μmlayers were grown us

Fig. 8: TEM mIn0.7Ga0.3As QWFEbarrier layer andhigh-K gate dieleTaSiOx-InP gate sconsists of TiN/Pt

ig. 7: Sheet carrier density and electron mobility ersus magnetic field of In0.7Ga0.3As QW stack with P top barrier layer at different temperatures,

howing no parallel conduction. The mobility in the 0.7Ga0.3As QW is 10,000 cm2/Vs at 300K.

Fig. 10: Drain curr(VGS) of LG=180nmcomposite 4nm T(tOXE=22Å). At VD

excellent subthreshodrain induced barrier

Fig. 9(b): JG versus VG of In0.7Ga0.3As QWFET with the same (i) composite gate stack and (ii) Schottky gate electrode as Fig. 9(a).

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1.5μm

0.5μm

As QW

InGaAs QW

k

Gate (TiN/Pt/Au)

InAlAs/GaAson Si

InGaAs n+ capLG=75nm

ectional TEM micrograph of k with InP top barrier layer on Si

m composite buffer. All III-V sing MBE.

micrograph of the LG=75nm ET showing the 2nm InP upper

d 4nm ALD-deposited TaSiOx ectric, which form a composite stack. The metal gate electrode /Au.

rent (ID) versus gate voltage m In0.7Ga0.3As QWFET with TaSiOx-2nm InP gate stack DS= 0.5V the device shows old slope (SS) =85mV/dec and r lowering (DIBL) =35mV/V.

IEDM09-32113.1.3

Fig. 13: Transconductance (Gm) characteristiIn0.7Ga0.3As QWFET with composite 4nm TaSiOx-2(tOXE=22Å). Peak Gm is 1750μS/μm at VDS= 0.5V, wreported for III-V QWFET with high-K dielectric.

Fig. 11: Drain current (ID) versus gate voltage (In0.7Ga0.3As QWFET with composite 4nm TaSiOx-2(tOXE=22Å). At VDS= 0.5V the device shows 0.49mA/μm over 0.5V VGS swing.

Fig. 15: Peak transconductance (Gm) as a function for the In0.7Ga0.3As QWFETs with composite gate versus that of the state-of-the-art III-V transistors dielectrics reported in literature [3-6].

Fig. 12: ID-VDS of LG=75nm In0.7Ga0.3As QWTaSiOx-2nm InP gate stack (tOXE=22Å).

Fig. 14: Measured effective electron velocomparing In0.7Ga0.3As QWFET with compogate stack (tOXE=22Å) and strained Si MOSFEoverdrive of (VGS−VT)=0.3V. InGaAs QWdielectric shows more than 3.5X increase in V

ics of LG=75nm 2nm InP gate stack

which is highest ever

(VGS) of LG=75nm 2nm InP gate stack

drive current of

of gate length (LG) stack of this work with high-K gate

Fig. 16: Subthreshold slope (SS) as a functiothe In0.7Ga0.3As QWFETs with composite gatethat of the state-of-the-art III-V transistors wireported in literature [3-6].

WFET with composite 4nm

ocity (Veff) versus DIBL site 4nm TaSiOx-2nm InP ET at VDS=0.5 V and gate

WFET with high-K gate Veff over strained Si.

on of gate length (LG) for e stack of this work versus ith high-K gate dielectrics

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