12V High Current Driver Touch MCU - Home - Holtek€¦ · applications such as touch LED dimming table lamps, touch nail phototherapy machines and various touch controlled products

12V High Current Driver Touch MCU

BS45F5930

Revision: V1.00 Date: ea 01ea 01

Rev. 1.00 ea 01 Rev. 1.00 3 ea 01

BS45F593012V High Current Driver Touch MCU


Table of Contents

Features ............................................................................................................ 5CPU eates ......................................................................................................................... 5Peipheal eates ................................................................................................................. 5

General Description ......................................................................................... 6Block Diagram .................................................................................................. 6Pin Assignment ................................................................................................ 7Pin Description ................................................................................................ 7Absolute Maximum Ratings ............................................................................ 8D.C. Characteristics ......................................................................................... 9

Opeating Voltage Chaacteistics .......................................................................................... 9Stand Cent Chaacteistics ............................................................................................. 9Opeating Cent Chaacteistics ........................................................................................... 9

A.C. Characteristics ....................................................................................... 10High Speed Intenal Oscillato – HIRC – eqenc Accac ............................................. 10Low Speed Intenal Oscillato Chaacteistics – LIRC .......................................................... 10Sstem Stat Up Time Chaacteistics ..................................................................................11

Input/Output Characteristics .........................................................................11LDO Electrical Characteristics ..................................................................... 12High Voltage Driver Output Electrical Characteristics ............................... 13OVP Electrical Characteristics ..................................................................... 13Power-on Reset Characteristics ................................................................... 13System Architecture ...................................................................................... 14

Clocking and Pipelining ......................................................................................................... 14Pogam Conte ................................................................................................................... 15Stack ..................................................................................................................................... 15Aithmetic and Logic Unit – ALU ........................................................................................... 16

Flash Program Memory ................................................................................. 17Stcte ................................................................................................................................ 17Special Vectos ..................................................................................................................... 17Look-p Tale ........................................................................................................................ 17Tale Pogam Example ........................................................................................................ 1In Cicit Pogamming – ICP ............................................................................................... 1On Chip Deg Sppot – OCDS ......................................................................................... 19

Data Memory .................................................................................................. 20Stcte ................................................................................................................................ 0Geneal Ppose Data Memo ............................................................................................ 0Special Ppose Data Memo ............................................................................................. 1

Special Function Register Description ........................................................ 22Indiect Addessing Registe – IAR0 IAR1 ........................................................................... Memo Pointes – MP0 MP1 .............................................................................................

Rev. 1.00 ea 01 Rev. 1.00 3 ea 01



Accmlato – ACC ............................................................................................................... 3Pogam Conte Low Registe – PCL ................................................................................. 3Look-p Tale Registes – TBLP TBHP TBLH .................................................................... 3Stats Registe – STATUS .................................................................................................... 3

Oscillators ...................................................................................................... 25Oscillato Oveview ............................................................................................................... 5System Clock Configurations ................................................................................................ 5High Speed Intenal RC Oscillato – HIRC ........................................................................... 5Intenal 3kHz Oscillato – LIRC ........................................................................................... 6

Operating Modes and System Clocks ......................................................... 26Sstem Clocks ...................................................................................................................... 6Sstem Opeation Modes ...................................................................................................... 7Contol Registe .................................................................................................................... Opeating Mode Switching ................................................................................................... 9Stand Cent Consideations .......................................................................................... 33Wake-p ................................................................................................................................ 33

Watchdog Timer ............................................................................................. 34Watchdog Time Clock Soce .............................................................................................. 34Watchdog Time Contol Registe ......................................................................................... 34Watchdog Time Opeation ................................................................................................... 35

Reset and Initialisation .................................................................................. 36Reset nctions .................................................................................................................... 36Reset Initial Conditions ......................................................................................................... 37

Input/Output Ports ......................................................................................... 39Pll-high Resistos ................................................................................................................ 39Pot A Wake-p ..................................................................................................................... 40I/O Pot Contol Registes ..................................................................................................... 40Pin-shaed nctions ............................................................................................................ 41I/O Pin Stctes .................................................................................................................. 4Pogamming Consideations ............................................................................................... 43

Timer/Event Counter ..................................................................................... 44Configuring the Timer/Event Counter Input Clock Source .................................................... 44Time Registe – TMR ........................................................................................................... 44Time Contol Registe – TMRC ............................................................................................ 45Time/Event Conte Opeation ............................................................................................ 45Pescale ............................................................................................................................... 45Pogamming Consideation ................................................................................................. 46

Touch Key Function ...................................................................................... 47Toch Ke Stcte .............................................................................................................. 47Toch Ke Registes Desciption .......................................................................................... 4Toch Ke Opeation ............................................................................................................. 5Pogsmming Consideations ................................................................................................ 55

Rev. 1.00 4 ea 01 Rev. 1.00 5 ea 01



High Voltage Driver Output ........................................................................... 56High Voltage Dive Otpt Registes ................................................................................... 56nctional Desciption ........................................................................................................... 5

Pulse Width Modulator .................................................................................. 59PWM Registes Desciption .................................................................................................. 59PWM Opeation ..................................................................................................................... 60PWM Otpt Contol ............................................................................................................. 6

Low Dropout Regulator – LDO ..................................................................... 63LDO Contol Registe ............................................................................................................ 63

Over Voltage Protection – OVP ..................................................................... 64Ove Voltage Potection Opeation ....................................................................................... 64Ove Voltage Potection Contol Registes ........................................................................... 64Inpt Offset Caliation ......................................................................................................... 66

Interrupts ........................................................................................................ 67Intept Registes ................................................................................................................. 67Intept Opeation ................................................................................................................ 69Extenal Intept ................................................................................................................... 70Toch Ke Modle Intept .................................................................................................. 70Time/Event Conte Intept ............................................................................................... 70Ove Voltage Potection Intept .......................................................................................... 70Time Base Intept ............................................................................................................... 71Intept Wake-p nction ................................................................................................... 7Pogamming Consideations ................................................................................................ 7

Application Descriptions – Dimming and Toning Touch Desk Lights ...... 73Intodction ........................................................................................................................... 73nctional Desciption ........................................................................................................... 73Hadwae Cicit Diagam ..................................................................................................... 75

Instruction Set ................................................................................................ 76Intodction ........................................................................................................................... 76Instction Timing .................................................................................................................. 76Moving and Tansfeing Data ............................................................................................... 76Aithmetic Opeations ............................................................................................................ 76Logical and Rotate Opeation ............................................................................................... 77Banches and Contol Tansfe ............................................................................................. 77Bit Opeations ....................................................................................................................... 77Tale Read Opeations ......................................................................................................... 77Othe Opeations ................................................................................................................... 77

Instruction Set Summary .............................................................................. 78Tale Conventions ................................................................................................................. 7

Instruction Definition ..................................................................................... 80Package Information ..................................................................................... 89

-pin SOP (150mil) Otline Dimensions ............................................................................... 9010-pin SOP (150mil) Otline Dimensions ............................................................................. 9116-pin NSOP (150mil) Otline Dimensions ........................................................................... 9

Rev. 1.00 4 ea 01 Rev. 1.00 5 ea 01



Features

CPU Features• Operatingvoltage

♦ fSYS=8MHz:4.75V~5.25V♦ VCC=6V~12V@±10%

• Upto0.5μsinstructioncyclewith8MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• Oscillatortypes:♦ InternalHighSpeed8MHzRC–HIRC♦ Internal32kHzRC–LIRC

• Multi-modeoperation:FAST,SLOW,IDLEandSLEEP

• Fullyintegratedinternaloscillatorsrequirenoexternalcomponents

• Allinstructionsexecutedinoneortwoinstructioncycles

• Tablereadinstructions

• 63powerfulinstructions

• 4-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:2K×16

• DataMemory:128×8

• WatchdogTimerfunction

• Upto5bidirectionalI/Olines

• SingleexternalinterruptlinesharedwithI/Opin

• Single8-bitprogrammableTimer/EventCounter

• SingleTimeBasefunctionforgenerationoffixedtimeinterruptsignals

• OverVoltageProtectionfunction

• Twohighvoltagedriveroutputlines

• 4touchkeyfunctions

• 2-channel8-bitPWMoutputfunction

• Flashprogrammemorycanbere-programmedupto100,000times

• Flashprogrammemorydataretention>10years

• Packagetypes:8/10-pinSOP

Rev. 1.00 6 ea 01 Rev. 1.00 7 ea 01



General DescriptionThedeviceisaFlashMemorytype8-bithighperformanceRISCarchitecturemicrocontrollerwithahighvoltagedriverofupto12V.WiththetouchkeyfunctionsprovidedinternallyandwiththeconvenienceofFlashMemorymulti-programmingfeatures, thisdevicerangehasall thefeaturestoofferdesignersareliableandeasymeansof implementingTouchKeyswithin theirproductsapplications.

The touchkey functions are fully integrated completely eliminating theneed for externalcomponents. Inaddition to theflashprogrammemory,othermemory includesanareaofDataMemory.Protective features suchasan internalWatchdogTimerandovervoltageprotectionfunctioncoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.

Thisdevice includesfully integrated lowandhighspeedoscillatorswhichrequirenoexternalcomponentsfortheirimplementation.Theabilitytooperateandswitchdynamicallybetweenarangeofoperatingmodesusingdifferentclocksourcesgivesuserstheabilitytooptimisemicrocontrolleroperationandminimisepowerconsumption.TheinclusionofflexibleI/Oprogrammingfeatures,TimeBase,Timer/EventCounter,PulseWidthModulatorandmanyotherfeaturesfurtherenhancedevicefunctionalityandflexibility.

The touchkeydevicewill findexcellentuse inahuge rangeofmodernTouchKeyproductapplicationssuchastouchLEDdimmingtablelamps,touchnailphototherapymachinesandvarioustouchcontrolledproductsthatrequire12Vhighcurrentandsoon.

Block Diagram

Intept Contolle

Bs

MUX

Reset Cicit

Stack4-Level

RAM1 x

ROMK x 16

WatchdogTime Pot A

Dive

VDD

HIRCMHz

LIRC3kHz

HVO1

HVO0

Time/Event Conte

Pin-Shaednction

LDO

PA0~PA4

VCC

Clock Sstem

Digital Peipheals

HT MCU Coe

High Voltage Analog Peipheals

HVO0

HVO1

OVP

Potection Cicit

Toch Ke

Time Base

I/O

PWM

Toch Ke

Pin- ShaedWith HVO0 & HVO1

KEY1~KEY4

Pin- ShaedWith Pot A

OVPI



5V

6V~1V

INT

PWM0

PWM1

Rev. 1.00 6 ea 01 Rev. 1.00 7 ea 01



Pin Assignment

134

765

10976

1345

16151413111109

134567

VLDO&VDDHVO0/PWM0/PWM1

VCCHVO1/PWM1/PWM0

VSSPA0/KEY1/ICPDAPA/KEY/ICPCKPA1/KEY3/OVPI

BS45F59308 SOP-A


VCCHVO1/PWM1/PWM0

PA4/INT/OVPI

VSSPA0/KEY1/ICPDAPA/KEY/ICPCKPA1/KEY3/OVPIPA3/KEY4/OVPI

BS45F593010 SOP-A


VCCHVO1/PWM1/PWM0

PA4/INT/OVPI

NC

NCOCDSCK

VSSPA0/KEY1/ICPDAPA/KEY/ICPCKPA1/KEY3/OVPIPA3/KEY4/OVPI

NC

NCOCDSDA

BS45V593016 NSOP-A

Note:1.Ifthepin-sharedpinfunctionshavemultipleoutputs,thedesiredpin-sharedfunctionisdeterminedbythecorrespondingsoftwarecontrolbits.

2.The16-pinNSOPpackagetypeisonlyforOCDSEVchip.TheOCDSDAandOCDSCKpinsaretheOCDSdedicatedpins.

Pin DescriptionPin Name Function OPT I/T O/T Descriptions

PA0/KEY1/ICPDA

PA0PAPUPAWUPAS0

ST CMOS Geneal ppose I/O. Registe enaled pll-p and wake-p

KEY1 PAS0TKMC1 ST CMOS Toch ke inpt

ICPDA — ST CMOS ICP addess/data

PA1/KEY3/OVPI

PA1PAPUPAWUPAS0



OVPI PAS0 ST — OVP inpt

PA/KEY/ICPCK

PAPAPUPAWUPAS0


KEY PAS0TKMC1 ST CMOS Toch ke inpt

ICPCK — ST CMOS ICP clock

Rev. 1.00 ea 01 Rev. 1.00 9 ea 01



Pin Name Function OPT I/T O/T Descriptions

PA3/KEY4/OVPI

PA3PAPUPAWUPAPS0




PA4/INT/OVPI

PA4PAPUPAWUPAS1


INT INTEG ST — Extenal Intept inpt


HVO0/PWM0/PWM1

HVO0 HVOC1 — CMOS High voltage dive otpt

PWM0 HVOC1 — CMOS PWM channel 0 otpt


HVO1/PWM1/PWM0

HVO1 HVOC1 — CMOS High voltage dive otpt



VCC VCC — PWR — LDO inpt powe sppl High voltage dive otpt and Level Shift inpt

VLDO/VDDVLDO — PWR — LDO otpt digital positive powe sppl

VDD — PWR — Digital positive powe sppl

VSS VSS — PWR — Digital negative powe sppl

The following pins ae onl fo the BS45V5930

NC NC — — — No connection

OCDSDA OCDSDA — ST CMOS OCDS Addess/Data fo EV chip onl

OCDSCK OCDSCK — ST — OCDS Clock pin fo EV chip onl

Legend:I/T:Inputtype; O/T:Outputtype; OPT:Optionalbyregisteroption; PWR:Power; ST:SchmittTriggerinput; CMOS:CMOSoutput

Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOHTotal....................................................................................................................................-80mAIOLTotal..................................................................................................................................... 80mATotalPowerDissipation......................................................................................................... 500mW

Note:Theseare stress ratingsonly.Stressesexceeding the range specifiedunder "AbsoluteMaximumRatings"maycausesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.

Rev. 1.00 ea 01 Rev. 1.00 9 ea 01



D.C. CharacteristicsFordatainthefollowingtables,notethatfactorssuchasoscillatortype,operatingvoltage,operatingfrequency,pin loadconditions, temperatureandprograminstruction type,etc.,canallexertaninfluenceonthemeasuredvalues.

Operating Voltage Characteristics Ta=-40°C~5°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDDOpeating Voltage – HIRC — fSYS = fHIRC = MHz 4.75 — 5.5 VOpeating Voltage – LIRC — fSYS = fLIRC = 3kHz 4.75 — 5.5 V

Standby Current CharacteristicsTa=5°C

Symbol Standby ModeTest Conditions

Min. Typ. Max.Max.

UnitVDD Conditions 85°C

ISTB

SLEEP Mode 5V WDT on — 330 560 570 μAIDLE0 Mode – LIRC 5V fSUB on — 30 555 560 μAIDLE1 Mode – HIRC 5V fSUB on fSYS = MHz — 600 00 960 μA

Notes:Whenusingthecharacteristictabledata,thefollowingnotesshouldbetakenintoconsideration:1.Anydigitalinputsaresetupinanon-floatingcondition.2.Allmeasurementsaretakenunderconditionsofnoloadandwithallperipheralsinanoffstate.3.TherearenoDCcurrentpaths.4.AllStandbyCurrentvaluesaretakenafteraHALTinstructionexecutionthusstoppingall instructionexecution.

Operating Current CharacteristicsTa=5°C

Symbol Operating ModeTest Conditions


IDDSLOW Mode – LIRC 5V fSYS = 3kHz — 350 600 μAAST Mode – HIRC 5V fSYS = MHz — 3 mA

Notes:Whenusingthecharacteristictabledata,thefollowingnotesshouldbetakenintoconsideration:1.Anydigitalinputsaresetupinanon-floatingcondition.2.Allmeasurementsaretakenunderconditionsofnoloadandwithallperipheralsinanoffstate.3.TherearenoDCcurrentpaths.4.AllOperatingCurrentvaluesaremeasuredusingacontinuousNOPinstructionprogramloop.

Rev. 1.00 10 ea 01 Rev. 1.00 11 ea 01



A.C. CharacteristicsFordatainthefollowingtables,notethatfactorssuchasoscillatortype,operatingvoltage,operatingfrequencyandtemperatureetc.,canallexertaninfluenceonthemeasuredvalues.

High Speed Internal Oscillator – HIRC – Frequency AccuracyDuringtheprogramwritingoperationthewriterwill trimtheHIRCoscillatoratauserselectedHIRCfrequencyanduserselectedvoltageof5V.


Min. Typ. Max. UnitVDD Temp.

fHIRCMHz Wite Timmed HIRC eqenc 5V

5°C -1% +1%MHz

-40°C ~ 5°C -% +%

Notes:1.The5VvalueforVDDisprovidedasthisistheselectablefixedvoltageatwhichtheHIRCfrequencyistrimmedbythewriter.

2.Itisrecommendedthatthetrimvoltageisfixedat5Vforapplicationvoltagerangesfrom4.75Vto5.25V.3.Theminimumandmaximumtolerancevaluesprovidedinthetableareonlyforthefrequencyatwhichthewriter trimstheHIRCoscillator.After trimmingat thischosenspecificfrequencyanychangeinHIRCoscillatorfrequencyusingtheoscillatorregistercontrolbitsbytheapplicationprogramwillgiveafrequencytolerancetowithin±20%.

Low Speed Internal Oscillator Characteristics – LIRCTa=5°C, unless otherwise specified


Min. Typ. Max. UnitVDD Temp.

fLIRC LIRC eqenc 5V~5.5V5°C -10% 3 +10%

kHz-40°C ~ 5°C -50% 3 +60%

tSTART LIRC Stat Up Time — — — — 500 μs

Rev. 1.00 10 ea 01 Rev. 1.00 11 ea 01



System Start Up Time Characteristics Ta=-40°C ~5°C



tSST

Sstem Stat-p TimeWake-p fom condition whee fSYS is off

— fSYS = fH ~ fH/64 fH = fHIRC — 16 — tHIRC

— fSYS = fSUB = fLIRC — — tLIRC

Sstem Stat-p TimeWake-p fom condition whee fSYS is on

— fSYS = fH ~ fH/64 fH = fHIRC — — tH

— fSYS = fSUB = fLIRC — — tSUB

Sstem Speed Switch TimeAST to SLOW Mode oSLOW to AST Mode

— fHIRC switches from off → on — 16 — tHIRC

tRSTD

Sstem Reset Dela TimeReset Soce fom Powe-on Reset

— RRPOR = 5 V/ms4 4 54 ms

Sstem Reset Dela TimeWDTC Softwae Reset — —

Sstem Reset Dela TimeReset Soce fom WDT Overflow

— — 14 16 1 ms

tSRESETMinimm Softwae Reset Width to Reset — — 45 90 10 μs

Notes:1.For theSystemStart-up timevalues,whetherfSYS isonoroffdependsuponthemodetypeandthechosenfSYSsystemoscillator.DetailsareprovidedintheSystemOperatingModessection.

2.Thetimeunits,shownbythesymbolstHIRCetc.aretheinverseofthecorrespondingfrequencyvaluesasprovidedinthefrequencytables.ForexampletHIRC=1/fHIRC,tSYS=1/fSYSetc.

3.If theLIRCisusedasthesystemclockandif it isoffwhenintheSLEEPMode,thenanadditionalLIRCstartuptime,tSTART,asprovidedintheLIRCfrequencytable,mustbeaddedtothetSSTtimeinthetableabove.

4.TheSystemSpeedSwitchTimeiseffectivelythetimetakenforthenewlyactivatedoscillatortostartup.

Input/Output CharacteristicsTa=5°C



VILInpt Low Voltage fo I/O Pots o Inpt Pins

5V — 0 — 1.5V

— — 0 — 0.VDD

VIHInpt High Voltage fo I/O Pots o Inpt Pins

5V — 3.5 — 5V

— — 0.VDD — VDD

IOH Soce Cent fo I/O Pins 5V VOH = 0.9VDD - -16 — mAIOL I/O Pot Sink Cent 5V VOL=0.1VDD 3 65 — mARPH Pll-high Resistance fo I/O Pots 5V — 10 30 50 kΩ

RPHPll-high Resistance fo I/O Pots(OCDSCK and OCDSDA fo BS45V5930) 5V — 10 30 50 kΩ

ILEAK Inpt Leakage Cent 5V VIN = VDD o VIN = VSS — — ±1 μA

Note:TheRPHinternalpullhighresistancevalueiscalculatedbyconnectingtogroundandenablingtheinputpinwithapull-highresistorandthenmeasuringtheinputsinkcurrentat thespecifiedsupplyvoltagelevel.DividingthevoltagebythismeasuredcurrentprovidestheRPHvalue.

Rev. 1.00 1 ea 01 Rev. 1.00 13 ea 01



LDO Electrical CharacteristicsVIN = VOUT +1V CLOAD = 1μ Ta = 5°C nless othewise specif


Min. Typ. Max. UnitVIN Conditions

VIN Inpt Voltage — — 5.1 6 1 V

VOUT Otpt Voltage— ILOAD = 1mA VOUT = 5.0V -3% 5.0 3% V

— Ta = -40°C ~ 5°CILOAD = 1mA VOUT = 5.0V -5% 5.0 5% V

ΔVLOAD Load Reglation(1) — 1mA ≤ ILOAD ≤ 40mA, — 0.015 0.033 %/mA

VDROP Dopot Voltage()

— ΔVOUT = % ILOAD = 1mA — 0 — mV— ΔVOUT = % ILOAD = 10mA — 100 — mV

— VIN = VOUT + 1.5V ΔVOUT = % ILOAD = 40mA — 400 600 mV

IOUT Otpt Cent— VIN = VOUT + 1V VOUT = 5V

ΔVOUT = -3% 5 — — mA

— VIN = VOUT + V VOUT = 5VΔVOUT = -3% 40 — — mA

IQ Qiescent Cent 1V No load — 30 — μAΔVLINE Line Reglation — VOUT + 1V ≤ VIN ≤ 1V ILOAD = 1mA — — 0. %/VTC Temperature Coefficient — Ta = -40°C ~ 5°C ILOAD = 10mA — ±1.5 ± mV/°C

RR Ripple Rejection(3) — VIN = 10VDC+VP-P(AC) ILOAD ≤ 40mA, f = 120Hz 35 — — dB

tLDOSTART LDO Statp Time 6V ILOAD = 1mA VOUT settle to ± 5% — — 10 msVCCO VCCO Voltage — VIN = 5.1V ~ 1V - 5% 0.×VIN + 5% V

Notes:1.Loadregulationismeasuredataconstantjunctiontemperature,usingpulsetestingwithalowONtimeandisguaranteeduptothemaximumpowerdissipation.Powerdissipationisdeterminedbytheinput/outputdifferentialvoltageandtheoutputcurrent.Guaranteedmaximumpowerdissipationwillnotbeavailableoverthefull input/outputrange.ThemaximumallowablepowerdissipationatanyambienttemperatureisPD=(TJ(MAX)-Ta)/θJA

2.Dropoutvoltageisdefinedastheinputvoltageminustheoutputvoltagethatproducesa2%changeintheoutputvoltagefromthevalueatappointedVIN.

3.Ripplerejectionratiomeasurementcircuit.RR=20×log(ΔVIN/ΔVOUT).

0.33μ

1 3

10μ

RL

OtptGND

LDOVIN VOUT

Rev. 1.00 1 ea 01 Rev. 1.00 13 ea 01



High Voltage Driver Output Electrical CharacteristicsTa= 5°C



VIN Inpt Voltage — — VDD — 1 VIOH Soce Cent fo PAn Pins — VOH = 0.9 × VIN VIN = 6V -50 -300 — mAIOL Sink Cent fo PAn Pins — VOL = 0.1 × VIN VIN = 6V 40 50 — mA

OVP Electrical Characteristics Ta= 5°C



VDD Opeating Voltage — — 4.75 — 5.5 V

IOVP Opeating Cent 5V OVPEN = 1 OVPDAH[3:0]OVPDAL[7:0] = 1000 0000 0000 — 145 10 μA

VOS Inpt Offset Voltage 5V With caliation - — mVVHYS Hsteesis 5V — 0 40 60 mV

VCMCommon Mode Voltage Range 5V — VSS — VDD -

1.4 V

DNL Diffeential Nonlineait 5V DAC VRE = VDD — — ±3 LSBINL Integal Nonlineait 5V DAC VRE = VDD — — ±4 LSB

Power-on Reset CharacteristicsTa=5°C



VPOR VDD Stat Voltage to Ense Powe-on Reset — — — — 100 mV

RRPOR VDD Rising Rate to Ense Powe-on Reset — — 0.035 — — V/ms

tPORMinimm Time fo VDD Stas at VPOR to Ense Powe-on Reset — — 1 — — ms

VDD

tPOR RRPOR

VPOR

Time

Rev. 1.00 14 ea 01 Rev. 1.00 15 ea 01



System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.TherangeofthedevicetakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningscheme is implemented insuchaway that instruction fetchingand instructionexecutionareoverlapped,hence instructionsareeffectivelyexecuted inonecycle,with theexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitectural featuresensure thataminimumofexternalcomponents is required toprovideafunctional I/Ocontrolsystemwithmaximumreliabilityandflexibility.Thismakes thedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derivedfromeitheraHIRCorLIRCoscillator issubdivided intofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

etch Inst. (PC+)Execte Inst. (PC+1)

Oscillato Clock(Sstem Clock)

Phase Clock T1

Phase Clock T

Phase Clock T3

Phase Clock T4

Pogam Conte

Pipelining

PC PC+1 PC+

etch Inst. (PC+1)Execte Inst. (PC)

Execte Inst. (PC-1)etch Inst. (PC)

System Clocking and Pipelining

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

Rev. 1.00 14 ea 01 Rev. 1.00 15 ea 01



Execte Inst. 1etch Inst.

1 MOV A [1H] CALL DELAY3 CPL [1H]4 :5 :6 DELAY: NOP

etch Inst. 1Execte Inst. etch Inst. 3 lsh Pipeline

etch Inst. 6 Execte Inst. 6etch Inst. 7

Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas"JMP"or"CALL" thatdemandsa jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

Program CounterHigh Byte Low Byte (PCL)PC10~PC PCL7~PCL0

Program Counter

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly;however,asonlythis lowbyteisavailable formanipulation, the jumpsare limited to thepresentpageofmemory that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisorganizedinto4levelsandneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.Theactivatedlevel is indexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.

Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

Rev. 1.00 16 ea 01 Rev. 1.00 17 ea 01



Stack Level

Stack Level 1

Stack Level 3Pogam Memo

Pogam Conte

Top of Stack

Stack Level 4Bottom of Stack

StackPointe

Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrementINCA,INC,DECA,DEC

• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

Rev. 1.00 16 ea 01 Rev. 1.00 17 ea 01



Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthedevicetheProgramMemory isFlash type,whichmeans itcanbeprogrammedandre-programmeda largenumberof times,allowingtheuser theconvenienceofcodemodificationonthesamedevice.Byusingtheappropriateprogrammingtools,theFlashdeviceoffersuserstheflexibilitytoconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof2K×16bits.TheProgramMemory isaddressedby theProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.

000H004H

014H

7H

Reset

InteptVectos

16 its

Program Memory Structure

Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reserved foruseby thedevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressofthelookupdatatoberetrievedinthetablepointerregisters,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe"TABRD[m]"or"TABRDL[m]"instructions,respectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas0.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

Last Page o TBHP Registe

TBLP Registe

Pogam Memo

Registe TBLH Use Selected Registe

Addess

Data16 its

High Bte Low Bte

Rev. 1.00 1 ea 01 Rev. 1.00 19 ea 01



Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.Thisexampleusesrawtabledata located in theProgramMemorywhich isstoredthereusingtheORGstatement.ThevalueatthisORGstatementis"0700H"whichreferstothestartaddressofthelastpagewithinthe2KProgramMemoryofthemicrocontroller.Thetablepointerlowbyteregisterissetupheretohaveaninitialvalueof"06H".ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress"0706H"or6locationsafterthestartofthelastpage.NotethatthevalueforthetablepointerisreferencedtothefirstaddressspecifiedbyTBLPandTBHPifthe"TABRD[m]"instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe"TABRDL[m]"instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2::mov a,06h ; initialise low table pointer - note that this address is referencedmov tblp,a ; to the last page or the page that tbhp pointedmov a,07h ; initialise high table pointermov tbhp,a::tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "0706H" transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address "0705H" transferred to ; tempreg2 and TBLH in this example the data "1AH" is ; transferred to tempreg1 and data "0FH" to register tempreg2::org 0700h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh

In Circuit Programming – ICPTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

Rev. 1.00 1 ea 01 Rev. 1.00 19 ea 01



Holtek Writer Pins MCU Programming Pins Pin DescriptionICPDA PA0 Pogamming Seial Data/AddessICPCK PA Pogamming ClockVDD VDD Powe SpplVSS VSS Gond

TheProgramMemorycanbeprogrammedserially in-circuitusing this4-wire interface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditional linefor theclock.Twoadditional linesarerequiredfor thepowersupply.The technicaldetails regarding the in-circuitprogrammingof thedevice arebeyond the scopeof thisdocument andwill be supplied insupplementaryliterature.

Duringtheprogrammingprocess,theusermusttakecontroloftheICPDAandICPCKpinsfordataandclockprogrammingpurposestoensurethatnootheroutputsareconnectedtothesetwopins.

* *

Wite_VDD

ICPDA

ICPCK

Wite_VSS

To othe Cicit

VDD

PA0

PA

VSS

Wite Connecto Signals

MCU PogammingPins

Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1kΩorthecapacitanceof*mustbelessthan1nF.

On Chip Debug Support – OCDSThereisanEVchipnamedBS45V5930whichisusedtoemulatetheBS45F5930device.TheEVchipdevicealsoprovidesan"On-ChipDebug"functiontodebugtherealMCUdeviceduringthedevelopmentprocess.TheEVchipandtherealMCUdevicearealmostfunctionallycompatibleexcept for"On-ChipDebug" functionandpackage type.Userscanuse theEVchipdevice toemulatetherealchipdevicebehaviorbyconnectingtheOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApinis theOCDSData/Addressinput/outputpinwhiletheOCDSCKpinistheOCDSclockinputpin.FormoredetailedOCDSinformation,refertothecorrespondingdocumentnamed"Holteke-Linkfor8-bitMCUOCDSUser’sGuide".

Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSDA OCDSDA On-Chip Deg Sppot Data/Addess inpt/otptOCDSCK OCDSCK On-Chip Deg Sppot Clock inpt

VDD VDD Powe SpplVSS VSS Gond

Rev. 1.00 0 ea 01 Rev. 1.00 1 ea 01



Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.

StructureCategorizedintotwotypes,thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

TheDataMemoryhasabank,whichis implementedin8-bitwideMemory.TheDataMemoryBankiscategorizedintotwotypes,thespecialPurposeDataMemoryandtheGeneralPurposeDataMemory.

TheaddressrangeoftheSpecialPurposeDataMemoryforthedeviceisfrom00Hto3FHwhiletheGeneralPurposeDataMemoryaddressrangeisfrom40HtoBFH.

Special Purpose Data Memory General Purpose Data Memory

Available Banks Bank: Address Capacity Bank: Address

0 Bank 0: 00H~3H 1× 0: 40H~BH

Data Memory Summary

00H

3H40H

BH

Special Ppose Data Memo

Geneal Ppose Data Memo

Bank 0

(Bank 0)

(Bank 0)

Data Memory Structure

General Purpose Data MemoryAllmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.Byusingthebitoperationinstructions individualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.

Rev. 1.00 0 ea 01 Rev. 1.00 1 ea 01



Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue"00H".

00H IAR0

01H MP0

0H IAR1

03H MP1

04H

05H ACC

06H PCL

07H TBLP

0H TBLH

09H

RSTC

0AH STATUS

0BH

0CH

0DH

0EH

0H

10H

11H

1H

19H

1H

1BH

1AH

1DH

1CH

1H

1EH

13H

14H

15H

16H

17H

PAS1

PAPU

PAWU

0H

1H

H

9H

H

AH

BH

3H

4H

5H

6H

7H

PA

PAC

INTC1

WDTC

PSCR

Bank 0 Bank0

EH

30H

31H

3H

33H

34H

35H

36H

37H

3H

CH

DH

: Unsed ead as “00”

H

TBC

PAS0

TBHP

HVOC

HVOC1

DIVOC

TMRC

TKMROH

TKC0

TK16DL

OVPDAH

TKTMR

TKMC1

TMR

OVPC0

OVPC1

TKC1

TKM16DH

TKM16DL

TKMROL

OVPDAL

TKMC0

PWM0DATA

PWMC

PWM1DATA

TK16DH

SCC

HIRCC

INTC0

INTEG

39H

3BH

3AH

3DH

3CH

3H

3EH

Special Purpose Data Memory

Rev. 1.00 ea 01 Rev. 1.00 3 ea 01



Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsections;howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Register – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof"00H"andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1 TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedto,istheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileIAR1andMP1registerpairareusedtoaccessdatafromanybank.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 code´org 00hstart: mov a,04h ; setup size of block mov block,a mova,offsetadres1 ;AccumulatorloadedwithfirstRAMaddress movmp0,a ;setupmemorypointerwithfirstRAMaddressloop: clrIAR0 ;clearthedataataddressdefinedbymp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.

Rev. 1.00 ea 01 Rev. 1.00 3 ea 01



Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuserdefinedregisterandanother, it isnecessary todo thisbypassingthedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCL Toprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBHP, TBLH Thesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointersandindicate thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe"INC"or"DEC"instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe"CLRWDT"or"HALT"instruction.ThePDFflagisaffectedonlybyexecutingthe"HALT"or"CLRWDT"instructionorduringasystempower-up.

TheZ,OV,AC,andCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe"CLRWDT"instruction.PDFissetbyexecutingthe"HALT"instruction.

Rev. 1.00 4 ea 01 Rev. 1.00 5 ea 01



• TOisclearedbyasystempower-uporexecutingthe"CLRWDT"or"HALT"instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

• STATUS Register

Bit 7 6 5 4 3 2 1 0Name — — TO PD OV Z AC CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 x x x x

"x": nknownBit7~6 Unimplemented,readas"0"Bit5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe"CLRWDT"or"HALT"instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe"CLRWDT"instruction1:Byexecutingthe"HALT"instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

The"C"flagisalsoaffectedbyarotatethroughcarryinstruction.

Rev. 1.00 4 ea 01 Rev. 1.00 5 ea 01



OscillatorsVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughtheapplicationprogramandrelevantcontrolregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfortheWatchdogTimerandTimeBaseInterrupts.Twofullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovidedtoformarangeofbothfastandslowsystemoscillators.Thehigherfrequencyoscillatorprovideshigherperformancebutcarrywithit thedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillator.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock,thedevicehastheflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Frequency

Intenal High Speed RC HIRC MHz

Intenal Low Speed RC LIRC 3kHz

Oscillator Types

System Clock ConfigurationsThereare twomethodsofgeneratingthesystemclock,ahighspeedoscillatoranda lowspeedoscillator.Thehighspeedoscillator is the internal8MHzRCoscillator,HIRC.The lowspeedoscillatoristheinternal32kHzRCoscillator,LIRC.ThefrequencyoftheslowspeedorhighspeedsystemclockisalsodeterminedusingtheCKS2~CKS0bitsintheSCCregister.

High Speed Oscillato

PescaleHIRC fH

fH/

fH/4

fH/

fH/16

fH/3

fH/64

CKS~CKS0

fSYS

Low Speed Oscillato

LIRC

IDLE0SLEEP

IDLESLEEP

fSUB

fSUB

fLIRC

HIRCEN

System Clock Configurations

High Speed Internal RC Oscillator – HIRCThehighspeedinternalRCoscillator isafullyintegratedsystemoscillatorrequiringnoexternalcomponents.TheinternalRCoscillatorhasafixedfrequencyof8MHz.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.

Rev. 1.00 6 ea 01 Rev. 1.00 7 ea 01



Internal 32kHz Oscillator – LIRCThe Internal32kHzSystemOscillator is the lowfrequencyoscillator. It isa fully integratedRCoscillatorwith a typical frequencyof32kHz, requiringno external components for itsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.

Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcourseviceversa,lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthedevicewithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically, theusercanoptimisetheoperationof theirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockselectionsusingregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequency,fH,orlowfrequency,fSUB,source,andisselectedusingtheCKS2~CKS0bits intheSCCregister.ThehighspeedsystemclockissourcedfromHIRCoscillator.ThelowspeedsystemclocksourcecanbesourcedfromtheLIRCoscillator.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

HIRCENPescale

High Speed Oscillato

Low Speed Oscillato

fH/

fH/16

fH/64

fH/

fH/4

fH/3

CKS~CKS0

fSYS

fSUB fSUB

LIRC

fLIRC

fLIRC

HIRC

fH

WDT

fSYS/4Time BasefSUB

fSYS

Pescale

CLKSEL[1:0]

fPSC

IDLE0SLEEP

IDLESLEEP

TB[:0]

Device Clock Configuration

Note:WhenthesystemclocksourcefSYSisswitchedtofSUBfromfH,thehighspeedoscillatorcanbestoppedtoconservethepowerorcontinuetooscillatetoprovidetheclocksource,fH~fH/64,forperipheralcircuittouse,whichisdeterminedbyconfiguringthecorrespondinghighspeedoscillatorenablecontrolbit.

Rev. 1.00 6 ea 01 Rev. 1.00 7 ea 01



System Operation ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller,theFASTModeandSLOWMode.Theremainingfourmodes,theSLEEP,IDLE0,IDLE1andIDLE2ModeareusedwhenthemicrocontrollerCPUisswitchedofftoconservepower.

Operation Mode CPU

Register SettingfSYS fH fSUB fLIRC

FHIDEN FSIDEN CKS[2:0]AST Mode On x x 000~110 On On On OnSLOW Mode On x x 111 On On/Off(1) On On

IDLE0 Mode Off 0 1000~110 Off

Off On On111 On

IDLE1 Mode Off 1 1 xxx On On On On

IDLE Mode Off 1 0000~110 On

On Off On111 Off

SLEEP Mode Off 0 0 xxx Off Off Off On ()

"x ": Don’t caeNote:1.ThefHclockwillbeswitchedonoroffbyconfiguringthecorrespondingoscillatorenable

bitintheSLOWmode.2.ThefLIRCclockwillbeswitchedonsincetheWDTfunctionisalwaysenabledintheSLEEPmode.

FAST ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbyoneofthehighspeedoscillator.Thismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromthehighspeedoscillator,HIRC.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64, theactualratiobeingselectedbytheCKS2~CKS0bits intheSCCregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.TheclocksourceusedwillbefromfSUB.ThefSUBclockisderivedfromtheLIRCoscillator.

SLEEP ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENandFSIDENbitarelow.IntheSLEEPmodetheCPUwillbestopped,andthefSUBclocktoperipheralwillbestoppedtoo.HoweverthefLIRCclockstillcontinuestooperatesincetheWDTfunctionisalwaysenabled.

IDLE0 Mode TheIDLE0ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitintheSCCregister is lowandtheFSIDENbit intheSCCregister ishigh.IntheIDLE0ModetheCPUwillbeswitchedoffbutthelowspeedoscillatorwillbeturnedontodrivesomeperipheralfunctions.

Rev. 1.00 ea 01 Rev. 1.00 9 ea 01



IDLE1 ModeTheIDLE1ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitintheSCCregisterishighandtheFSIDENbitintheSCCregisterishigh.IntheIDLE1ModetheCPUwillbeswitchedoffbutboththehighandlowspeedoscillatorswillbeturnedontoprovideaclocksourcetokeepsomeperipheralfunctionsoperational.

IDLE2 ModeTheIDLE2ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitintheSCCregisterishighandtheFSIDENbitintheSCCregisterislow.IntheIDLE2ModetheCPUwillbeswitchedoffbutthehighspeedoscillatorwillbeturnedontoprovideaclocksourcetokeepsomeperipheralfunctionsoperational.

Control RegisterThe registers,SCCandHIRCC,areused tocontrol the systemclockand thecorrespondingoscillatorconfigurations.

Register Name

Bit7 6 5 4 3 2 1 0

SCC CKS CKS1 CKS0 — — — HIDEN SIDENHIRCC — — — — — — HIRC HIRCEN

System Operating Mode Control Registers List

• SCC Register

Bit 7 6 5 4 3 2 1 0Name CKS CKS1 CKS0 — — — HIDEN SIDEN

R/W R/W R/W R/W — — — R/W R/W

POR 0 0 0 — — — 0 0

Bit7~5 CKS2~CKS0:Systemclockselection000:fH001:fH/2010:fH/4011:fH/8100:fH/16101:fH/32110:fH/64111:fSUB

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.InadditiontothesystemclocksourcedirectlyderivedfromfHorfSUB,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

Bit4~2 Unimplemented,readas"0"Bit1 FHIDEN:HighFrequencyoscillatorcontrolwhenCPUisswitchedoff

0:Disable1:Enable

Thisbit isusedtocontrolwhether thehighspeedoscillator isactivatedorstoppedwhentheCPUisswitchedoffbyexecutingan"HALT"instruction.

Bit0 FSIDEN:LowFrequencyoscillatorcontrolwhenCPUisswitchedoff0:Disable1:Enable

Thisbit isusedtocontrolwhether the lowspeedoscillator isactivatedorstoppedwhen theCPUisswitchedoffbyexecutingan"HALT" instruction. If thisbit isclearedto0buttheWDTfunctionisalwaysenabled,theLIRCoscillatorwillalsobeenabled.

Rev. 1.00 ea 01 Rev. 1.00 9 ea 01



• HIRCC Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — HIRC HIRCEN

R/W — — — — — — R/W R/W

POR — — — — — — 0 1

Bit7~2 Unimplemented,readas"0"Bit1 HIRCF:HIRCoscillatorstableflag

0:Unstable1:Stable

Thisbit isusedto indicatewhether theHIRCoscillator isstableornot.WhentheHIRCENbit isset to1 toenable theHIRCoscillator, theHIRCFbitwill firstbeclearedto0andthensetto1aftertheHIRCoscillatorisstable.

Bit0 HIRCEN:HIRCoscillatorenablecontrol0:Disable1:Enable

Operating Mode Switching Thedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimpleterms,modeswitchingbetweentheFASTModeandSLOWModeisexecutedusingtheCKS2~CKS0bitsintheSCCregisterwhilemodeswitchingfromtheFAST/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenanHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionoftheFHIDENandFSIDENbitsintheSCCregister.

FASTfSYS=fH~fH/64

fH onCPU nfSYS onfSUB on

SLOWfSYS=fSUBfSUB on

CPU nfSYS onfH on/off

IDLE0HALT instction exected

CPU stopHIDEN=0SIDEN=1

fH offfSUB on



fH onfSUB on



fH onfSUB off

SLEEPHALT instction exected


fH offfSUB off

Rev. 1.00 30 ea 01 Rev. 1.00 31 ea 01



FAST Mode to SLOW Mode Switching Whenrunning in theFASTMode,whichuses thehighspeedsystemoscillator,and thereforeconsumesmorepower, the systemclock can switch to run in theSLOWModeby set theCKS2~CKS0bitsto"111"intheSCCregister.Thiswill thenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequires thisoscillator tobestablebeforefullmodeswitchingoccurs.

FAST Mode

SLOW Mode

CKS~CKS0 = 111

SLEEP Mode

HIDEN=0 SIDEN=0HALT instction is exected

IDLE0 Mode


IDLE1 Mode


IDLE2 Mode


Rev. 1.00 30 ea 01 Rev. 1.00 31 ea 01



SLOW Mode to FAST Mode Switching InSLOWmodethesystemclockisderivedfromfSUB.WhensystemclockisswitchedbacktotheFASTModefromfSUB, theCKS2~CKS0bitsshouldbeset to"000"~"110"andthenthesystemclockwillrespectivelybeswitchedtofH~fH/64.

However, if fH isnotused inSLOWmodeand thusswitchedoff, itwill takesometime tore-oscillateandstabilisewhenswitchingtotheFASTModefromtheSLOWMode.ThisismonitoredusingtheHIRCFbit intheHIRCCregister.ThetimedurationrequiredforthehighspeedsystemoscillatorstabilizationisspecifiedintheA.C.characteristics.

FAST Mode

SLOW Mode

CKS~CKS0 = 000~110

SLEEP Mode


IDLE0 Mode


IDLE1 Mode


IDLE2 Mode


Entering the SLEEP Mode ThereisonlyonewayforthedevicetoentertheSLEEPModeandthatistoexecutethe"HALT"instructionintheapplicationprogramwithboththeFHIDENandFSIDENbitsintheSCCregisterequalto"0".InthismodealltheclocksandfunctionswillbeswitchedoffexcepttheWDTfunction.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• The systemclockwill be stoppedand the applicationprogramwill stop at the "HALT"instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

• TheWDTwillbeclearedandresumecountingastheWDTfunctionisalwaysenabled.

Rev. 1.00 3 ea 01 Rev. 1.00 33 ea 01



Entering the IDLE0 Mode ThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeFHIDENbitintheSCCregisterequalto"0"andtheFSIDENbitintheSCCregisterequalto"1".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThefHclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instruction,butthefSUBclockwillbeon.





Entering the IDLE1 Mode ThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwithboththeFHIDENandFSIDENbitsintheSCCregisterequalto"1".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThefHandfSUBclockswillbeonbuttheapplicationprogramwillstopatthe"HALT"instruction.





Entering the IDLE2 Mode ThereisonlyonewayforthedevicetoentertheIDLE2Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeFHIDENbitintheSCCregisterequalto"1"andtheFSIDENbit inSCCregisterequal to"0".Whenthis instructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThefHclockwillbeonbutthefSUBclockwillbeoffandtheapplicationprogramwillstopatthe"HALT"instruction.





Rev. 1.00 3 ea 01 Rev. 1.00 33 ea 01



Standby Current Considerations AsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1andIDLE2Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerif thepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.Alsonote thatadditionalstandbycurrentwillalsoberequirediftheLIRCoscillatorhasenabled.

In theIDLE1andIDLE2Modethehighspeedoscillator ison, if theperipheral functionclocksourceisderivedfromthehighspeedoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Wake-upTominimisepowerconsumptionthedevicecanenter theSLEEPoranyIDLEMode,wheretheCPUwillbeswitchedoff.However,whenthedeviceiswokenupagain,itwilltakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabliseandallownormaloperationtoresume.

AfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

Whenthedeviceexecutesthe"HALT"instruction,thePDFflagwillbesetto1.ThePDFflagwillbeclearedto0ifthedeviceexperiencesasystempower-uporexecutestheclearWatchdogTimerinstruction.IfthesystemiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiatedandtheTOflagwillbesetto1.TheTOflagissetifaWDTtime-outoccursandcausesawake-upthatonlyresetstheProgramCounterandStackPointer,otherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowakeupthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.Inthissituation,theinterruptwhichwokeupthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

Rev. 1.00 34 ea 01 Rev. 1.00 35 ea 01



Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalclock,fLIRC,whichissourcedfromtheLIRCoscillator.TheLIRCinternaloscillatorhasanapproximatefrequencyof32kHzandthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to218togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.

Watchdog Timer Control RegisterAsingleregister,WDTC,controlstherequiredtime-outperiodaswellastheenableandresetMCUoperation.

• WDTC Register

Bit 7 6 5 4 3 2 1 0Name WE4 WE3 WE WE1 WE0 WS WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit7~3 WE4~WE0:WDTfunctionsoftwarecontrol01010/10101:EnabledOthervalues:ResetMCU

When thesebitsarechanged toanyothervaluesdue toenvironmentalnoise themicrocontrollerwillbereset;thisresetoperationwillbeactivatedafteradelaytime,tSRESET,andtheWRFbitintheRSTFCregisterwillbesethigh.

Bit2~0 WS2~WS0:WDTtime-outperiodselection000:28/fLIRC001:210/fLIRC010:212/fLIRC011:214/fLIRC100:215/fLIRC101:216/fLIRC110:217/fLIRC111:218/fLIRC

These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.

• RSTFC Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — — WR

R/W — — — — — — — R/W

POR — — — — — — — 0

Bit7~1 Unimplemented,readas"0"Bit0 WRF:WDTcontrolregistersoftwareresetflag

0:Notoccurred1:Occurred

Thisbit isset to1by theWDTcontrol registersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.

Rev. 1.00 34 ea 01 Rev. 1.00 35 ea 01



Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.Therearefivebits,WE4~WE0,intheWDTCregistertooffertheenableandresetcontroloftheWatchdogTimer.TheWDTfunctionwillbeenabledwhentheWE4~WE0bitsaresettoavalueof01010Bor10101B.IftheWE4~WE0bitsaresettoanyothervaluesotherthan01010Band10101B,itwillresetthedeviceafteradelaytime,tSRESET.Afterpoweronthesebitswillhavethevalueof01010B.

WE4~WE0 Bits WDT Function01010B/10101B EnaleAn othe vales Reset MCU

Watchdog Timer Function Control

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101BwrittenintotheWE4~WE0bitfiled, thesecondisusingtheWatchdogTimersoftwareclear instructionsandthethirdisviaaHALTinstruction.

ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle"CLRWDT"instructiontocleartheWDT.

Themaximumtimeoutperiod iswhenthe218divisionratio isselected.Asanexample,witha32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8secondsforthe218divisionratio,andaminimumtimeoutof8msforthe28divisionration.

“CLR WDT”Instction

-stage Divide WDT Pescale

WE4~WE0 itsWDTC Registe Reset MCU

fLIRC fLIRC/

-to-1 MUX

CLR

WS~WS0 WDT Time-ot(/fLIRC ~ 1/fLIRC)

“HALT”Instction

LIRC

Watchdog Timer

Rev. 1.00 36 ea 01 Rev. 1.00 37 ea 01



Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawell-definedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

AtypeofresetiswhentheWatchdogTimeroverflowsandresetsthemicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.

Reset FunctionsTherearethreewaysinwhichamicrocontrollerresetcanoccur,througheventsoccurringinternally.

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

VDD

Powe-on Reset

SST Time-ot

tRSTD

Power-On Reset Timing Chart

Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperationsintheFASTorSLOWmodeisthesameasaPowerOnresetexceptthattheWatchdogtime-outflagTOwillbesetto"1".

WDT Time-ot

Intenal Reset

tRSTD + tSST

WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto"0"andtheTOflagwillbesetto"1".RefertotheSystemStartUpTimeCharacteristicsfortSSTdetails.

WDT Time-ot

Intenal ResettSST

WDT Time-out Reset during SLEEP or IDLE Timing Chart

Rev. 1.00 36 ea 01 Rev. 1.00 37 ea 01



Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF Reset Conditions0 0 Powe-on eset1 WDT time-ot eset ding AST o SLOW Mode opeation1 1 WDT time-ot eset ding IDLE o SLEEP Mode opeation

Note:"u"standsforunchanged

Thefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition after ResetPogam Conte Reset to zeoIntepts All intepts will e disaledWDT Time Base Clea afte eset WDT egins contingTime/Event Conte Time/Event Conte will e tned offInpt/Otpt Pots I/O pots will e setp as inptsStack Pointe Stack Pointe will point to the top of the stack

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.

Register Name Power On Reset WDT Time-out(Normal Operation)

WDT Time-out(IDLE/SLEEP)

IAR0 x x x x x x x x x x x x x x x x MP0 x x x x x x x x x x x x x x x x IAR1 x x x x x x x x x x x x x x x x MP1 x x x x x x x x x x x x x x x x ACC x x x x x x x x PCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x TBLH x x x x x x x x TBHP - - - - - x x x - - - - - - - - - - STATUS - - 0 0 x x x x - - 1 - - 1 1 SCC 0 0 0 - - - 0 0 0 0 0 - - - 0 0 - - - HIRCC - - - - - - 0 1 - - - - - - 0 1 - - - - - - INTEG - - - - - - 0 0 - - - - - - 0 0 - - - - - - INTC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - RSTC - - - - - - - 0 - - - - - - - - - - - - - - INTC1 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - - - PA - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - PAC - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - PAPU - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - PAWU - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 TBC 0 - - - - 0 0 0 0 - - - - 0 0 0 - - - -

Rev. 1.00 3 ea 01 Rev. 1.00 39 ea 01



Register Name Power On Reset WDT Time-out(Normal Operation)

WDT Time-out(IDLE/SLEEP)

PSCR - - - - - - 0 0 - - - - - - 0 0 - - - - - - PAS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAS1 - - - - - - 0 0 - - - - - - 0 0 - - - - - - HVOC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - HVOC1 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 - - DIVOC - - - - - - - 0 - - - - - - - 0 - - - - - - - PWMC 0 0 0 - - - 0 0 0 0 0 - - - 0 0 - - - PWM0DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM1DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMRC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - - TMR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVPC0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 - OVPC1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 OVPDAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVPDAH - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - TKTMR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TKC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - TK16DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TK16DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TKC1 - - - - - - 1 1 - - - - - - 1 1 - - - - - - TKM16DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TKM16DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TKMROL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TKMROH - - - - - - 0 0 - - - - - - 0 0 - - - - - - TKMC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TKMC1 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 -

Note:"u"standsforunchanged"x"standsforunknown"-"standsforunimplemented

Rev. 1.00 3 ea 01 Rev. 1.00 39 ea 01



Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedeviceprovidesbidirectional input/output lines labeledwithportnamePA.TheseI/Oportsaremappedto theRAMDataMemorywithspecificaddressesasshownin theSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction"MOVA,[m]",wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

Register Name

Bit7 6 5 4 3 2 1 0

PA — — — PA4 PA3 PA PA1 PA0PAC — — — PAC4 PAC3 PAC PAC1 PAC0

PAPU — — — PAPU4 PAPU3 PAPU PAPU1 PAPU0PAWU — — — PAWU4 PAWU3 PAWU PAWU1 PAWU0

"—": Unimplemented ead as “0”I/O Logic Function Register List

Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasan inputhave thecapabilityofbeingconnected toan internalpull-highresistor.Thesepull-highresistorsareselectedusingtherelevantpull-highcontrolregistersPAPU,andareimplementedusingweakPMOStransistors.

Notethat thepull-highresistorcanbecontrolledbytherelevantpull-highcontrolregistersonlywhenthepin-sharedfunctionalpinisselectedasainputorNMOSoutput.Otherwise,thepull-highresistorscannotbeenabled.

• PAPU Register

Bit 7 6 5 4 3 2 1 0Name — — — PAPU4 PAPU3 PAPU PAPU1 PAPU0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas"0"Bit4~0 PAPU4~PAPU0:PortAbit4~bit0Pull-highControl

0:Disable1:Enable

Rev. 1.00 40 ea 01 Rev. 1.00 41 ea 01



Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

Notethat thewake-upfunctioncanbecontrolledbythewake-upcontrolregistersonlywhenthepin-sharedfunctionalpinisselectedasgeneralpurposeinput/outputandtheMCUentersthePowerdownmode.

• PAWU Register

Bit 7 6 5 4 3 2 1 0

Name — — — PAWU4 PAWU3 PAWU PAWU1 PAWU0

R/W — — — R/W R/W R/W R/W R/W

POR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas"0"Bit4~0 PAWU4~PAWU0:PortAbit4~bit0Wake-upControl

0:Disable1:Enable

I/O Port Control RegistersEachI/OporthasitsowncontrolregisterknownasPAC,tocontroltheinput/outputconfiguration.With thiscontrol register,eachCMOSoutputor inputcanbe reconfigureddynamicallyundersoftwarecontrol.EachpinoftheI/Oportsisdirectlymappedtoabitinitsassociatedportcontrolregister.FortheI/Opintofunctionasaninput, thecorrespondingbitofthecontrolregistermustbewrittenasa"1".Thiswill thenallowthe logicstateof the inputpin tobedirectly readbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa"0",theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

• PAC Register

Bit 7 6 5 4 3 2 1 0

Name — — — PAC4 PAC3 PAC PAC1 PAC0

R/W — — — R/W R/W R/W R/W R/W

POR — — — 1 1 1 1 1

Bit7~5 Unimplemented,readas"0"Bit4~0 PAC4~PAC0:PortAbit4~bit0Input/OutputControl

0:Output1:Input

Rev. 1.00 40 ea 01 Rev. 1.00 41 ea 01



Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forthesepins,thedesiredfunctionofthemulti-functionI/Opinsisselectedbyaseriesofregistersviatheapplicationprogramcontrol.

Pin-shared Function Selection RegistersThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.ThedeviceincludesPort"A"pinsharedfunctionselectionregisters, labeledasPASn,whichcanselectthedesiredfunctionsofthemulti-functionpin-sharedpins.

Themostimportantpoint tonoteis tomakesurethat thedesiredpin-sharedfunctionisproperlyselectedandalsodeselected.Formostpin-sharedfunctions,toselectthedesiredpin-sharedfunction,thepin-sharedfunctionshouldfirstbecorrectlyselectedusingthecorrespondingpin-sharedcontrolregister.Afterthatthecorrespondingperipheralfunctionalsettingshouldbeconfiguredandthentheperipheralfunctioncanbeenabled.However,aspecialpointmustbenotedforsomedigitalinputpins,suchasINT,OVPIandKEYnetc,whichsharethesamepin-sharedcontrolconfigurationwiththeircorrespondinggeneralpurposeI/Ofunctionswhensettingtherelevantpin-sharedcontrolbitfields.Toselectthesepinfunctions,inadditiontothenecessarypin-sharedcontrolandperipheralfunctionalsetupaforementioned,theymustalsobesetupasaninputbysettingthecorrespondingbitintheI/Oportcontrolregister.Tocorrectlydeselectthepin-sharedfunction,theperipheralfunctionshouldfirstbedisabledand then thecorrespondingpin-sharedfunctioncontrol registercanbemodifiedtoselectotherpin-sharedfunctions.

Register Name

Bit

7 6 5 4 3 2 1 0PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS0 PAS01 PAS00

PAS1 — — — — — — PAS11 PAS10

Pin-shared Function Selection Registers List

• PAS0 Register

Bit 7 6 5 4 3 2 1 0Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS0 PAS01 PAS00R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PAS07~PAS06:PA3Pin-sharedfunctionselection00:PA301:PA310:OVPI11:KEY4

Bit5~4 PAS05~PAS04:PA2Pin-sharedfunctionselection00:PA201:PA210:PA211:KEY2

Rev. 1.00 4 ea 01 Rev. 1.00 43 ea 01



Bit3~2 PAS03~PAS02:PA1Pin-sharedfunctionselection00:PA101:PA110:OVPI11:KEY3

Bit1~0 PAS01~PAS00:PA0Pin-sharedfunctionselection00:PA001:PA010:PA011:KEY1

• PAS1 Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — PAS11 PAS10R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 PAS11~PAS10:PA4Pin-Sharedfunctionselection

00:PA401:PA410:PA411:OVPI

I/O Pin StructuresTheaccompanyingdiagramillustratestheinternalstructureoftheI/Ologicfunction.Astheexactlogicalconstructionof theI/Opinwilldifferfromthisdrawing, it issuppliedasaguideonlytoassistwith thefunctionalunderstandingof theI/Ologicfunction.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

MUX

VDD

Contol Bit

Data Bit

Data Bs

Wite Contol Registe

Chip Reset

Read Contol Registe

Read Data Registe

Wite Data Registe

Sstem Wake-p wake-p Select

I/O pin

WeakPll-p

Pll-highRegisteSelect

Q

D

CK

Q

D

CK

Q

QS

S

Logic Function Input/Output Structure

Rev. 1.00 4 ea 01 Rev. 1.00 43 ea 01



Programming Considerations Withintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregister,PAC,arethenprogrammedtosetupsomepinsasoutputs, theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregister,PA,arefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbitsintheportcontrolregisterusingthe"SET[m].i"and"CLR[m].i"instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

Rev. 1.00 44 ea 01 Rev. 1.00 45 ea 01



Timer/Event CounterTheprovisionoftimersformanimportantpartofanymicrocontroller,givingthedesignerameansofcarryingouttimerelatedfunctions.Thedevicecontainsan8-bitTimer/EventCounter.Andtheprovisionofaninternalprescalertotheclockcircuitryongivesaddedrangetothetimer.

Thereare twotypesofregistersrelatedto theTimer/EventCounter.Thefirst is theregister thatcontainstheactualvalueofthetimerandintowhichaninitialvaluecanbepreloaded.ReadingfromthisregisterretrievesthecontentsoftheTimer/EventCounter.ThesecondtypeofassociatedregisteristheTimerControlRegisterwhichdefinesthetimeroptionsanddetermineshowthetimeristobeused.

-1 MUX

-stage ConteMUX

1

0fSYS

fSUB

TS

fTP

6

TPSC[:0]

Peload Registe

Up Conte

Data Bs

Reload

Oveflow to Intept

Time Pescale

Time Base Contol Time Base Intept Peiod

Timer/Event Counter Structure

Configuring the Timer/Event Counter Input Clock SourceTheTimer/EventCounterclocksourcecanoriginate fromeither fSYSor the fSUBoscillator, thechoiceofwhichisdeterminedbytheTSbitintheTMRCregister.Thisinternalclocksourceisfirstdividedbyaprescaler,thedivisionratioofwhichisconditionedbytheTimerControlRegisterbitsTPSC2~TPSC0.

Timer Register – TMRThetimerregisterTMRisaspecialfunctionregisterlocatedintheSpecialPurposeDataMemoryandistheplacewheretheactualtimervalueisstored.Thevalueinthetimerregisterincreasesbyoneeachtimeaninternalclockpulseisreceived.ThetimerwillcountfromtheinitialvalueloadedbythepreloadregistertothefullcountofFFHforthe8-bitTimer/EventCounter,atwhichpointthetimeroverflowsandaninternalinterruptsignalisgenerated.Thetimervaluewillthenresetwiththeinitialpreloadregistervalueandcontinuecounting.

NotethattoachieveamaximumfullrangecountofFFH,thepreloadregistermustfirstbeclearedtoallzeros.Note that if theTimer/EventCounter is inanOFFconditionanddata iswritten toitspreloadregister, thisdatawillbeimmediatelywrittenintotheactualcounter.However, if thecounter isenabledandcounting,anynewdatawritten into thepreloaddataregisterduring thisperiodwillremaininthepreloadregisterandwillonlybewrittenintotheactualcounterthenexttimeanoverflowoccurs.

Rev. 1.00 44 ea 01 Rev. 1.00 45 ea 01



Timer Control Register – TMRCItistheTimerControlRegistertogetherwithitscorrespondingtimerregisterthatcontrolsthefulloperationoftheTimer/EventCounter.Beforethetimercanbeused,it isessentialthattheTimerControlRegisterisfullyprogrammedwiththerightdatatoensureitscorrectoperation,aprocessthatisnormallycarriedoutduringprograminitialisation.

Thetimer-onbit,whichisbit4oftheTimerControlRegisterandknownasTONbit,providesthebasicon/offcontrolofthetimer.Settingthebithighallowsthecountertorun.Clearingthebitstopsthecounter.Bits0~2oftheTMRCRegisterdeterminethedivisionratiooftheinputclockprescaler.Inaddition,thebitTSisusedtoselecttheinternalclocksource.

• TMRC Register

Bit 7 6 5 4 3 2 1 0Name — — TS TON — TPSC TPSC1 TPSC0R/W — — R/W R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5 TS:Timer/EventCounterClockSource

0:fSYS

1:fSUB

Bit4 TON:Timer/EventCounterCountingEnable0:Disable1:Enable

Bit3 Unimplemented,readas"0"Bit2~0 TPSC2~TPSC0:Timerprescalerrateselection

Timerinternalclock=000:fTP001:fTP/2010:fTP/4011:fTP/8100:fTP/16101:fTP/32110:fTP/64111:fTP/128

Timer/Event Counter OperationTheTimer/EventCountercanbeutilised tomeasurefixed timeintervals,providingan internalinterruptsignaleachtimetheTimer/EventCounteroverflows.Theinternalclockisusedasthetimerclock.ThetimerinputclockiseitherfSYSorthefSUBoscillator.However,thistimerclocksourceisfurtherdividedbyaprescaler,thevalueofwhichisdeterminedbythebitsTPSC0~TPSC2intheTimerControlRegister.Thetimer-onbit,TONmustbesethightoenablethetimertorun.Eachtimewhenaninternalclockhightolowtransitionoccurs,thetimerwillreloadthevaluealreadyloadedinto thepreloadregisterandcontinuescounting.Atimeroverflowconditionandcorrespondinginternalinterruptisoneofthewake-upsources,however,theinternalinterruptscanbedisabledbyensuringthattheTEbitoftheINTC0registerareresettozero.

PrescalerBitsTPSC0~TPSC2of theTMRCregistercanbeusedtodefineadivisionratiofor theinternalclocksourceoftheTimer/EventCounterenablinglongertimeoutperiodstobesetup.

Rev. 1.00 46 ea 01 Rev. 1.00 47 ea 01



Programming ConsiderationWhentheTimer/EventCounter is read,or ifdata iswritten to thepreloadregister, theclock isinhibitedtoavoiderrors,howeverasthismayresultinacountingerror,thisshouldbetakenintoaccountbytheprogrammer.Caremustbetakentoensurethatthetimerisproperlyinitializedbeforeusingthemforthefirsttime.Theassociatedtimerenablebitsintheinterruptcontrolregistermustbeproperlysetotherwisetheinternalinterruptassociatedwiththetimerwillremaininactive.Theedgeselect,timermodeandclocksourcecontrolbitsintimercontrolregistermustalsobecorrectlysettoensurethetimerisproperlyconfiguredfortherequiredapplication.Itisalsoimportanttoensurethataninitialvalueisfirstloadedintothetimerregistersbeforethetimerisswitchedon;thisisbecauseafterpower-ontheinitialvaluesofthetimerregistersareunknown.

Afterthetimerhasbeeninitializedthetimercanbeturnedonandoffbycontrollingtheenablebitinthetimercontrolregister.WhentheTimer/EventCounteroverflows,itscorrespondinginterruptrequest flag in the interruptcontrol registerwillbeset. If theTimer/EventCounter interrupt isenabledthiswillinturngenerateaninterruptsignal.Howeverirrespectiveofwhethertheinterruptsareenabledornot,aTimer/EventCounteroverflowwillalsogenerateawake-upsignalifthedeviceisinaPower-downcondition.Thissituationmayoccurif theTimer/EventCounter is in theEventCountingModeandiftheexternalsignalcontinuestochangestate.Insuchacase,theTimer/EventCounterwillcontinuetocounttheseexternaleventsand ifanoverflowoccursthedevicewillbewokenupfromitsPower-downcondition.Topreventsuchawake-upfromoccurring, the timerinterruptrequestflagshouldfirstbesethighbeforeissuingthe"HALT"instructiontoentertheIdle/SleepMode.

Rev. 1.00 46 ea 01 Rev. 1.00 47 ea 01



Touch Key FunctionThedeviceprovides4touchkeyfunctions.Thetouchkeyfunctionisfullyintegratedandrequiresnoexternalcomponents,allowingtouchkeyfunctionstobeimplementedbythesimplemanipulationofinternalregisters.

Touch Key StructureThetouchkeysarepinsharedwiththeI/Opins,withthedesiredfunctionchosenviathepin-sharedselectionregisterbit.Keysareorganisedintoonegroup,knownasamodule.ThemoduleisafullyindependentsetoffourTouchKeysandhasitsownoscillator.Themodulecontainsitsowncontrollogiccircuitsandregisterset.

Total Key Number Touch Key Shared I/O Pin

4 KEY1~KEY4 PA0 PA PA1 PA3

Touch Key Structure

16-it ConteMUX

-it Time Slot Conte Peload Registe

33MHzAnalog ilte

MUX

KeOSCKEY4

KeOSCKEY3

KeOSCKEY

KEY1 KeOSC

-it Time Slot Conte TKRCOV

Mlti-feqenc 16-it C/ Conte

MDEN

TKCOV

TK16DH / TK16DL

TKTMR

Refeence Oscillato

fSYS/4 MUX

MTSS

MMXS1 ~ MMXS0

5-it Unit Peiod Conte

TKTMR Oveflow

TK16OV

TK16S1~TK16S0

MILEN

fCTMCK

33MHzAnalog ilte

MILENTKMROH / TKMROL

fSYS/4fSYS/

fSYS

fSYS/

Note:1.Thestructurecontainedinthedashlineisforthetouchkeymodulewhichcontainsfourtouchkeys.2.WhenMTSS=0andMROEN=1orwhenMTSS=1, thetouchkeyfunction16-bitcountercanoperate

normally.Touch Key Function Block Diagram

Rev. 1.00 4 ea 01 Rev. 1.00 49 ea 01



Touch Key Registers DescriptionThetouchkeymodule,whichcontainsfour touchkeyfunctions,has itsownsuiteregisters.Thefollowingtableshowstheregistersetforthetouchkeymodule.

Register Name DescriptionTKTMR Toch ke time slot -it conte peload egisteTKC0 Toch ke fnction contol egiste 0TKC1 Toch ke fnction contol egiste 1

TK16DL Toch ke fnction 16-it conte low teTK16DH Toch ke fnction 16-it conte high te

TKM16DL Toch ke modle 16-it C/ conte low teTKM16DH Toch ke modle 16-it C/ conte high teTKMROL Toch ke modle efeence oscillato capacito select low teTKMROH Toch ke modle efeence oscillato capacito select high teTKMC0 Toch ke modle contol egiste 0TKMC1 Toch ke modle contol egiste 1

Touch Key Function Register Definition

Register Name

Bit7 6 5 4 3 2 1 0

TKTMR D7 D6 D5 D4 D3 D D1 D0TKC0 — TKRCOV TKST TKCOV TK16OV — TK16S1 TK16S0TKC1 — — — — — — TKS1 TKS0

TK16DL D7 D6 D5 D4 D3 D D1 D0TK16DH D15 D14 D13 D1 D11 D10 D9 D

TKM16DL D7 D6 D5 D4 D3 D D1 D0TKM16DH D15 D14 D13 D1 D11 D10 D9 DTKMROL D7 D6 D5 D4 D3 D D1 D0TKMROH — — — — — — D9 DTKMC0 MMXS1 MMXS0 MDEN MILEN MSOC MSO MSO1 MSO0TKMC1 MTSS — MROEN MKOEN MK4EN MK3EN MKEN MK1EN

Touch Key Function Register List

• TKTMR Register

Bit 7 6 5 4 3 2 1 0Name D7 D6 D5 D4 D3 D D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 D7~D0:Touchkeytimeslot8-bitcounterpreloadregisterThetouchkeytimeslotcounterpreloadregisterisusedtodeterminethetouchkeytimeslotoverflowtime.Thetimeslotunitperiodisobtainedbya5-bitcounterandequalto32timeslotclockcycles.Therefore, thetimeslotcounteroverflowtimeisequaltothefollowingequationshown.Timeslotcounteroverflowtime=(256-TKTMR[7:0])×32tTSC,wherethetTSCisthetimeslotcounterclockperiod.

Rev. 1.00 4 ea 01 Rev. 1.00 49 ea 01



• TKC0 Register

Bit 7 6 5 4 3 2 1 0Name — TKRCOV TKST TKCOV TK16OV — TK16S1 TK16S0R/W — R/W R/W R/W R/W — R/W R/WPOR — 0 0 0 0 — 0 0

Bit7 Unimplemented,readas"0"Bit6 TKRCOV:Touchkeytimeslotcounteroverflowflag

0:Nooverflowoccurs1:Overflowoccurs

Thisbitcanbeaccessedbyapplicationprogram.Whenthisbit issetbytouchkeytimeslotcounteroverflow,thecorrespondingtouchkeyinterruptrequestflagwillbeset.However,ifthisbitissetbyapplicationprogram,thetouchkeyinterruptrequestflagwillnotbeaffected.Therefore,thisbitcannotbesetbyapplicationprogrambutmustbeclearedto0byapplicationprogram.If the timeslotcounteroverflows, theTKRCOVbitand theTouchKeyInterruptrequest flag,TKMF,willbesetandallmodulekeysandreferenceoscillatorswillautomaticallystop.The touchkeymodule16-bitC/Fcounter, touchkeyfunction16-bitcounter,5-bit timeslotunitperiodcounterand8-bit timeslotcounterwillbeautomaticallyswitchedoff.

Bit5 TKST:Touchkeydetectionstartcontrol0:Stoppedornooperation0→1:Startdetection

Thetouchkeymodule16-bitC/Fcounter,touchkeyfunction16-bitcounterand5-bittimeslotunitperiodcounterwillautomaticallybeclearedwhenthisbitisclearedtozero.However, the8-bitprogrammabletimeslotcounterwillnotbecleared.Whenthisbitischangedfromlowtohigh,thetouchkeymodule16-bitC/Fcounter,touchkeyfunction16-bitcounter,5-bit timeslotunitperiodcounterand8-bit timeslotcounterwillbeswitchedontogetherwiththekeyandreferenceoscillatorstodrivethecorrespondingcounters.

Bit4 TKCFOV:Touchkeymodule16-bitC/Fcounteroverflowflag0:Nooverflowoccurs1:Overflowoccurs

Thisbitissetbytouchkeymodule16-bitC/Fcounteroverflowandmustbeclearedto0byapplicationprogram.

Bit3 TK16OV:Touchkeyfunction16-bitcounteroverflowflag0:Nooverflowoccurs1:Overflowoccurs

Thisbitissetbytouchkeyfunction16-bitcounteroverflowandmustbeclearedto0byapplicationprogram.

Bit2 Unimplemented,readas"0"Bit1~0 TK16S1~TK16S0:Touchkeyfunction16-bitcounterclocksourceselection

00:fSYS

01:fSYS/210:fSYS/411:fSYS/8

• TKC1 Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — TKS1 TKS0R/W — — — — — — R/W R/WPOR — — — — — — 1 1

Bit7~2 Unimplemented,readas"0"

Rev. 1.00 50 ea 01 Rev. 1.00 51 ea 01



Bit1~0 TKFS1~TKFS0:TouchkeyoscillatorandReferenceoscillatorfrequencyselection00:1MHz01:3MHz10:7MHz11:11MHz

• TK16DL Register

Bit 7 6 5 4 3 2 1 0Name D7 D6 D5 D4 D3 D D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 D7~D0:Touchkeyfunction16-bitcounterlowbytecontents

• TK16DH Register

Bit 7 6 5 4 3 2 1 0Name D15 D14 D13 D1 D11 D10 D9 DR/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 D15~D8:Touchkeyfunction16-bitcounterhighbytecontentsThisregisterpairisusedtostorethetouchkeyfunction16-bitcountervalue.This16-bitcountercanbeusedtocalibratethereferenceorkeyoscillatorfrequency.Whenthetouchkeytimeslotcounteroverflows,this16-bitcounterwillbestoppedandthecountercontentwillbeunchanged.ThisregisterpairwillbeclearedtozerowhentheTKSTbitiscleared.

• TKM16DL Register

Bit 7 6 5 4 3 2 1 0Name D7 D6 D5 D4 D3 D D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 D7~D0:Touchkeymodule16-bitC/Fcounterlowbytecontents

• TKM16DH Register

Bit 7 6 5 4 3 2 1 0Name D15 D14 D13 D1 D11 D10 D9 DR/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 D15~D8:Touchkeymodule16-bitC/FcounterhighbytecontentsThisregisterpairisusedtostorethetouchkeymodule16-bitC/Fcountervalue.This16-bitC/Fcounterwillbestoppedandthecountercontentwillbekeptunchangedwhenthetouchkeytimeslotcounteroverflows.ThisregisterpairwillbeclearedtozerowhentheTKSTbitissetlow.

• TKMROL Register


Bit7~0 D7~D0:Touchkeymodulereferenceoscillatorinternalcapacitorselection

Rev. 1.00 50 ea 01 Rev. 1.00 51 ea 01



• TKMROH Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — D9 DR/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 D9~D8:Touchkeymodulereferenceoscillatorinternalcapacitorselection

Thisregisterpairisusedtostorethetouchkeymodulereferenceoscillatorcapacitorvalue.Thereferenceoscillatorinternalcapacitorvalue=(TKMRO[9:0]×50pF)/1024

• TKMC0 Register

Bit 7 6 5 4 3 2 1 0Name MMXS1 MMXS0 MDEN MILEN MSOC MSO MSO1 MSO0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 MMXS1~ MMXS0:Touchkeymodulemultiplexerkeyselection00:KEY101:KEY210:KEY311:KEY4

Bit5 MDFEN:Touchkeymodulemulti-frequencycontrol0:Disable1:Enable

Thisbitisusedtocontrolthetouchkeyoscillatorfrequencydoublingfunction.Whenthisbitissetto1,thekeyoscillatorfrequencywillbedoubled.

Bit4 MFILEN:Touchkeymodulefilterfunctioncontrol0:Disable1:Enable

Bit3 MSOFC:TouchkeymoduleC-to-Foscillatorfrequencyhoppingfunctioncontrolselection0:ControlledbytheMSOF2~MSOF01:Controlledbyhardwarecircuit

Thisbitisusedtoselectthetouchkeyoscillatorfrequencyhoppingfunctioncontrolmethod.Whenthisbit isset to1, thekeyoscillatorfrequencyhoppingfunction iscontrolledbythehardwarecircuitregardlessoftheMSOF2~MSOF0bitsvalue.

Bit2~0 MSOF2~MSOF0:TouchkeymoduleReferenceandKeyoscillatorshoppingfrequencyselection000:1.020MHz001:1.040MHz010:1.059MHz011:1.074MHz100:1.085MHz101:1.099MHz110:1.111MHz111:1.125MHz

Thesebitsareused to select the touchkeyoscillator frequency for thehoppingfunction.NotethatthesebitsareonlyavailablewhentheMSOFCbitisclearedto0.Thefrequencymentionedherewillbechangedwhentheexternalorinternalcapacitoriswithdifferentvalues.Ifthetouchkeyoperatesat1MHzfrequency,userscanadjustthefrequencyinscalewhenanyotherfrequencyisselected.

Rev. 1.00 5 ea 01 Rev. 1.00 53 ea 01



• TKMC1 Register

Bit 7 6 5 4 3 2 1 0Name MTSS — MROEN MKOEN MK4EN MK3EN MKEN MK1ENR/W R/W — R/W R/W R/W R/W R/W R/WPOR 0 — 0 0 0 0 0 0

Bit7 MTSS:Touchkeymoduletimeslotcounterclocksourceselection0:Touchkeymodulereferenceoscillator1:fSYS/4

Bit6 Unimplemented,readas"0"Bit5 MROEN:TouchkeymoduleReferenceoscillatorenablecontrol

0:Disable1:Enable

Thisbitisusedtoenablethetouchkeymodulereferenceoscillator.ThereferenceoscillatorshouldfirstbeenabledbeforesettingtheTKSTbitfromlowtohighifthereferenceoscillatorisselectedtobeused.

Bit4 MKOEN:TouchkeymoduleKeyoscillatorenablecontrol0:Disable1:Enable

Thisbitisusedtoenablethetouchkeymodulekeyoscillator.ThekeyoscillatorshouldfirstbeenabledbeforesettingtheTKSTbitfromlowtohighiftherelevantkeyisenabledtobescanned.

Bit3 MK4EN:TouchkeymoduleKEY4enablecontrol0:Disable1:Enable




Touch Key OperationWhenafingertouchesorisinproximitytoatouchpad,thecapacitanceofthepadwill increase.Byusingthiscapacitancevariationtochangeslightlythefrequencyoftheinternalsenseoscillator,touchactionscanbesensedbymeasuringthesefrequencychanges.Usinganinternalprogrammabledivider the referenceclock isused togeneratea fixed timeperiod.Bycountinganumberofgeneratedclockcyclesfromthesenseoscillatorduringthisfixedtimeperiodtouchkeyactionscanbedetermined.

Rev. 1.00 5 ea 01 Rev. 1.00 53 ea 01



TKST

MKOENMROEN

KEY OSC CLK

Refeence OSC CLK

fCTMCK Enale

fCTMCK (MDEN=0)

fCTMCK (MDEN=1)

TKRCOV

Cleaed hadwae

Set Toch Ke TKRCOV intept eqest flag

Touch Key Module Timing Diagram

Thetouchkeymodulecontainsfourtouchkeyinputs,namelyKEY1~KEY4,whicharesharedwithlogicalI/Opins,andthedesiredfunctionisselectedusingregisterbits.Thetouchkeyhasitsownindependentsenseoscillator.Therearethereforefoursenseoscillatorswithinthetouchkeymodule.

During this referenceclock fixed interval, thenumberofclockcyclesgeneratedby thesenseoscillatorismeasured,anditisthisvaluethatisusedtodetermineifatouchactionhasbeenmadeornot.AttheendofthefixedreferenceclocktimeintervalaTouchKeyinterruptsignalwillbegenerated.

The touchkeymodule16-bitC/Fcounter,16-bitcounter,5-bit timeslotunitperiodcounter inthemodulewillbeautomaticallyclearedwhen theTKSTbit iscleared tozero,but the8-Bitprogrammabletimeslotcounterwillnotbecleared.Theoverflowtimeissetupbyuser.WhentheTKSTbitchangesfromlowtohigh,the16-bitC/Fcounter,16-bitcounter,5-bittimeslotunitperiodcounterand8-bittimeslottimercounterwillbeautomaticallyswitchedon.

Thekeyoscillatorandreferenceoscillatorinthemodulewillbeautomaticallystoppedandthe16-bitC/Fcounter,16-bitcounter,5-bittimeslotunitperiodcounterand8-bittimeslottimercounterwillbeautomaticallyswitchedoffwhenthetimeslotcounteroverflows.TheclocksourceforthetimeslotcounterissourcedfromthereferenceoscillatororfSYS/4whichisselectedusingtheMTSSbitintheTKMC1register.ThereferenceoscillatorandkeyoscillatorwillbeenabledbysettingtheMROENbitandMKOENbitsintheTKMC1register.

Whenthetimeslotcounterinthetouchkeymoduleoverflows,anactualtouchkeyinterruptwilltakeplace.Thetouchkeysmentionedherearethekeyswhichareenabled.

Rev. 1.00 54 ea 01 Rev. 1.00 55 ea 01



Touch Key Scan Operation Flowchart

Stat

Wite Ref. OSC Capacito to TKMROH/TKMROL

Touch Key Scan Operation StartSet Stat it TKST 0 1

All Time SlotConte oveflow ?

TKRCOV=0

Initiate Time Slot &16-it C/ Conte

All Time Slot &16-it C/ Conte

stat to cont

Time Slot &16-it C/ Conte

keep conting

TKRCOV=1

Geneate Intept eqest flag

Read C/ conte fom TKM16DH/TKM16DL

Toch ke scan endSet TKST it 1 0

End

Touch Key Scan Operation Flowchart

Rev. 1.00 54 ea 01 Rev. 1.00 55 ea 01



Touch Key InterruptThetouchkeyonlyhassingleinterrupt,whenthetouchkeymoduletimeslotcounteroverflows,anactualtouchkeyinterruptwilltakeplace.Thetouchkeysmentionedherearethekeyswhichareenabled.The16-bitC/Fcounter,16-bitcounter,5-bit timeslotunitperiodcounterand8-bit timeslotcounterinthemodulewillbeautomaticallycleared.

TheTKCFOVflagwhichisthe16-bitC/FcounteroverflowflagwillgohighwhentheTouchKeyModule16-bitC/Fcounteroverflows.Asthisflagwillnotbeautomaticallycleared, ithas tobeclearedbytheapplicationprogram.

TheTK16OVflagwhichisthe16-bitcounteroverflowflagwillgohighwhenthe16-bitcounteroverflows.Asthisflagwillnotbeautomaticallycleared, ithas tobeclearedbytheapplicationprogram.Moredetailsregardingthetouchkeyinterruptsarelocatedintheinterruptsectionofthedatasheet.

Progrsmming ConsiderationsAftertherelevantregistersaresetup,thetouchkeydetectionprocessisinitiatedthechangingtheTKSTBitfromlowtohigh.Thiswillenableandsynchroniseallrelevantoscillators.TheTKRCOVflagwhichisthetimeslotcounterflagwillgohighwhenthecounteroverflows.Whenthishappensaninterruptsignalwillbegenerated.

When theexternal touchkeysizeand layoutaredefined, their relatedcapacitanceswill thendeterminethesensoroscillatorfrequency.

Rev. 1.00 56 ea 01 Rev. 1.00 57 ea 01



High Voltage Driver OutputThedevicecontainsahighvoltagedrivercircuit,whichhas twogroupsofhighvoltageoutput.Eachgroupismainlycomposedofamistake-proofingcircuitandlevelshiftcircuit.Withthetwointegrated12Vhighvoltageprocesslevelshiftcircuits,thehighvoltagedriverprovidestwooutputpins,HVO0~HVO1,whichcanbeusedfordrivingLEDsusingbyPMOS.

HVO0LevelShift

GLTn

GLBn

Mistake-Poofing

CKT

OUTnMGTn

MGBn

VCCVDD

VCC

GBn

NMOSnEN

GTnUNCnData

HVO Contol

CKT

HVOnOEN

GB0n

VSS

HVO1

Note:1.n=0or1.2.TheFUNC0DataissourcedfromPWM0/PWM1/HVO0pin,whiletheFUNC1Dataissourced

fromPWM1/PWM0/HVO1pin,andactedasthecontrolsignaloutputHigh/Lowdatasource.

3.ItisrecommendedtocleartheNMOSnENbittozerowhendrivingLEDs.High Voltage Driver Output Block Diagram

High Voltage Driver Output RegistersTheoveralloperationofthehighvoltagedriveroutputiscontrolledusingtheHVOCregisterandHVOC1register.TheHVOCregistercontrolsthehighvoltagedriveroutputenable/disableoperation.TheHVOC1registerisusedtoselecttheHVOnpinsourceandhighvoltagedriveroutputdata.

• HVOC Register

Bit 7 6 5 4 3 2 1 0Name — — — — NMOS1EN HVO1OEN NMOS0EN HVO0OENR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3 NMOS1EN:NMOS1outputenablecontrol

0:NMOS1isalwaysdisabled1:NMOS1iscontrolledbyGB01signal

Note:When thePWM0orPWM1pin isselectedfor thehighvoltageoutput, theNMOS1ENbitshouldbeclearedtozero.

Bit2 HVO1OEN:Highvoltagedriveroutput1enablecontrol0:Disable1:Enable

WhentheHVO1OENbitisclearedtozero,theHVO1pinwillbeinafloatingstatus.Bit1 NMOS0EN:NMOS0outputenablecontrol

0:NMOS0isalwaysdisabled1:NMOS0iscontrolledbyGB00signal

Note:When thePWM0orPWM1pin is selectedas thehighvoltageoutput, theNMOS0ENbitshouldbeclearedtozero.

Bit0 HVO0OEN:Highvoltagedriveroutput0enablecontrol0:Disable1:Enable

WhentheHVO0OENbitisclearedtozero,theHVO0pinwillbeinafloatingstatus.

Rev. 1.00 56 ea 01 Rev. 1.00 57 ea 01



• HVOC1 Register

Bit 7 6 5 4 3 2 1 0

Name HVO1S1 HVO1S0 HVO0S1 HVO0S0 — — HVOD1 HVOD0

R/W R/W R/W R/W R/W — — R/W R/W

POR 0 0 0 0 — — 0 0

Bit7~6 HVO1S1~HVO1S0:Highvoltagedriveroutput1selection00:HVO101:HVO110:PWM011:PWM1


Bit3~2 Unimplemented,readas"0"Bit1 HVOD1:Highvoltagedriveroutput1data

1:HVO1=VCC0:HVO1=VSS

Bit0 HVOD0:Highvoltagedriveroutput0data1:HVO0=VCC0:HVO0=VSS

Rev. 1.00 5 ea 01 Rev. 1.00 59 ea 01



Functional DescriptionTheHighvoltagedriveroutputontheHVOnpinsareusedtodrivetheexternalpowerMOSbytheHVOnOENbitorusingFUNCnDataoutputtocontrolpowerMOSloads.

Mistake-Proofing Circuit for High Voltage DriverIncorrectwriteoperationsorexternal factorssuchanESDcondition,maycause incorrecton/off control resulting in the topandbottomsidesof external transistorbeingboth turnedonsimultaneously.Amistake-proofcircuitisprovidedtoavoidsuchsituation.

Mistake-Poofing

CKT

GTn

GBn

MGTn

MGBn

GTn GBn MGTn MGBn HVOn0 0 0 0 VCC0 1 1 1 VSS1 0 1 0 loating1 1 1 1 VSS

Note:0:MOSoff;1:MOSon.

High Voltage Driver Output Control Circuit

GBn

NMOSnEN

GTnUNCnData

HVO Contol

CKT

HVOnOEN

GB0n

HVOnOEN HVO Function data NMOSnEN GTn GBn HVOn1 0 1 1 1 VSS1 1 1 0 0 VCC1 0 0 1 0 loating1 1 0 0 0 VCC0 x x 1 0 loating

"x ": Don’t cae

Rev. 1.00 5 ea 01 Rev. 1.00 59 ea 01



Pulse Width ModulatorThedevicecontainstwo8-bitpulsewidthmodulationfunctions.Usefulfortheapplicationssuchasmotorspeedcontrol,thePWMfunctionprovidestwooutputswithafixedfrequencybutwithadutycyclethatcanbevariedbysettingparticularvaluesintothecorrespondingPWMnDATAregister.

PWMnPWMnSEL-it PWM Compaato

(7+1)/(6+)

PWMnDATA

fSYS PescaleDivide(/1 / /3 /4)

PWMDIV[1:0]

PWMEN

fDIV

PSC[7:0]

PWM Block Diagram

PWM Registers DescriptionThetworegisterscontrol theoveralloperationof thePulseWidthModulator.Thesearethedataregister,PWMnDATAandacontrolregister,PWMC.ThefrequencyofthePWMcounterissourcedfromtheprescaleroutputsignal.

• PWMC Register

Bit 7 6 5 4 3 2 1 0Name PWMEN PWMDIV1 PWMDIV0 — — — PWM1SEL PWM0SELR/W R/W R/W R/W — — — R/W R/WPOR 0 0 0 — — — 0 0

Bit7 PWMEN:PWMenablecontrol0:Disable1:Enable

Bit6~5 PWMDIV1 ~ PWMDIV0:fDIVFrequencyselection00:fDIV=fSYS

01:fDIV=fSYS/210:fDIV=fSYS/311:fDIV=fSYS/4

Bit4~2 Unimplemented,readas"0"Bit1 PWM1SEL:PWM1typeselection

0:(6+2)mode1:(7+1)mode

Bit0 PWM0SEL:PWM0typeselection0:(6+2)mode1:(7+1)mode

Rev. 1.00 60 ea 01 Rev. 1.00 61 ea 01



• PWMnDATA Register (n= 0 or 1)


Bit7~0 D7~D0:PWMdatabits

PWM OperationThePWMCregisterandPWMnDATAregisterareassignedtoeachPulseWidthModulatorchannel.ThePWMnDATAregisterrepresent theoveralldutycycleofonemodulationcycleof theoutputwaveform,shouldbeplaced.ToincreasethePWMmodulationfrequency,eachmodulationcycleissubdividedintotwoorfourindividualmodulationsubsections,knownasthe7+1modeor6+2moderespectively.Therequiredmodeandtheenable/disablecontrolforeachPWMchannel isselectedusingthePWMCregister.NotethatwhenusingthePWM,itisonlynecessarytowritetherequiredvalueintothePWMnDATAregisterandselecttherequiredmodesetupandenable/disablecontrolusingthePWMCregister,thesubdivisionofthewaveformintoitssub-modulationcyclesis implementedautomaticallywithinthemicrocontrollerhardware.ThePWMclocksourceis thesystemclockfSYS.

Thismethodofdividingtheoriginalmodulationcycleintoafurther2or4sub-cyclesenablethegenerationofhigherPWMfrequencieswhichallowawiderrangeofapplicationstobeserved.ThedifferencebetweenwhatisknownasthePWMcyclefrequencyandthePWMmodulationfrequencyshouldbeunderstood.AsthePWMclockisthesystemclock,fSYS,andasthePWMvalueis8-bitswide,theoverallPWMcyclefrequencyisfSYS/256.However,wheninthe7+1modeofoperationthePWMmodulationfrequencywillbefSYS/128,whilethePWMmodulationfrequencyforthe6+2modeofoperationwillbefSYS/64.

Themodulation frequency, cycle frequency and cycle dutyof thePWMoutput signal aresummarizedinthefollowingtable.

PWM Modulation Frequency PWM Cycle Frequency PWM Cycle Duty

fDIV/64 fo (6+) its modefDIV/56 (PWMnDATA egiste vale)/56

fDIV/1 fo (7+1) its mode

(6+2) Bits PWM Mode ModulationA(6+2)bitsmodePWMcycle isdivided into fourmodulationcycles,whicharenamedasModulationcycle0~Modulationcycle3.Eachmodulationcyclehas64PWMinputclockperiod.Ina(6+2)bitsPWMmode,thecontentsofthePWMregisterisdividedintotwogroups.Group1ofthePWMregisterisdenotedbyDCwhichisthevalueofD7~D2bitsinthePWMnDATAregister.Thegroup2isdenotedbyACwhichis thevalueofD1~D0bits inthePWMnDATAregister.Ina(6+2)bitsmodePWMcycle,thedutycycleofeachmodulationcycleisshowninthefollowingtable.

Parameter AC (0~3) Duty Cycle

Modlation ccle i(i=0~3)

i<AC (DC+1)/64i≥AC DC/64

6+2 Mode Modulation Cycle Values

Thefollowingdiagramillustrates thewaveformsassociatedwith the(6+2)bitsmodeofPWMoperation. It is important tonotehow the singlePWMcycle is subdivided into4 individualmodulationcycles,numberedfrom0~3andhowtheACvalueisrelatedtothePWMvalue.ThewaveformsofPWMoutputsareasshown.

Rev. 1.00 60 ea 01 Rev. 1.00 61 ea 01



f

PWM

[PWM] =100

[PWM] =101

PWM

[PWM] =10

PWM

[PWM] =103

PWM

PWM ccle : 56/f

PWM modlation peiod : 64/fDIV

5/64

6/64

6/64

6/64

5/64 5/64 5/64

5/64

5/64

5/64

5/64

6/64

6/64

5/64

5/64

6/64 5/64

6/64

6/64

6/64

Modlation ccle=0 Modlation ccle=1 Modlation ccle= Modlation ccle=3 Modlation ccle=0

DIV

DIV

(6+2) Bits PWM Mode Modulation Waveform

(7+1) Bits PWM Mode ModulationA(7+1)bitsmodePWMcycleisdividedintotwomodulationcycles,whichisnamedasModulationcycle0~Modulationcycle1.Eachmodulationcyclehas128PWMinputclockperiod.Ina(7+1)bitsPWMmode,thecontentsofthePWMregisterisdividedintotwogroups.Group1ofthePWMregisterisdenotedbyDCwhichisthevalueofD7~D1bitsinthePWMnDATAregister.Thegroup2isdenotedbyACwhichisthevalueofD0bitinthePWMnDATAregister.Ina(7+1)bitsmodePWMcycle,thedutycycleofeachmodulationcycleisshowninthefollowingtable.

Parameter AC (0~1) Duty Cycle

Modlation ccle i(i=0~1)

i<AC (DC+1)/1i≥AC DC/1

(7+1) Bits Mode Modulation Cycle Values

Thefollowingdiagramillustrates thewaveformsassociatedwith the(7+1)bitsmodeofPWMoperation. It is important tonotehow the singlePWMcycle is subdivided into2 individualmodulationcycles,numberedfrom0~1andhowtheACvalueisrelatedtothePWMvalue.ThewaveformsofPWMoutputsareasshown.

f

PWM

[PWM] =100

[PWM] =101

PWM

[PWM] =10

PWM

[PWM] =103

PWM

PWM modlation peiod : 1/f

50/1

51/1

51/1

5/1

50/1

50/1

51/1

51/1

50/1

51/1

51/1

5/1

PWM ccle : 56/f

Modlation ccle 0 Modlation ccle 1 Modlation ccle0

DIV

DIV

DIV

(7+1) Bits PWM Mode Modulation Waveform

Rev. 1.00 6 ea 01 Rev. 1.00 63 ea 01



PWM Output ControlThePWMoutputsarepin-sharedwiththeHVOnpins.TooperateasaPWMoutputandnotasahighvoltageoutput,thecorrectbitsmustbesetintheHVOC1register.

• HVOC1 Register

Bit 7 6 5 4 3 2 1 0Name HVO1S1 HVO1S0 HVO0S1 HVO0S0 — — HVOD1 HVOD0R/W R/W R/W R/W R/W — — R/W R/WPOR 0 0 0 0 — — 0 0



Bit3~2 Unimplemented,readas"0"Bit1 HVOD1:Highvoltagedriveroutput1data

DescribedelsewhereBit0 HVOD0:Highvoltagedriveroutput0data

Describedelsewhere

Rev. 1.00 6 ea 01 Rev. 1.00 63 ea 01



Low Dropout Regulator – LDOThesystemissuppliedbyahighersystemvoltageapproximately6Vto12VontheinputpinVCC.

AninternalLDOreducesthishighervoltagetoa5VlevelwhichissuppliedontheoutputpinVDD.Thislowervoltagelevelisusedbytheinternallogiccircuitsbutasitcansupplyupto40mAitcanalsobeusedbyexternalcircuitry.

DPreference

Level shift

VCCVDD

R1 = 12kΩ

R2=3kΩ

VSS

VCCO

LDO VDD

VCC

VSS

DIVOEN

Note:TheVoltageDivider=R1:R2=12kΩ:3kΩ=4:1,VCCO=R2/(R1+R2)×VCC=0.2×VCC.

LDO Control Register

• DIVOC Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — — DIVOENR/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas"0"Bit0 DIVOEN:VCCdivideroutputenablecontrol

0:Disable1:Enable

WhentheDIVOENbitisclearedto0,theVCCOisinafloatingstatus.WhentheDIVOENbitissethigh,theVCCOvoltageisequaltoVCC/5.

Rev. 1.00 64 ea 01 Rev. 1.00 65 ea 01



Over Voltage Protection – OVPThedevice includesanovervoltageprotectionfunction,alsoknownasOVP,whichprovidesaprotectionmechanismforapplications.Topreventtheoperatingvoltagefromexceedingaspecificlevel, thevoltageon theOVPIpin iscomparedwitha referencevoltagegeneratedbya12-bitDAC.Whenanovervoltageeventoccurs,anOVPinterruptwillbegeneratedifthecorrespondinginterruptcontrolisenabled.

OVPINT

OVPCHYS1

-

+

OVPCOUT

Deonce

OVPDEB[:0]

fSYS

1-itDAC

OVPDAL[7:0]

S0

S CMP

OVPO

OVPSPOL

OVPDAH[3:0]

VDD

OVPEN

OVPENOVPI

OVPCOM OVPCRS

Over Voltage Protection Circuit

Theon/offcontrolfortheswitchesS0,S1andS2issummarisedinthefollowingtable.

OVPCOFM OVPCRS S0 S1 S20 x ON ON O1 0 O ON ON1 1 ON O ON

"x": Don’t cae

Over Voltage Protection OperationThesourcevoltageissuppliedontheOVPIpinandthenconnectedtooneinputofthecomparator.ADACisusedtogenerateareferencevoltage.ThecomparatorcomparesthereferencevoltagewiththeinputvoltagetoproducetheOVPOsignal.

Over Voltage Protection Control RegistersOveralloperationoftheovervoltageprotectioniscontrolledusingseveralregisters.Oneregisterisusedtoprovidethereferencevoltagesfortheovervoltageprotectioncircuit.TheremainingtworegistersarecontrolregisterswhichareusedtocontroltheOVPfunction,DACreferencevoltageselection,comparatorde-bouncetime,comparatorhysteresisfunctiontogetherwiththecomparatorinputoffsetcalibration.

RegisterName

Bit

7 6 5 4 3 2 1 0

OVPC0 OVPCOUT OVPSPOL OVPEN OVPCHY — OVPDEB OVPDEB1 OVPDEB0

OVPC1 OVPO OVPCOM OVPCRS OVPCO4 OVPCO3 OVPCO OVPCO1 OVPCO0

OVPDAL D7 D6 D5 D4 D3 D D1 D0

OVPDAH — — — — D3 D D1 D0

OVP Control Registers List

Rev. 1.00 64 ea 01 Rev. 1.00 65 ea 01



• OVPC0 Register

Bit 7 6 5 4 3 2 1 0Name OVPCOUT OVPSPOL OVPEN OVPCHY — OVPDEB OVPDEB1 OVPDEB0R/W R R/W R/W R/W — R/W R/W R/WPOR 0 0 0 0 — 0 0 0

Bit7 OVPCOUT:OVPcomparatoroutput0:Positiveinputvoltage<negativeinputvoltage1:Positiveinputvoltage>negativeinputvoltage

Bit6 OVPSPOL:OVPOpolaritycontrol0:Non-inverted1:Inverted

Bit5 OVPEN:OVPfunctionenablecontrol0:Disable1:Enable

IftheOVPENbitisclearedto0,theovervoltageprotectionfunctionisdisabledandnopowerwillbeconsumed.ThisresultsinthecomparatorandD/AconverterofOVPbothbeingswitchedoff.

Bit4 OVPCHY:OVPcomparatorhysteresisfunctionenablecontrol0:Disable1:Enable

Bit3 Unimplemented,readas"0"Bit2~0 OVPDEB2~OVPDEB0:OVPcomparatordebouncetimecontrol

000:Nodebounce001:(1~2)×1/fSYS

010:(3~4)×1/fSYS

011:(7~8)×1/fSYS

100:(15~16)×1/fSYS

101:(31~32)×1/fSYS

110:(63~64)×1/fSYS

111:(127~128)×1/fSYS

• OVPC1 Register

Bit 7 6 5 4 3 2 1 0Name OVPO OVPCOM OVPCRS OVPCO4 OVPCO3 OVPCO OVPCO1 OVPCO0R/W R R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 1 0 0 0 0

Bit7 OVPO:OVPcomparatordebounceoutputTheOVPOisthedebounceversionofOVPCOUT.

Bit6 OVPCOFM:OVPcomparatornormaloperationor inputoffsetvoltagecalibrationmodeselection0:Normaloperation1:Inputoffsetvoltagecalibrationmode

Bit5 OVPCRS:OVPcomparatorinputoffsetvoltagecalibrationreferenceselection0:Inputreferencevoltagecomesfromnegativeinput1:Inputreferencevoltagecomesfrompositiveinput

Bit4~0 OVPCOF4~OVPCOF0:OVPcomparatorinputoffsetvoltagecalibrationcontrol

Rev. 1.00 66 ea 01 Rev. 1.00 67 ea 01



• OVPDAL Register


Bit7~0 D7~ D0:OVPDACoutputvoltagecontrolNote:Thedata in theOVPDALregister isonlywritten intoshadowbuffer,and

thedatawillbecopiedinto theOVPDALregisteruntilwritingdata into theOVPDAHregister.

• OVPDAH Register

Bit 7 6 5 4 3 2 1 0Name — — — — D3 D D1 D0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3~0 D3~D0:OVPDACoutputvoltagecontrol

DACVOUT=(VDD/4096)×OVPDAH[3:0],OVPDAL[7:0]

Input Offset CalibrationTheOVPCOFMbitintheOVPC1registerisusedtoselecttheOVPcomparatoroperatingmode,normaloperationorinputoffsetcalibrationmode.Ifsetthebithigh,thecomparatorwillentertheoffsetvoltagecalibrationmode.Itisneedtonotethatbeforeoffsetcalibration,thehysteresisvoltageshouldbezerobyclearingtheOVPCHYbitto0.BecausetheOVPIpinispin-sharedwithI/Oorotherpinfunctions,itshouldbeconfiguredascomparatorinputfirst.Forcomparatorinputoffsetcalibration,theproceduresaresummarisedinthefollowingsteps.

Step1:SetOVPCOFM=1,OVPCRS=1,theOVPisnowinthecomparatorcalibrationmode,S0andS2on.TomakesureVOSasminimiseaspossibleaftercalibration,theinputreferencevoltageincalibrationmodeshouldbe thesameas inputDCoperatingvoltage innormalmodeoperation.

Step2:SetOVPCOF[4:0]=00000thenreadtheOVPObitstatus.

Step3:LetOVPCOF[4:0]=OVPCOF[4:0]+1thenreadtheOVPObitstatus, ifOVPOischanged,recordtheOVPCOF[4:0]dataasVOS1.

Step4:SetOVPCOF[4:0]=11111thenreadtheOVPObitstatus.

Step5:LetOVPCOF[4:0]=OVPCOF[4:0]-1 then read theOVPObit status, ifOVPOdata ischanged,recordtheOVPCOF[4:0]dataasVOS2.

Step6:RestoreVOS=(VOS1+VOS2)/2totheOVPCOF[4:0]bits.Thecalibrationisfinished.

If(VOS1+VOS2)/2isnotintegral,discardthedecimal.ResidueVOS=VOUT-VIN

Rev. 1.00 66 ea 01 Rev. 1.00 67 ea 01



InterruptsInterruptsareanimportantpartofanymicrocontrollersystem.WhenanexternaleventoraninternalfunctionsuchasatouchactionorTimer/Counteroverflowrequiresmicrocontrollerattention,theircorresponding interruptwillenforcea temporarysuspensionof themainprogramallowing themicrocontrollertodirectattentiontotheirrespectiveneeds.Thedevicecontainsanexternalinterruptandseveralinternalinterruptsfunctions.TheexternalinterruptsaregeneratedbytheactionoftheexternalINTpin,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchastheTouchKeys,Timer/EventCounter,TimeBase,andOverVoltageProtection.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontroller conditionsoccur and the settingof interrupt enablebitsby the applicationprogram, iscontrolledbyaseriesof registers, located in theSpecialPurposeDataMemory,asshownintheaccompanyingtable.Thenumberofregistersfallsintotwocategories.ThefirstistheINTC0~INTC1registerswhichsetuptheprimaryinterrupts,thesecondistheINTEGregisterwhichsetuptheexternalinterrupttriggeredgetype.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran"E"forenable/disablebitor"F"forrequestflag.

Function Enable Bit Request FlagGloal EMI —INT Pin INTE INTToch Ke TKME TKMTime/Event Conte TE TOve Voltage Potection OVPE OVPTime Base TBE TB

Interrupt Register Bit Naming Conventions

Register Name

Bit

7 6 5 4 3 2 1 0INTEG — — — — — — INTS1 INTS0

INTC0 — T TKM INT TE TKME INTE EMI

INTC1 — — TB OVP — — TBE OVPE

Interrupt Registers List

• INTEG Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — INTS1 INTS0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 INTS1~INTS0:InterruptedgecontrolforINTpin

00:Disable01:Risingedge10:Fallingedge11:Risingandfallingedges

Rev. 1.00 6 ea 01 Rev. 1.00 69 ea 01



• INTC0 Register

Bit 7 6 5 4 3 2 1 0Name — T TKM INT TE TKME INTE EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6 TF:Timer/EventCounterinterruptrequestflag

0:Norequest1:Interruptrequest

Bit5 TKMF:Touchkeymoduleinterruptrequestflag0:Norequest1:Interruptrequest

Bit4 INTF:INTinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 TE:Timer/EventCounterinterruptcontrol0:Disable1:Enable

Bit2 TKME:Touchkeymoduleinterruptcontrol0:Disable1:Enable

Bit1 INTE:INTinterruptcontrol0:Disable1:Enable

Bit0 EMI:Globalinterruptcontrol0:Disable1:Enable

• INTC1 Register

Bit 7 6 5 4 3 2 1 0Name — — TB OVP — — TBE OVPER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 TBF:TimeBaseinterruptrequestflag

0:Norequest1:Interruptrequest

Bit4 OVPF:OVPinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 TBE:TimeBaseinterruptcontrol

0:Disable1:Enable

Bit0 OVPE:OVPinterruptcontrol0:Disable1:Enable

Rev. 1.00 6 ea 01 Rev. 1.00 69 ea 01



Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTimer/EventCounterortouchkeytimeslotcounteroverflowsetc., therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea"JMP"whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha"RETI",whichretrieves theoriginalProgramCounteraddress fromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramswiththeirorderofpriority.Onceaninterruptsubroutineisserviced,alltheother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurther interruptnestingfromoccurring.However, ifotherinterruptrequestsoccurduringthisinterval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

Intept Name

Reqestlags

Enale Bits

Maste Enale Vector

EMI ato disaled in ISR

PioitHigh

Low

InteptName

Reqest lags

Enale Bits

xxE Enale Bits

xx Reqest lag ato eset in ISR

Legend

Time Base TB TBE EMI 14H

10HOVP OVP OVPE EMI

0CHEMIT TETime/Event Conte

0HTKM TKME EMIToch Ke

04HINT Pin INT INTE EMI

Interrupt Structure

Rev. 1.00 70 ea 01 Rev. 1.00 71 ea 01



External InterruptTheexternal interruptsarecontrolledbysignal transitionsontheINTpin.Anexternal interruptrequestwill takeplacewhentheexternal interruptrequestflag,INTF,areset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternal interruptpin.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INTE,mustfirstbeset.Additionallythecorrect interruptedgetypemustbeselectedusingtheINTEGregister toenable theexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpin ispin-sharedwithI/Opin,itcanonlybeconfiguredasexternalinterruptpiniftheirexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflag,INTF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionontheexternalinterruptpinwillremainvalidevenifthepinisusedasanexternalinterruptinput.

TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.

Touch Key Module InterruptATouchKeyModuleInterruptrequestwilltakeplacewhentheTouchKeyModuleInterruptrequestflag,TKMF,isset,whichoccurswhenthe touchkeytimeslotcounteroverflows.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtheTouchKeyModuleInterruptenablebit,TKME,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandthetouchkeytimeslotcounteroverflows,asubroutinecalltotherespectiveInterruptvector,will takeplace.Whentheinterrupt isserviced, theTouchKeyModuleInterruptflag,TKMF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Timer/Event Counter InterruptAnactualTimer/EventCounter interruptrequestwill takeplacewhentheTimer/EventCounterinterruptrequestflag,TF,isset,whichoccurswhentheTimer/EventCounteroverflows.Toallowtheprogramtobranch to its respective interruptvectoraddress, theglobal interruptenablebit,EMI,andtheTimer/EventCounterInterruptenablebit,TE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTimer/EventCounteroverflows,asubroutinecalltotherespectiveInterruptvector,willtakeplace.Whentheinterruptisserviced,theTimer/EventCounterInterruptflag,TF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Over Voltage Protection InterruptTheOVPInterrupt iscontrolledbydetecting the inputvoltage.AnOVPInterrupt requestwilltakeplacewhentheOVPInterruptrequestflag,OVPF,isset,whichoccurswhenalargevoltageisdetected.Toallowtheprogramtobranchto itsrespective interruptvectoraddress, theglobalinterruptenablebit,EMI,andOVPInterruptenablebit,OVPE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalargevoltageisdetected,asubroutinecalltotheOVPInterruptvector,will takeplace.When the interrupt is serviced, theOVPInterrupt flag,OVPF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Rev. 1.00 70 ea 01 Rev. 1.00 71 ea 01



Time Base InterruptThefunctionoftheTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappens their respective interrupt request flag,TBFwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebit,TBE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecalltotheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TBF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.Itsclocksource,fPSC,originatesfromtheinternalclocksourcefSYS, fSYS/4orfSUBandthenpasses throughadivider,thedivisionratioofwhichisselectedbyprogrammingtheappropriatebitsintheTBCregistertoobtainlonger interruptperiodswhosevalueranges.Theclocksourcewhichinturncontrols theTimeBaseinterruptperiodisselectedusingtheCLKSEL1~CLKSEL0bitsinthePSCRregister.

MUX

fSYS/4fSYS

fSUB

Pescale

CLKSEL[1:0]

fPSC fPSC/ ~ fPSC/15 MUX

TB[:0]

Time Base Intept

TBON

Time Base Interrupt

• PSCR Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — CLKSEL1 CLKSEL0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 CLKSEL1~CLKSEL0:Prescalerclocksourceselection

00:fSYS

01:fSYS/41x:fSUB

• TBC Register

Bit 7 6 5 4 3 2 1 0Name TBON — — — — TB TB1 TB0R/W R/W — — — — R/W R/W R/WPOR 0 — — — — 0 0 0

Bit7 TBON:TimeBaseControl0:Disable1:Enable

Bit6~3 Unimplemented,readas"0"Bit2~0 TB2~TB0:SelectTimeBaseTime-outPeriod

000:28/fPSC

001:29/fPSC

010:210/fPSC

011:211/fPSC

100:212/fPSC

101:213/fPSC

110:214/fPSC

111:215/fPSC

Rev. 1.00 7 ea 01 Rev. 1.00 73 ea 01



Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandis independentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionontheexternalinterruptpinmaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenters theSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe"CALL"instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

Rev. 1.00 7 ea 01 Rev. 1.00 73 ea 01



Application Descriptions – Dimming and Toning Touch Desk Lights

IntroductionThedimmingandtoningtouchdesklightshavemainlythreefunctionssuchas touchdetecting,PWMregulationandhighvoltagedriving.Ifthedevicewiththeinputvoltageof12Vhasdetectedthatthekeyispressed,thelightbrightnesswillbechanged.WhenthetwoLEDmodulesuseyellowlightandwhitelightrespectively,differentlightcolorswillbegeneratedthroughdifferentyellowandwhitelightratios.Thefunctionalprinciplewillbedescribedasfollows.

Functional DescriptionThesystempowersupplyis12V.EachLEDmodulehasthreeserialLEDsandacurrentlimitingresistor,whichcanlimit themaximumcurrentflowingthroughLEDstoprevent theLEDsfromburningbecauseof toolargecurrent.Thedevicealsoprovidesovervoltageprotectionfunction,whichcandetect theVCCvoltagewithHighVoltagedivider.If theVCCvoltageis toohigh, theHVOoutputwillbeofftoavoidburningLEDsbecauseoftoolargecurrent.Inthisapplication,theLEDmodule0usewhiteLED,whiletheLEDmodule1usewarmwhiteLED,userscanadjustthesetwomodulesPWMdutytogetdifferentcolortemperaturebymixingdifferentbrightnessratios.

Thereare two touchkeys in the light control section, and theKEY1 isused toadjust colortemperature,whiletheKEY2isusedtoadjustbrightness.

Hardware Block Diagram

PWM0LDO

BS45F5930

VCC

KEY1

KEY

OVP

HVO0

HV divide

PWM1 HVO1

Toch keHTMCUCoe

I/O

LEDModle 0

LEDModle1

Rev. 1.00 74 ea 01 Rev. 1.00 75 ea 01



Color Temperature Adjustment Key (KEY1)TheKEY1functionsettingiscircular.Afterpoweronreset, theKEY1ispresetedtoturnoff.ThelightwillbeswitchedtocoldlightthroughtouchingtheKEY1,thenthelightwillbecuttoneutrallightthroughtouchingtheKEY1againandsoon.Thisprocesswillbeshowninthefollowingfigure.

Wam light

Off

Cold light

Netal light

Dimming Key (KEY2)TheKEY2functionsettingiscircular.Afterpoweronreset,theKEY2ispresetedtothefirstlevel.ThelightwillbeswitchedtothesecondlevelthroughtouchingtheKEY2,thenthelightwillbeswitchedtothethirdlevelthroughtouchingtheKEY2againandsoon.Therearesevenbrightnessleveloptionsintheapplication,whichisshowninthefollowingfigure.

The seventh level

The fist level

The second level

The thid level

The sixth level

The fifth level

The foth level

Color Temperature DefinitionThecolortemperaturedefinitionisshowninthefollowingtable.ThePWMdutycycleismarkedbynumber,whichcanchangebrightnesswithoutaffectingcolor temperature in thesamecolortemperaturemode.Whenthebrightnessisenhanced,thedutycycleintwoLEDmoduleswillbenotincreasedbyanequalratio.ThevaluesinthefollowingtableareforreferenceonlyandthedifferentLEDbeadswillhavedifferentsetting.

PWM DutyWarm Light Neutral Light Cold Light

Warm White White Warm White White Warm White WhiteThe first level 9% % 5% 5% % 9%The second level 3% 3% 1% 1% 3% 3%The thid level 36% 4% 0% 0% 4% 36%The foth level 50% 6% % % 6% 50%The fifth level 63% 7% 35% 35% 7% 63%The sixth level 77% 9% 43% 43% 9% 77%The seventh level 90% 10% 50% 50% 10% 90%

Rev. 1.00 74 ea 01 Rev. 1.00 75 ea 01



Hardware Circuit Diagram

GND

10uF

0.1uF

0.1uF

GND

5V

GND

VCC 2

VSS 10

VDD 1

9 KEY1

8 KEY2

OVP0

PWM0

OVP1

PWM1

BS45F5930

12V

10uF

PAD

PAD

20R

20R

20R

20R

36

47

Rev. 1.00 76 ea 01 Rev. 1.00 77 ea 01



Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe"CLRPCL"or"MOVPCL,A".Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

Rev. 1.00 76 ea 01 Rev. 1.00 77 ea 01



Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction"RET"inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe"SET[m].i"or"CLR[m].i" instructionsrespectively.Thefeatureremovestheneedforprogrammers tofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemory tobesetasa tablewheredatacanbedirectlystored.Asetofeasy touse instructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe"HALT"instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

Rev. 1.00 7 ea 01 Rev. 1.00 79 ea 01



Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A[m] Add Data Memo to ACC 1 Z C AC OVADDM A[m] Add ACC to Data Memo 1Note Z C AC OVADD Ax Add immediate data to ACC 1 Z C AC OVADC A[m] Add Data Memo to ACC with Ca 1 Z C AC OVADCM A[m] Add ACC to Data memo with Ca 1Note Z C AC OVSUB Ax Stact immediate data fom the ACC 1 Z C AC OVSUB A[m] Stact Data Memo fom ACC 1 Z C AC OVSUBM A[m] Stact Data Memo fom ACC with eslt in Data Memo 1Note Z C AC OVSBC A[m] Stact Data Memo fom ACC with Ca 1 Z C AC OVSBCM A[m] Stact Data Memo fom ACC with Ca eslt in Data Memo 1Note Z C AC OVDAA [m] Decimal adjst ACC fo Addition with eslt in Data Memo 1Note CLogic OperationAND A[m] Logical AND Data Memo to ACC 1 ZOR A[m] Logical OR Data Memo to ACC 1 ZXOR A[m] Logical XOR Data Memo to ACC 1 ZANDM A[m] Logical AND ACC to Data Memo 1Note ZORM A[m] Logical OR ACC to Data Memo 1Note ZXORM A[m] Logical XOR ACC to Data Memo 1Note ZAND Ax Logical AND immediate Data to ACC 1 ZOR Ax Logical OR immediate Data to ACC 1 ZXOR Ax Logical XOR immediate Data to ACC 1 ZCPL [m] Complement Data Memo 1Note ZCPLA [m] Complement Data Memo with eslt in ACC 1 ZIncrement & DecrementINCA [m] Incement Data Memo with eslt in ACC 1 ZINC [m] Incement Data Memo 1Note ZDECA [m] Decement Data Memo with eslt in ACC 1 ZDEC [m] Decement Data Memo 1Note ZRotateRRA [m] Rotate Data Memo ight with eslt in ACC 1 NoneRR [m] Rotate Data Memo ight 1Note NoneRRCA [m] Rotate Data Memo ight thogh Ca with eslt in ACC 1 CRRC [m] Rotate Data Memo ight thogh Ca 1Note CRLA [m] Rotate Data Memo left with eslt in ACC 1 NoneRL [m] Rotate Data Memo left 1Note NoneRLCA [m] Rotate Data Memo left thogh Ca with eslt in ACC 1 CRLC [m] Rotate Data Memo left thogh Ca 1Note C

Rev. 1.00 7 ea 01 Rev. 1.00 79 ea 01



Mnemonic Description Cycles Flag AffectedData MoveMOV A[m] Move Data Memo to ACC 1 NoneMOV [m]A Move ACC to Data Memo 1Note NoneMOV Ax Move immediate data to ACC 1 NoneBit OperationCLR [m].i Clea it of Data Memo 1Note NoneSET [m].i Set it of Data Memo 1Note NoneBranch OperationJMP add Jmp nconditionall NoneSZ [m] Skip if Data Memo is zeo 1Note NoneSZA [m] Skip if Data Memo is zeo with data movement to ACC 1Note NoneSZ [m].i Skip if it i of Data Memo is zeo 1Note NoneSNZ [m].i Skip if it i of Data Memo is not zeo 1Note NoneSIZ [m] Skip if incement Data Memo is zeo 1Note NoneSDZ [m] Skip if decement Data Memo is zeo 1Note NoneSIZA [m] Skip if incement Data Memo is zeo with eslt in ACC 1Note NoneSDZA [m] Skip if decement Data Memo is zeo with eslt in ACC 1Note NoneCALL add Sotine call NoneRET Retn fom sotine NoneRET Ax Retn fom sotine and load immediate data to ACC NoneRETI Retn fom intept NoneTable Read OperationTABRD [m] Read table (specific page) to TBLH and Data Memory Note NoneTABRDC [m] Read tale (cent page) to TBLH and Data Memo Note NoneTABRDL [m] Read tale (last page) to TBLH and Data Memo Note NoneMiscellaneousNOP No opeation 1 NoneCLR [m] Clea Data Memo 1Note NoneSET [m] Set Data Memo 1Note NoneCLR WDT Clea Watchdog Time 1 TO PDCLR WDT1 Pe-clea Watchdog Time 1 TO PDCLR WDT Pe-clea Watchdog Time 1 TO PDSWAP [m] Swap niles of Data Memo 1Note NoneSWAPA [m] Swap niles of Data Memo with eslt in ACC 1 NoneHALT Ente powe down mode 1 TO PD

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the"CLRWDT1"and"CLRWDT2"instructions theTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDF flagsareclearedafterboth "CLRWDT1"and"CLRWDT2"instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

Rev. 1.00 0 ea 01 Rev. 1.00 1 ea 01



Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

Rev. 1.00 0 ea 01 Rev. 1.00 1 ea 01



CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

Rev. 1.00 ea 01 Rev. 1.00 3 ea 01



CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

Rev. 1.00 ea 01 Rev. 1.00 3 ea 01



JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

Rev. 1.00 4 ea 01 Rev. 1.00 5 ea 01



RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

Rev. 1.00 4 ea 01 Rev. 1.00 5 ea 01



RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryisrotatedrightby1bitwithbit0rotatedintobit7. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

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SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

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SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

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TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

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Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

• FurtherPackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

• PackingMeterialsInformation

• Cartoninformation

http://www.holtek.com/en/

http://www.holtek.com/en/package_carton_information

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8-pin SOP (150mil) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max.A — 0.36 BSC —

B — 0.154 BSC —

C 0.01 — 0.00C’ — 0.193 BSC —D — — 0.069E — 0.050 BSC — 0.004 — 0.010G 0.016 — 0.050H 0.004 — 0.010α 0° — °

SymbolDimensions in mm

Min. Nom. Max.A — 6 BSC —B — 3.9 BSC —C 0.31 — 0.51

C’ — 4.9 BSC —

D — — 1.75E — 1.7 BSC — 0.10 — 0.5G 0.40 — 1.7H 0.10 — 0.5α 0° — °

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10-pin SOP (150mil) Outline Dimensions


Min. Nom. Max.A — 0.36 BSC —B — 0.154 BSC —C 0.01 — 0.01C’ — 0.193 BSC —D — — 0.069E — 0.039 BSC — 0.004 — 0.010G 0.016 — 0.050H 0.004 — 0.010α 0° — °


Min. Nom. Max.A — 6.00 BSC —B — 3.90 BSC —C 0.30 — 0.45C’ — 4.90 BSC —D — — 1.75E — 1.00 BSC — 0.10 — 0.5G 0.40 — 1.7H 0.10 — 0.5α 0° — °

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16-pin NSOP (150mil) Outline Dimensions


Min. Nom. Max.A — 0.36 BSC —

B — 0.154 BSC —

C 0.01 — 0.00C’ — 0.390 BSC —D — — 0.069E — 0.050 BSC — 0.004 — 0.010G 0.016 — 0.050H 0.004 — 0.010α 0° — °


Min. Nom. Max.A — 6 BSC —B — 3.9 BSC —C 0.31 — 0.51C’ — 9.9 BSC —D — — 1.75E — 1.7 BSC — 0.10 — 0.5G 0.40 — 1.7H 0.10 — 0.5α 0° — °

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Copight© 01 HOLTEK SEMICONDUCTOR INC.

The infomation appeaing in this Data Sheet is elieved to e accate at the time of plication. Howeve Holtek assmes no esponsiilit aising fom the se of the specifications described. The applications mentioned herein are used solely fo the ppose of illstation and Holtek makes no waant o epesentation that sch applications will e sitale withot fthe modification no ecommends the se of its podcts fo application that ma pesent a isk to hman life de to malfnction o othewise. Holtek's podcts ae not athoized fo se as citical components in life sppot devices o sstems. Holtek eseves the ight to alte its products without prior notification. For the most up-to-date information, please visit o we site at http://www.holtek.com/en/.

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