HT32F50343 User Manual - Holtek

HT32F50343 User Manual
Rev. 1.00 2 of 508 May 21, 2020
32-Bit Arm® Cortex®-M0+ MCU HT32F50343
Table of C ontents
Overview .............................................................................................................................. 23 Features ............................................................................................................................... 23 Device Information ............................................................................................................... 27 Block Diagram ..................................................................................................................... 28
2 Document Conventions ....................................................................................... 29
3 System Architecture ............................................................................................. 30 Arm® Cortex®-M0+ Processor .............................................................................................. 30 Bus Architecture ................................................................................................................... 31 Memory Organization .......................................................................................................... 32
Memory Map ................................................................................................................................... 33 Embedded Flash Memory ............................................................................................................... 35 Embedded SRAM Memory ............................................................................................................. 35 AHB Peripherals ............................................................................................................................. 36 APB Peripherals ............................................................................................................................. 36
4 Flash Memory Controller (FMC) .......................................................................... 37 Introduction .......................................................................................................................... 37 Features ............................................................................................................................... 37 Functional Descriptions ....................................................................................................... 38
Flash Memory Map ......................................................................................................................... 38 Flash Memory Architecture ............................................................................................................. 39 Wait State Setting ........................................................................................................................... 39 Booting Configuration ..................................................................................................................... 40 Page Erase ..................................................................................................................................... 40 Mass Erase ..................................................................................................................................... 42 Word Programming ......................................................................................................................... 43 Option Byte Description .................................................................................................................. 44 Page Erase/Program Protection ..................................................................................................... 45 Security Protection .......................................................................................................................... 46
Register Map ....................................................................................................................... 47 Register Descriptions ........................................................................................................... 48
Flash Target Address Register – TADR .......................................................................................... 48 Flash Write Data Register – WRDR ............................................................................................... 49 Flash Operation Command Register – OCMR ............................................................................... 50 Flash Operation Control Register – OPCR ..................................................................................... 51 Flash Operation Interrupt Enable Register – OIER ........................................................................ 52 Flash Operation Interrupt and Status Register – OISR .................................................................. 53 Flash Page Erase/Program Protection Status Register – PPSR .................................................... 55 Flash Security Protection Status Register – CPSR ........................................................................ 56
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Flash Vector Mapping Control Register – VMCR ........................................................................... 57 Flash Manufacturer and Device ID Register – MDID ...................................................................... 58 Flash Page Number Status Register – PNSR ................................................................................ 59 Flash Page Size Status Register – PSSR ...................................................................................... 60 Device ID Register – DID ................................................................................................................ 60 Flash Pre-fetch Control Register – CFCR ...................................................................................... 61 Custom ID Register n – CIDRn (n = 0 ~ 3) ..................................................................................... 62
5 Power Control Unit (PWRCU) .............................................................................. 63 Introduction .......................................................................................................................... 63 Features ............................................................................................................................... 64 Functional Descriptions ....................................................................................................... 64
VDD Power Domain .......................................................................................................................... 64 1.5 V Power Domain ....................................................................................................................... 66 Operation Modes ............................................................................................................................ 66
Power Control Status Register – PWRSR ...................................................................................... 69 Power Control Register – PWRCR ................................................................................................. 70 Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 73
6 Clock Control Unit (CKCU) .................................................................................. 75 Introduction .......................................................................................................................... 75 Features ............................................................................................................................... 77 Functional Descriptions ....................................................................................................... 77
High Speed External Crystal Oscillator – HSE ............................................................................... 77 High Speed Internal RC Oscillator – HSI ........................................................................................ 78 Auto Trimming of High Speed Internal RC Oscillator – HSI ............................................................ 78 Phase Locked Loop – PLL .............................................................................................................. 80 USB Phase Locked Loop – USB PLL ............................................................................................. 81 Low Speed External Crystal Oscillator – LSE ................................................................................. 83 Low Speed Internal RC Oscillator – LSI ......................................................................................... 83 Clock Ready Flag ........................................................................................................................... 83 System Clock (CK_SYS) Selection ................................................................................................ 83 HSE Clock Monitor ......................................................................................................................... 84 Clock Output Capability .................................................................................................................. 84
Global Clock Configuration Register – GCFGR .............................................................................. 86 Global Clock Control Register – GCCR .......................................................................................... 87 Global Clock Status Register – GCSR ........................................................................................... 89 Global Clock Interrupt Register – GCIR .......................................................................................... 90 PLL Configuration Register – PLLCFGR ........................................................................................ 91 PLL Control Register – PLLCR ....................................................................................................... 92
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AHB Configuration Register – AHBCFGR ...................................................................................... 93 AHB Clock Control Register – AHBCCR ........................................................................................ 94 APB Configuration Register – APBCFGR ....................................................................................... 96 APB Clock Control Register 0 – APBCCR0 .................................................................................... 97 APB Clock Control Register 1 – APBCCR1 .................................................................................... 98 Clock Source Status Register – CKST ......................................................................................... 100 APB Peripheral Clock Selection Register 0 – APBPCSR0 ........................................................... 101 APB Peripheral Clock Selection Register 1 – APBPCSR1 ........................................................... 103 HSI Control Register – HSICR ...................................................................................................... 104 HSI Auto Trimming Counter Register – HSIATCR ........................................................................ 106 APB Peripheral Clock Selection Register 2 – APBPCSR2 ........................................................... 107 Low Power Control Register – LPCR ........................................................................................... 108 MCU Debug Control Register – MCUDBGCR .............................................................................. 109
7 Reset Control Unit (RSTCU) ...............................................................................111 Introduction .........................................................................................................................111 Functional Descriptions ......................................................................................................111
Global Reset Status Register – GRSR ..........................................................................................113 AHB Peripheral Reset Register – AHBPRSTR ..............................................................................114 APB Peripheral Reset Register 0 – APBPRSTR0 .........................................................................115 APB Peripheral Reset Register 1 – APBPRSTR1 .........................................................................116
8 General Purpose I/O (GPIO) ............................................................................... 118 Introduction ........................................................................................................................ 118 Features ............................................................................................................................. 119 Functional Descriptions ..................................................................................................... 119
Default GPIO Pin Configuration .....................................................................................................119 General Purpose I/O – GPIO .........................................................................................................119 GPIO Locking Mechanism ............................................................................................................ 121
Register Map ..................................................................................................................... 121 Register Descriptions ......................................................................................................... 123
Port A Data Direction Control Register – PADIRCR ..................................................................... 123 Port A Input Function Enable Control Register – PAINER ............................................................ 124 Port A Pull-Up Selection Register – PAPUR ................................................................................. 125 Port A Pull-Down Selection Register – PAPDR ............................................................................ 126 Port A Open-Drain Selection Register – PAODR .......................................................................... 127 Port A Drive Current Selection Register – PADRVR ..................................................................... 128 Port A Lock Register – PALOCKR ................................................................................................ 129 Port A Data Input Register – PADINR ........................................................................................... 130
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Port A Output Data Register – PADOUTR .................................................................................... 130 Port A Output Set/Reset Control Register – PASRR .................................................................... 131 Port A Output Reset Register – PARR .......................................................................................... 132 Port B Data Direction Control Register – PBDIRCR ..................................................................... 132 Port B Input Function Enable Control Register – PBINER ........................................................... 133 Port B Pull-Up Selection Register – PBPUR ................................................................................ 134 Port B Pull-Down Selection Register – PBPDR ............................................................................ 135 Port B Open-Drain Selection Register – PBODR ......................................................................... 136 Port B Drive Current Selection Register – PBDRVR .................................................................... 137 Port B Lock Register – PBLOCKR ................................................................................................ 138 Port B Data Input Register – PBDINR .......................................................................................... 139 Port B Output Data Register – PBDOUTR ................................................................................... 139 Port B Output Set/Reset Control Register – PBSRR .................................................................... 140 Port B Output Reset Register – PBRR ......................................................................................... 141 Port C Data Direction Control Register – PCDIRCR .................................................................... 141 Port C Input Function Enable Control Register – PCINER ........................................................... 142 Port C Pull-Up Selection Register – PCPUR ................................................................................ 143 Port C Pull-Down Selection Register – PCPDR ........................................................................... 144 Port C Open-Drain Selection Register – PCODR ......................................................................... 145 Port C Drive Current Selection Register – PCDRVR .................................................................... 146 Port C Lock Register – PCLOCKR ............................................................................................... 147 Port C Data Input Register – PCDINR .......................................................................................... 148 Port C Output Data Register – PCDOUTR ................................................................................... 148 Port C Output Set/Reset Control Register – PCSRR ................................................................... 149 Port C Output Reset Register – PCRR ......................................................................................... 150 Port D Data Direction Control Register – PDDIRCR .................................................................... 151 Port D Input Function Enable Control Register – PDINER ........................................................... 152 Port D Pull-Up Selection Register – PDPUR ................................................................................ 153 Port D Pull-Down Selection Register – PDPDR ........................................................................... 154 Port D Open-Drain Selection Register – PDODR ......................................................................... 155 Port D Drive Current Selection Register – PDDRVR .................................................................... 156 Port D Lock Register – PDLOCKR ............................................................................................... 157 Port D Data Input Register – PDDINR .......................................................................................... 158 Port D Output Data Register – PDDOUTR ................................................................................... 159 Port D Output Set/Reset Control Register – PDSRR ................................................................... 160 Port D Output Reset Register – PDRR ......................................................................................... 161
9 Alternate Function Input/Output Control Unit (AFIO) ...................................... 162 Introduction ........................................................................................................................ 162 Features ............................................................................................................................. 163 Functional Descriptions ..................................................................................................... 163
External Interrupt Pin Selection .................................................................................................... 163 Alternate Function ......................................................................................................................... 164 Lock Mechanism .......................................................................................................................... 164
Register Map ..................................................................................................................... 164
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Register Descriptions ......................................................................................................... 165 EXTI Source Selection Register 0 – ESSR0 ................................................................................ 165 EXTI Source Selection Register 1 – ESSR1 ................................................................................ 166 GPIO x Configuration Low Register – GPxCFGLR, x = A, B, C, D ............................................... 167 GPIO x Configuration High Register – GPxCFGHR, x = A, B, C, D ............................................. 168
10 Nested Vectored Interrupt Controller (NVIC) .................................................. 169 Introduction ........................................................................................................................ 169 Features ............................................................................................................................. 170 Functional Descriptions ..................................................................................................... 171
SysTick Calibration ....................................................................................................................... 171
Register Map ..................................................................................................................... 171
EXTI Interrupt n Configuration Register – EXTICFGRn, n = 0 ~ 15 ............................................. 175 EXTI Interrupt Control Register – EXTICR ................................................................................... 176 EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 177 EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 178 EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 179 EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 180 EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 181 EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 182
12 Analog to Digital Converter (ADC) .................................................................. 183 Introduction ........................................................................................................................ 183 Features ............................................................................................................................. 184 Functional Descriptions ..................................................................................................... 185
ADC Clock Setup .......................................................................................................................... 185 Channel Selection ......................................................................................................................... 185 Conversion Mode .......................................................................................................................... 185 Start Conversion on External Event .............................................................................................. 188 Sampling Time Setting .................................................................................................................. 189 Data Format .................................................................................................................................. 189 Analog Watchdog.......................................................................................................................... 189 Interrupts ....................................................................................................................................... 190 PDMA Request ............................................................................................................................ 190
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ADC Conversion Control Register – ADCCR ............................................................................... 192 ADC Conversion List Register 0 – ADCLST0 ............................................................................... 194 ADC Conversion List Register 1 – ADCLST1 ............................................................................... 195 ADC Input Sampling Time Register – ADCSTR ........................................................................... 196 ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ............................................................... 197 ADC Trigger Control Register – ADCTCR .................................................................................... 198 ADC Trigger Source Register – ADCTSR ..................................................................................... 199 ADC Watchdog Control Register – ADCWCR .............................................................................. 200 ADC Watchdog Threshold Register – ADCTR .............................................................................. 202 ADC Interrupt Enable Register – ADCIER .................................................................................... 203 ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 204 ADC Interrupt Status Register – ADCISR ..................................................................................... 205 ADC Interrupt Clear Register – ADCICLR .................................................................................... 206 ADC DMA Request Register – ADCDMAR ................................................................................... 207 Voltage Reference Control Register – VREFCR .......................................................................... 208
13 General-Purpose Timer (GPTM) ...................................................................... 209 Introduction ........................................................................................................................ 209 Features ............................................................................................................................. 210 Functional Descriptions ..................................................................................................... 210
Counter Mode ............................................................................................................................... 210 Clock Controller ............................................................................................................................ 212 Trigger Controller .......................................................................................................................... 214 Slave Controller ............................................................................................................................ 215 Master Controller .......................................................................................................................... 217 Channel Controller ........................................................................................................................ 218 Input Stage ................................................................................................................................... 220 Quadrature Decoder ..................................................................................................................... 222 Output Stage ................................................................................................................................. 223 Update Management .................................................................................................................... 227 Single Pulse Mode ........................................................................................................................ 228 Asymmetric PWM Mode ............................................................................................................... 230 Timer Interconnection ................................................................................................................... 230 PDMA Request ............................................................................................................................. 233
Timer Counter Configuration Register – CNTCFR ....................................................................... 235 Timer Mode Configuration Register – MDCFR ............................................................................. 236 Timer Trigger Configuration Register – TRCFR ............................................................................ 239 Timer Counter Register – CTR ..................................................................................................... 240 Channel 0 Input Configuration Register – CH0ICFR .................................................................... 241 Channel 1 Input Configuration Register – CH1ICFR .................................................................... 242 Channel 2 Input Configuration Register – CH2ICFR .................................................................... 244
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Channel 3 Input Configuration Register – CH3ICFR .................................................................... 245 Channel 0 Output Configuration Register – CH0OCFR ............................................................... 247 Channel 1 Output Configuration Register – CH1OCFR ............................................................... 249 Channel 2 Output Configuration Register – CH2OCFR ............................................................... 251 Channel 3 Output Configuration Register – CH3OCFR ............................................................... 253 Channel Control Register – CHCTR ............................................................................................. 255 Channel Polarity Configuration Register – CHPOLR .................................................................... 256 Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 257 Timer Event Generator Register – EVGR ..................................................................................... 259 Timer Interrupt Status Register – INTSR ...................................................................................... 260 Timer Counter Register – CNTR................................................................................................... 263 Timer Prescaler Register – PSCR ................................................................................................ 264 Timer Counter-Reload Register – CRR ........................................................................................ 265 Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 266 Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 267 Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 268 Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 269 Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 270 Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 270 Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 271 Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 271
14 Pulse-Width-Modulation Timer (PWM) ............................................................ 272 Introduction ........................................................................................................................ 272 Features ............................................................................................................................. 273 Functional Descriptions ..................................................................................................... 273
Counter Mode ............................................................................................................................... 273 Clock Controller ............................................................................................................................ 276 Trigger Controller .......................................................................................................................... 277 Slave Controller ............................................................................................................................ 278 Master Controller .......................................................................................................................... 280 Channel Controller ........................................................................................................................ 281 Output Stage ................................................................................................................................. 281 Update Management .................................................................................................................... 285 Single Pulse Mode ........................................................................................................................ 285 Asymmetric PWM Mode ............................................................................................................... 288 Timer Interconnection ................................................................................................................... 288 Trigger Peripherals Start ............................................................................................................... 291 PDMA Request ............................................................................................................................. 291
Timer Counter Configuration Register – CNTCFR ....................................................................... 293 Timer Mode Configuration Register – MDCFR ............................................................................. 294 Timer Trigger Configuration Register – TRCFR ............................................................................ 297
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Timer Counter Register – CTR ..................................................................................................... 298 Channel 0 Output Configuration Register – CH0OCFR .............................................................. 299 Channel 1 Output Configuration Register – CH1OCFR ............................................................... 301 Channel 2 Output Configuration Register – CH2OCFR ............................................................... 303 Channel 3 Output Configuration Register – CH3OCFR ............................................................... 305 Channel Control Register – CHCTR ............................................................................................. 307 Channel Polarity Configuration Register – CHPOLR .................................................................... 308 Timer PDMA / Interrupt Control Register – DICTR ....................................................................... 309 Timer Event Generator Register – EVGR ..................................................................................... 310 Timer Interrupt Status Register – INTSR ...................................................................................... 312 Timer Counter Register – CNTR................................................................................................... 314 Timer Prescaler Register – PSCR ................................................................................................ 315 Timer Counter Reload Register – CRR ........................................................................................ 316 Channel 0 Compare Register – CH0CR ....................................................................................... 316 Channel 1 Compare Register – CH1CR ....................................................................................... 317 Channel 2 Compare Register – CH2CR ....................................................................................... 317 Channel 3 Compare Register – CH3CR ....................................................................................... 318 Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 318 Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 319 Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 319 Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 320 Channel 4 Output Configuration Register – CH4OCFR ............................................................... 321 Channel 5 Output Configuration Register – CH5OCFR ............................................................... 322 Channel 6 Output Configuration Register – CH6OCFR ............................................................... 324 Channel 7 Output Configuration Register – CH7OCFR ............................................................... 325 Channel 4 Compare Register – CH4CR ....................................................................................... 327 Channel 5 Compare Register – CH5CR ....................................................................................... 327 Channel 6 Compare Register – CH6CR ....................................................................................... 328 Channel 7 Compare Register – CH7CR ....................................................................................... 328
15 Single-Channel Timer (SCTM) ......................................................................... 329 Introduction ........................................................................................................................ 329 Features ............................................................................................................................. 330 Functional Descriptions ..................................................................................................... 330
Counter Mode ............................................................................................................................... 330 Clock Controller ............................................................................................................................ 331 Trigger Controller .......................................................................................................................... 332 Slave Controller ............................................................................................................................ 333 Channel Controller ........................................................................................................................ 335 Input Stage ................................................................................................................................... 337 Output Stage ................................................................................................................................. 338 Update Management .................................................................................................................... 340
Timer Counter Configuration Register – CNTCFR ....................................................................... 342
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Timer Mode Configuration Register – MDCFR ............................................................................. 343 Timer Trigger Configuration Register – TRCFR ............................................................................ 344 Timer Counter Register – CTR ..................................................................................................... 345 Channel Input Configuration Register – CHICFR ......................................................................... 346 Channel Output Configuration Register – CHOCFR .................................................................... 348 Channel Control Register – CHCTR ............................................................................................. 349 Channel Polarity Configuration Register – CHPOLR .................................................................... 350 Timer Interrupt Control Register – DICTR .................................................................................... 351 Timer Event Generator Register – EVGR ..................................................................................... 352 Timer Interrupt Status Register – INTSR ...................................................................................... 353 Timer Counter Register – CNTR................................................................................................... 354 Timer Prescaler Register – PSCR ................................................................................................ 354 Timer Counter Reload Register – CRR ........................................................................................ 355 Channel Capture/Compare Register – CHCCR ........................................................................... 356
16 Basic Function Timer (BFTM) .......................................................................... 357 Introduction ........................................................................................................................ 357 Features ............................................................................................................................. 357 Functional Description ....................................................................................................... 358
Repetitive Mode ............................................................................................................................ 358 One Shot Mode ............................................................................................................................. 359 Trigger ADC Start ......................................................................................................................... 359
BFTM Control Register – BFTMCR .............................................................................................. 360 BFTM Status Register – BFTMSR ................................................................................................ 361 BFTM Counter Value Register – BFTMCNTR .............................................................................. 362 BFTM Compare Value Register – BFTMCMPR ........................................................................... 362
17 Real Time Clock (RTC) ..................................................................................... 363 Introduction ........................................................................................................................ 363 Features ............................................................................................................................. 363 Functional Descriptions ..................................................................................................... 364
RTC Related Register Reset ........................................................................................................ 364 Low Speed Clock Configuration ................................................................................................... 364 RTC Counter Operation ................................................................................................................ 364 Interrupt and Wakeup Control ....................................................................................................... 364 RTCOUT Output Pin Configuration............................................................................................... 365
RTC Counter Register – RTCCNT ................................................................................................ 366 RTC Compare Register – RTCCMP ............................................................................................. 367 RTC Control Register – RTCCR ................................................................................................... 368 RTC Status Register – RTCSR..................................................................................................... 370
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RTC Interrupt and Wakeup Enable Register – RTCIWEN ........................................................... 371
18 Watchdog Timer (WDT) .................................................................................... 372 Introduction ........................................................................................................................ 372 Features ............................................................................................................................. 373 Functional Description ....................................................................................................... 373 Register Map ..................................................................................................................... 375 Register Descriptions ......................................................................................................... 375
Watchdog Timer Control Register – WDTCR ............................................................................... 375 Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 376 Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 377 Watchdog Timer Status Register – WDTSR ................................................................................. 378 Watchdog Timer Protection Register – WDTPR ........................................................................... 379 Watchdog Timer Clock Selection Register – WDTCSR ................................................................ 380
19 Inter-Integrated Circuit (I2C) ............................................................................. 381 Introduction ........................................................................................................................ 381 Features ............................................................................................................................. 382 Functional Descriptions ..................................................................................................... 382
Two-Wire Serial Interface ............................................................................................................. 382 START and STOP Conditions ....................................................................................................... 382 Data Validity .................................................................................................................................. 383 Addressing Format ....................................................................................................................... 383 Data Transfer and Acknowledge ................................................................................................... 385 Clock Synchronization .................................................................................................................. 385 Arbitration ..................................................................................................................................... 386 General Call Addressing ............................................................................................................... 386 Bus Error ....................................................................................................................................... 386 Address Mask Enable ................................................................................................................... 387 Address Snoop ............................................................................................................................. 387 Operation Mode ............................................................................................................................ 387 Conditions of Holding SCL Line .................................................................................................... 391 I2C Timeout Function .................................................................................................................... 392 PDMA Interface ............................................................................................................................. 392
I2C Control Register – I2CCR ....................................................................................................... 393 I2C Interrupt Enable Register – I2CIER ........................................................................................ 395 I2C Address Register – I2CADDR ................................................................................................. 397 I2C Status Register – I2CSR ......................................................................................................... 398 I2C SCL High Period Generation Register – I2CSHPGR .............................................................. 401 I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 402 I2C Data Register – I2CDR ........................................................................................................... 403 I2C Target Register – I2CTAR ....................................................................................................... 404
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20 Serial Peripheral Interface (SPI) ...................................................................... 408 Introduction ........................................................................................................................ 408 Features ............................................................................................................................. 409 Functional Descriptions ..................................................................................................... 409
Master Mode ................................................................................................................................. 409 Slave Mode ................................................................................................................................... 409 SPI Serial Frame Format .............................................................................................................. 409 Status Flags .................................................................................................................................. 414 PDMA Interface ............................................................................................................................. 416
SPI Control Register 0 – SPICR0 ................................................................................................. 417 SPI Control Register 1 – SPICR1 ................................................................................................. 419 SPI Interrupt Enable Register – SPIIER ....................................................................................... 420 SPI Clock Prescaler Register – SPICPR ...................................................................................... 422 SPI Data Register – SPIDR .......................................................................................................... 423 SPI Status Register – SPISR ........................................................................................................ 424 SPI FIFO Control Register – SPIFCR ........................................................................................... 425 SPI FIFO Status Register – SPIFSR ............................................................................................ 426 SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 427
21 Universal Asynchronous Receiver Transmitter (UART) ................................ 428 Introduction ........................................................................................................................ 428 Features ............................................................................................................................. 429 Functional Descriptions ..................................................................................................... 429
Serial Data Format ........................................................................................................................ 429 Baud Rate Generation .................................................................................................................. 430 Interrupts and Status .................................................................................................................... 431 PDMA Interface ............................................................................................................................. 432
UART Data Register – URDR ....................................................................................................... 432 UART Control Register – URCR ................................................................................................... 433 UART Interrupt Enable Register – URIER .................................................................................... 434 UART Status & Interrupt Flag Register – URSIFR ....................................................................... 436 UART Divider Latch Register – URDLR ....................................................................................... 437 UART Test Register – URTSTR .................................................................................................... 438
22 USB Device Controller (USB) .......................................................................... 439 Introduction ........................................................................................................................ 439
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Features ............................................................................................................................. 439 Functional Descriptions ..................................................................................................... 440
Endpoints ...................................................................................................................................... 440 EP_SRAM ..................................................................................................................................... 440 Serial Interface Engine – SIE ........................................................................................................ 441 Double-Buffering ........................................................................................................................... 441 Suspend Mode and Wake-up ....................................................................................................... 442 Remote Wake-up .......................................................................................................................... 443
USB Control and Status Register – USBCSR .............................................................................. 444 USB Interrupt Enable Register – USBIER .................................................................................... 446 USB Interrupt Status Register – USBISR ..................................................................................... 447 USB Frame Count Register – USBFCR ....................................................................................... 448 USB Device Address Register – USBDEVAR .............................................................................. 449 USB Endpoint 0 Control and Status Register – USBEP0CSR ..................................................... 450 USB Endpoint 0 Interrupt Enable Register – USBEP0IER ........................................................... 451 USB Endpoint 0 Interrupt Status Register – USBEP0ISR ............................................................ 453 USB Endpoint 0 Transfer Count Register – USBEP0TCR ........................................................... 454 USB Endpoint 0 Configuration Register – USBEP0CFGR ........................................................... 455 USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3 ............................... 456 USB Endpoint 1 ~ 3 Interrupt Enable Register – USBEPnIER, n = 1 ~ 3 ..................................... 457 USB Endpoint 1 ~ 3 Interrupt Status Register – USBEPnISR, n = 1 ~ 3 ...................................... 458 USB Endpoint 1 ~ 3 Transfer Count Register – USBEPnTCR, n = 1 ~ 3 ..................................... 459 USB Endpoint 1 ~ 3 Configuration Register – USBEPnCFGR, n = 1 ~ 3 ..................................... 460 USB Endpoint 4 ~ 7 Control and Status Register – USBEPnCSR, n = 4 ~ 7 ............................... 461 USB Endpoint 4 ~ 7 Interrupt Enable Register – USBEPnIER, n = 4 ~ 7 ..................................... 463 USB Endpoint 4 ~ 7 Interrupt Status Register – USBEPnISR, n = 4 ~ 7 ...................................... 464 USB Endpoint 4 ~ 7 Transfer Count Register – USBEPnTCR, n = 4 ~ 7 ..................................... 465 USB Endpoint 4 ~ 7 Configuration Register – USBEPnCFGR, n = 4 ~ 7 ..................................... 466
23 Peripheral Direct Memory Access (PDMA) ..................................................... 467 Introduction ........................................................................................................................ 467 Features ............................................................................................................................. 467 Functional Description ....................................................................................................... 468
AHB Master .................................................................................................................................. 468 PDMA Channel ............................................................................................................................. 468 PDMA Request Mapping .............................................................................................................. 468 Channel Transfer .......................................................................................................................... 469 Channel Priority ............................................................................................................................ 469 Transfer Request .......................................................................................................................... 470 Address Mode ............................................................................................................................... 470 Auto-Reload .................................................................................................................................. 471 Transfer Interrupt .......................................................................................................................... 471
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PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5 .................................................... 473 PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5 .................................. 475 PDMA Channel n Destination Address Register – PDMACHnDADR, n = 0 ~ 5 ........................... 476 PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 5 ......................................... 477 PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n = 0 ~ 5 ......................... 478 PDMA Interrupt Status Register – PDMAISR ............................................................................... 479 PDMA Interrupt Status Clear Register – PDMAISCR ................................................................... 480 PDMA Interrupt Enable Register – PDMAIER .............................................................................. 481
24 Divider (DIV) ...................................................................................................... 483 Introduction ........................................................................................................................ 483 Features ............................................................................................................................. 483 Functional Descriptions ..................................................................................................... 483 Register Map ..................................................................................................................... 484 Register Descriptions ......................................................................................................... 484
Divider Control Register – CR ...................................................................................................... 484 Dividend Data Register – DDR ..................................................................................................... 485 Divisor Data Register – DSR ........................................................................................................ 485 Quotient Data Register – QTR ...................................................................................................... 486 Remainder Data Register – RMR ................................................................................................. 486
25 Cyclic Redundancy Check (CRC) .................................................................... 487 Introduction ........................................................................................................................ 487 Features ............................................................................................................................. 487 Functional Descriptions ..................................................................................................... 488
CRC Computation ......................................................................................................................... 488 Byte and Bit Reversal for CRC Computation ................................................................................ 488 CRC with PDMA ........................................................................................................................... 489
CRC Control Register – CRCCR .................................................................................................. 489 CRC Seed Register – CRCSDR ................................................................................................... 490 CRC Checksum Register – CRCCSR .......................................................................................... 491 CRC Data Register – CRCDR ...................................................................................................... 491
26 Serial LED Interface (SLED) ............................................................................. 492 Introduction ........................................................................................................................ 492 Features ............................................................................................................................. 492 Functional Description ....................................................................................................... 492
Serial Transmission ...................................................................................................................... 492 Transfer Speed ............................................................................................................................. 493 T0, T1 and RESET Codes ............................................................................................................ 494
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FIFO Data Transfer ....................................................................................................................... 495 FIFO Control and BUSY Flag ....................................................................................................... 497 Polling Example ............................................................................................................................ 498 Interrupt Example ......................................................................................................................... 499 PDMA Example ............................................................................................................................. 500 Synchronous Operation ................................................................................................................ 500
SLED Control Register – CR ........................................................................................................ 502 SLED Status Register – SR .......................................................................................................... 503 SLED Clock Divider Register – CDR ............................................................................................ 504 SLED Time Code Register – TCR ................................................................................................ 505 SLED Data Register – DR ............................................................................................................ 506 SLED FIFO Control Register – FCR ............................................................................................. 507
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List of Tables Table 1. Features and Peripheral List ..................................................................................................... 27 Table 2. Document Conventions ............................................................................................................. 29 Table 3. Register Map ............................................................................................................................. 34 Table 4. Flash Memory and Option Byte ................................................................................................. 39 Table 5. Relationship between Wait State Cycle and HCLK ................................................................... 39 Table 6. Booting Modes .......................................................................................................................... 40 Table 7. Option Byte Memory Map ......................................................................................................... 44 Table 8. Access Permission of Protected Main Flash Page .................................................................... 45 Table 9. Access Permission When Security Protection is Enabled ......................................................... 46 Table 10. FMC Register Map .................................................................................................................. 47 Table 11. Operation Mode Definitions ..................................................................................................... 67 Table 12. Enter / Exit Power Saving Modes ............................................................................................ 67 Table 13. Power Status After System Reset ........................................................................................... 68 Table 14. PWRCU Register Map ............................................................................................................ 68 Table 15. Output Divider 2 Value Mapping.............................................................................................. 80 Table 16. Feedback Divider 2 Value Mapping......................................................................................... 81 Table 17. USB PLL Output Divider 2 Value Mapping .............................................................................. 82 Table 18. USB PLL Feedback Divider 2 Value Mapping ......................................................................... 82 Table 19. CKOUT Clock Source ............................................................................................................. 85 Table 20. CKCU Register Map ............................................................................................................... 85 Table 21. RSTCU Register Map ............................................................................................................112 Table 22. AFIO, GPIO and I/O Pad Control Signal True Table.............................................................. 120 Table 23. GPIO Register Map ............................................................................................................... 121 Table 24. AFIO Selection for Peripheral Map Example ......................................................................... 164 Table 25. AFIO Register Map ................................................................................................................ 164 Table 26. Exception Types .................................................................................................................... 169 Table 27. NVIC Register Map ............................................................................................................... 171 Table 28. EXTI Register Map ................................................................................................................ 174 Table 29. Data format in ADCDR [15:0] ................................................................................................ 189 Table 30. A/D Converter Register Map ................................................................................................. 191 Table 31. Counting Direction and Encoding Signals ............................................................................. 223 Table 32. Compare Match Output Setup .............................................................................................. 224 Table 33. GPTM Register Map ............................................................................................................. 234 Table 34. GPTM Internal Trigger Connection ....................................................................................... 239 Table 35. Compare Match Output Setup .............................................................................................. 282 Table 36. PWM Register Map ............................................................................................................... 292 Table 37. PWM Internal Trigger Connection ......................................................................................... 297 Table 38. Compare Match Output Setup .............................................................................................. 338 Table 39. SCTM Register Map .............................................................................................................. 341
Rev. 1.00 17 of 508 May 21, 2020
List of Tables
List of Tables
Table 40. BFTM Register Map .............................................................................................................. 360 Table 41. LSE Startup Mode Operating Current and Startup Time ....................................................... 364 Table 42. RTCOUT Output Mode and Active Level Setting .................................................................. 365 Table 43. RTC Register Map................................................................................................................. 366 Table 44. Watchdog Timer Register Map .............................................................................................. 375 Table 45. Conditions of Holding SCL line .............................................................................................. 391 Table 46. I2C Register Map ................................................................................................................... 393 Table 47. I2C Clock Setting Example .................................................................................................... 402 Table 48. SPI Interface Format Setup ................................................................................................... 410 Table 49. SPI Mode Fault Trigger Conditions ....................................................................................... 415 Table 50. SPI Master Mode SEL Pin Status ......................................................................................... 415 Table 51. SPI Register Map .................................................................................................................. 417 Table 52. Baud Rate Deviation Error Calculation – CK_UART = 40 MHz ............................................ 430 Table 53. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz ............................................ 431 Table 54. Baud Rate Deviation Error Calculation – CK_UART = 60 MHz ............................................ 431 Table 55. UART Register Map .............................................................................................................. 432 Table 56. Endpoint Characteristics ....................................................................................................... 440 Table 57. USB Data Types and Buffer Size .......................................................................................... 440 Table 58. USB Register Map ................................................................................................................ 443 Table 59. Resume Event Detection ...................................................................................................... 445 Table 60. PDMA Channel Assignments ................................................................................................ 469 Table 61. PDMA Address Modes .......................................................................................................... 470 Table 62. PDMA Register Map .............................................................................................................. 472 Table 63. DIV Register Map .................................................................................................................. 484 Table 64. CRC Register Map ................................................................................................................ 489 Table 65. SLED Clock Setting Examples .............................................................................................. 494 Table 66. SLED Register Map .............................................................................................................. 501
Rev. 1.00 18 of 508 May 21, 2020
List of Figures
List of Figures Figure 1. Block Diagram ......................................................................................................................... 28 Figure 2. Cortex®-M0+ Block Diagram .................................................................................................... 31 Figure 3. Bus Architecture ...................................................................................................................... 32 Figure 4. Memory Map ............................................................................................................................ 33 Figure 5. Flash Memory Controller Block Diagram ................................................................................. 37 Figure 6. Flash Memory Map .................................................................................................................. 38 Figure 7. Vector Remapping ................................................................................................................... 40 Figure 8. Page Erase Operation Flowchart ............................................................................................ 41 Figure 9. Mass Erase Operation Flowchart ............................................................................................ 42 Figure 10. Word Programming Operation Flowchart .............................................................................. 43 Figure 11. PWRCU Block Diagram ......................................................................................................... 63 Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 65 Figure 13. CKCU Block Diagram ............................................................................................................ 76 Figure 14. External Crystal, Ceramic and Resonators for HSE .............................................................. 77 Figure 15. HSI Auto Trimming Block Diagram ........................................................................................ 79 Figure 16. PLL Block Diagram ................................................................................................................ 80 Figure 17. USB PLL Block Diagram ........................................................................................................ 81 Figure 18. External Crystal, Ceramic and Resonators for LSE ............................................................. 83 Figure 19. RSTCU Block Diagram .........................................................................................................111 Figure 20. Power-On Reset Sequence ..................................................................................................112 Figure 21. GPIO Block Diagram ............................................................................................................118 Figure 22. AFIO/GPIO Control Signal ................................................................................................... 120 Figure 23. AFIO Block Diagram ............................................................................................................ 162 Figure 24. EXTI Channel Input Selection ............................................................................................. 163 Figure 25. EXTI Block Diagram ............................................................................................................ 172 Figure 26. EXTI Wakeup Event Management ...................................................................................... 173 Figure 27. EXTI Interrupt Debounce Function ...................................................................................... 174 Figure 28. ADC Block Diagram ............................................................................................................. 183 Figure 29. One Shot Conversion Mode ................................................................................................ 186 Figure 30. Continuous Conversion Mode ............................................................................................. 186 Figure 31. Discontinuous Conversion Mode ......................................................................................... 188 Figure 32. GPTM Block Diagram .......................................................................................................... 209 Figure 33. Up-Counting Example ..........................................................................................................211 Figure 34. Down-Counting Example ......................................................................................................211 Figure 35. Center-Aligned Counting Example ...................................................................................... 212 Figure 36. GPTM Clock Source Selection ............................................................................................ 213 Figure 37. Trigger Control Block ........................................................................................................... 214 Figure 38. Slave Controller Diagram ............................................................

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HT32F50343 User Manual - Holtek