124 Lecture 3

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ECE 124AECE 124A

Prof. Kaustav BanerjeeElectrical and Computer Engineering

E-mail: kaustav ece.ucsb.edu

Kaustav BanerjeeLecture 3, ECE 124A, VLSI Principles

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NOR GateNOR Gate

2 PMOS must be in series..


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2 NMOS must be in parallel.

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CMOS 3CMOS 3--input NOR Implementationinput NOR Implementation


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Combinational LogicCombinational Logic

Output state X should always beavoided: static power

Output state Z is of relevance incertain gates such as multiplexers


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Compound GatesCompound Gates Needs 20 transistors.Y= A.B + C.D


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Compound GatesCompound GatesY= A.B + C.D

Pull-down (when is Y =0?)

Pull-up (when is Y=1?)

Need 8 transistors


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Pass TransistorsPass Transistors


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Transmission Gates:Transmission Gates:Pass Transistors in ParallelPass Transistors in Parallel

Both 0 and 1 passed strongly

s

s

Double Rail Logic: both the control input and its complement is required


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Tristate BufferTristate Buffer


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Tristate BufferTristate Buffer


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Transmission Gate as Tristate BufferTransmission Gate as Tristate Buffer

Non-restorin :

input-signalwill slowly

anumber of

stages


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Tristate Buffer as InverterTristate Buffer as Inverter

directly connectedto Vdd or GND


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Multiplexer (MUX)Multiplexer (MUX)Connects one of n inputs to the output.

Used as data selectorsencoders

2:1 MUX

A

BY Y

C

D

21

inputs

1 output

inputs

ss1

s21 Select signal

2 Select signals

Y = As +Bs Y = As1s2 + +Bs1s2 + Cs1s2 + Ds1s2

12n m is a minterm of the


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In general, 2n inputs will have n select signals

0k

kkImY

n control variable andIk is the corresponding

data input

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Multiplexer (MUX)Multiplexer (MUX)

Y = D1.S +D0.S


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NonNon--restoring MUXrestoring MUX

Y = D1.S +D0.S


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Inverting and Restoring MUXInverting and Restoring MUX

S/S = 0/1

= : = = . .


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A 4:1 MUXA 4:1 MUX

Using three 2:1 MUXs


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Static CMOS SummarStatic CMOS Summar In static circuits at every point in time (except when switching)

the out ut is connected to either GND or V via a lowresistance path.

fan-in of n(or n-inputs) requires 2n(nN-type + nP-type) devices

-NMOS sizes (since no conflict between pull-up and pull-downnetworks)

No ath ever exists between Vdd and GND: low static ower

Fully-restored logic: (NMOS passes 0 only and PMOS passes1 only

= , = -down network is ON) for Y=0 (node is fully discharged)


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LatcheLatche

CLK=1: D to Q

CLK=0:Holdsstate of Q

As long asCLK remainshi h: D to Q

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FliFli Flo FloCombines two latches:

ne +ve sens t ve s ave an one ve

sensitive latch (master)Edge Triggered FF or Master-Slave FF Master Slave

CLK=0: D to QM

QM

QM = D

Slave holds previous value

QM

of QCLK=1: master cant sampleinput and holds value of D

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Slave opens and QM=(D) =Q

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124 Lecture 3