12/3/2015 Based on text by S. Mourad "Priciples of Electronic Systems" and M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital,

04/18/23

Based on text by S. Mourad "Priciples of Electronic Systems" and M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal

VLSI Circuits

Digital Testing: Test Pattern Generation

04/18/23 Copyright©2001, Samiha Mourad 2

Outline Types of Tests Deterministic Tests Notations and Basic Operations Design Verification Critical Path D-Algorithm Reconvergent Fanout PODEM Other Algorithms


Deterministic Tests

NP-complete problem Algebraic: Boolean Difference General Fault Objective

Critical PathPseudo Random

AlgorithmicD-Algorithm Roth 1967 IBMPODEM Goel 1981 IBMFAN Fujiwara 1983 Kyoto U.Socrates Schultz 1988 Germany0/1 propagation Rajski 1990


E=1G3

G4

G5

G

6

W/1

U = 0Z

V

H=1

F

G

G1B=0

A=0Justification

Sensitization or Propagation

G2

Implication

C0

Justification

The Basic Operations

W sa1 fault

Critical path tracing

if only one input has controlling value => such input is criticalif all inputs have value c’ =>

all inputs are critical

A signal is critical if its change causes the gate output change


Critical Path

111011

1 01 0

100000

1 1 1

0 0 0

G2

G3

G4

G5

X=0

W=1

U=0

Z=1

Y

H=0

F=0

G=1

G1

A

B=1

G2

G3

G4

G5

X=1

W=1

U

Z=1

Y=1

H=1

F=1

G=0

G1

A=0

B=0

(a)

(b)

Critical signals


critical signals C Out In Out InAND 0 0 0 1 111 start with the OR 1 1 1 0 000 output andNAND 0 1 0 0 111 propagate pathNOR 1 0 1 1 000 towards input

single all


Example: Start with critical 0c at the output and propagate the critical signals backwards

ab

c

g

d

e

h

i

j

k

l

f


Example :

Make it critical by setting c to 1

Faults detected by the input (abde) = 0000 => a1, b1, d1, e1, h0, i0, j0, k0, l0

a b c d e f g h i j k l 0C

1C 1C 1C 1C

0C 1 0C 1 0C 0C 1

ab

c

g

d

e

h

i

j

k

l

f


Example: Find critical paths for q = 0c

ab

cd

ef

gh

i

j

k

l

m

n

o

p q


Example :

a b c d e f g h i j k l m n o p q 0C

0C 0C 0C

1C 0C 1 1C 1C

1C 1C 0 0 0C 0C 0 1C

ab

cd

ef

gh

i

j

k

l

m

n

o

p q

Fault Oriented Algorithms



A Generic TestAlgorithm

Readnetlist

DisplayResults

Generate fault list

Select one fault andgenerate a pattern

Fault simulation

Remove all faults that aredetected by the pattern

Fault list emptyor desired FC

obtained?


Function of NAND Gate

cInput a

0 1 X D

0 1 1 1 1 1

1 1 0 X D

X 1 X X X X

D 1 X 1

1 D X 1 D

D

D

D

D

D

a

b c

D1/0

0/1

D

1

Inpu

t b

D-Algorithm

Use D-algebraActivate fault

• Place a D or D at fault site• Do justification, forward implication and consistency check

for all signals

Repeatedly propagate D-chain toward POs through a gate

• Do justification, forward implication and consistency check for all signals

Backtrack if• A conflict occurs, or• D-frontier becomes a null set

Stop when• D or D at a PO, i.e., test found, or• If search exhausted without a test, then no test possible

Definitions

Justification: Changing inputs of a gate if the present input values do not justify the output value.

Forward implication: Determination of the gate output value, denoted as X, according to the input values.

Consistency check: Verifying that the gate output is justifiable from the values of inputs, which may have changed since the output was determined.

D-frontier: Set of gates whose inputs have a D or D, and the output is X.

Line justification in a fanout-free circuit

Justify (l, val)begin

set l to valif l is a PI then return /* l is a gate (output) */c = controlling value of l i = inversion of l input_val = val iif (input_val = c’)

then for every input j of l Justify (j, input_val) --recursive callelse begin

select one input (j) of lJustify (j, input_val)

end end

1

1

1

0 l

x

0

x

1 l

j

j

Error propagation in a fanout-free circuit

Propagate (l, err)/* err is D or D’ */begin set l to err

if l is PO then returnk = the fanout of lc = controlling value of ki = inversion of kfor every input j of k other than l

Justify (j, c’)Propagate (k, err i)

end

1

err

1

err’ kl=

Definition: Singular Cover

A singular cover defines the least restrictive inputs for a deterministic output value.

Used for:• Line justification: determine gate inputs for specified output.• Forward implication: determine gate output.

a

b c

X

X

0

Examples: XX0 ∩ 110 = 1100XX ∩ 0X1 = 0X1

Definition: D-CubesD-cubes are singular covers with five-valued signals

Used for D-drive (propagation of D through gates) and forward implication.

a

b c

X

D

X

Examples: XDX ∩ 1DD = 1DD0DX ∩ 0D1 = 0D1DDX ∩ DD1 = DD1


Operations

PDCF

Propagation D-cube

Justification

X = D

(b)

(a)

1 1 1

0 11 01 1

D'D

{W,X,F} ={ 1,D,D}

A = 0B = 0

W = 1X = D

F = D

(c)

{W,X,F} ={ 1,D,x}

W = 1 F = xX = D

W = 1 F = 1E = x

W = xE = x

F = 1

set selected inputs to D (D’)set remaining inputs to c’the output is D i (D’ i)

Example: For OR gate with (c=1, i=0) and input D set the remaining inputs to 0 and the output is D

Propagation D-cubes

all inputs to c’ (c) if i = cone input to c (c’) if i’ = c (other don’t care)Example: for AND gate (c=0, i=0) and output equal to D (1/0) use all inputs equal to 1

Primitive D-cubes of fault

for output equal to D (D’) set :

D-Intersection

∩ 0 1 X D

0 0 0

1 1 1

X 0 1 X D

D D D

D

D

D

D

UndefinedState

(conflict)

D


Set Operations

AND 0 1 x D D' OR 0 1 x D D' A A'

0 0 0 0 0 0 0 0 1 x D D’ 0 1

1 0 1 x D D’ 1 1 1 1 1 1 1 0

x 0 x x x x x x 1 x x x x x

D 0 D x D 0 D D 1 x D 1 D D'

D' 0 D’ x 0 D' D' D’ 1 x 1 D' D' D

Testing for single stuck faults


Example : Propagate error in the following circuit

j

h

i

ab

cd

e

f sa0

g


D

j

h

i

ab

cd

e

f sa0

g

11

0x

0

D1

D0


Example : Propagate error in the following circuit


Example : Propagate 6 sa0 fault in the circuit

G1

G2

G3

G4sa0

12

34

7

8

9

5

6

G5


Example : Propagate 6 sa0 fault in the circuit

G1

G2

G3

G4sa0

12

34

7

8

9

5

6

G5

D

0

D’

1

D

0

0

0

X


Example :

G1 G2 G3 G4 G51 2 5 3 4 6 3 5 7 2 6 8 7 8 9X 1 0 X 0 D 0 X 1 0 D D’ 1 D D’1 X 0 0 X D X 0 1 D 0 D’ D 1 D’0 0 1 1 1 D’ 1 1 0 D D D’D D D’singular pdcf singular propagation propagationcover cover D-cube D-cube

G1

G2

G3

G4sa0

12

34

7

8

9

5

6

G5


Example :

Resulting test for 6 sa0 : T = 10x0

1 2 3 4 5 6 7 8 9 branch

X 0 D Y 0 X 0 D D’ Y 0 X 0 D 1 D’ D Y

0 X 0 0 D 1 D’ D N1 0 X 0 0 D 1 D’ D N

D-drive1, select pdcf for 6 sa02, propagate through G43, propagate through G5Consistency4, use singular cover of G35, use singular cover of G1

G1

G2

G3

G4sa0

12

34

7

8

9

5

6

G5

An Example: XOR

a b

a2

a1

b1

b2

c1 c

c2

d

e

f

Find tests for: c sa0c1 sa0c2 sa0

XOR: Test for c sa0

a b

a2

a1

b1

b2

c1 c

c2

d

e

f

Action Operation D-frontier

1. Activate fault c=1 or c=c1=c2=D d, e

2. Justify c=1 0X1, a=a1=a2=0 d, e

3. Forward impl a2=0 0D1, d=1 e

4. Forward imp d=1 1XX , no implication possible e

5. D-drive c2→e D1D, b2=b=b1=1, e=D f

6. Forward impl b1=1 011, consistency checked f

7. D-drive e→f 1DD, f=D PO

8. Stop, test found Test: (a,b) = (0, 1), f = 1

Test-Detect: XOR, Test (0,1)

Determine good circuit signal values.

For each fault• Place a D or D at the fault site• Perform forward implications• Fault is detected if any PO assumes a D or D value

a b

a2

a1

b1

b2

c1 c

c2

d

e

f

0

11 0

1

1

b1

b2

D for c1 sa0

D for c2 sa0

D

D

0D1 (null D-frontier) → c1 sa0 not detected

D1D

1DX ∩ 1DD = 1DD, D at PO →c2 sa0 is detected

XOR: Test for c1 sa0

a b

a2

a1

b1

b2

c1 c

c2

d

e

f

Action Operation D-frontier1. Activate fault c1=1 or c=c2=1, c1=D d2. Justify c=1 0X1, a=a1=a2=0 d3. Forward impl a2=0 0D1, d=1 null4. Back-up, redo step 3 No choice available null 5. Back-up, redo step 2 X01, b=b1=b2=0, a=X, d=X d6. Forward impl b2=0 101, e=1 d7. Forward impl e=1 X1X, no implication possible d8. D-drive c1→d 1DD, a2=a=a1=1,d=D f9. Forward impl a1=1 101, consistency checked f10. Forward impl d=D D1D, f=D PO11. Stop, test found Test: (a,b) = (1, 0), f = 1

An Example

The circuit will be used to illustrate the D-algorithm for faults on three different nodes

an internal node X

a primary input Y

a primary output Z

X/0G2

G3

G4

G5

W = 1

U = 0

Z

Y

HF

G

G1B = 0

A = 0


Node X sa0 Fault 1 Operation Gate A B X Y W U F G H Z

2 Initialization x x x x x x x x x x

3 PDFC G1 0 0 D

4 0 0 D x x x x x x x

5 D-drive G2 D 1 D

6 0 0 D x 1 x D x x x

7 D-drive G3 0 D D’

8 0 0 D x 1 0 D D’ x x

9 D-drive G5 D’ 0 D'

10 0 0 D x 1 0 D D’ 0 D'

11 Justification H = 00

x 0 0

12 0 0 D 0 1 0 D’ 0 D'

13 Justification H = 00

0 x 0

14 0 0 D 0 1 0 D D’ 0 D'

X/0G2

G3

G4

G5

W = 1

U = 0

Z

Y

HF

G

G1B = 0

A = 0


Compact Table 1 Operation Gate A B X Y W U F G H Z


3 PDFC G1 0 0 D x x x x x x x

4 D frontier G2 0 0 D x 1 x D x x x

5 D frontier G3 0 0 D x 1 0 D D’ x x

6 D frontier G5 0 0 D x 1 0 D D’ 0 D'

7 Justification H = 0 0 0 D x 1 0 D’ 0 D'

8 Justification H = 0 0 0 D 0 1 0 D D’ 0 D'


Input Y sa1 Fault

1 Operation Gate A B X Y W U F G H Z


3 PDCF Y x x x D’ x x x x x x

4 D frontier G4 x x x D’ x x 1 x D’ x

5 Implication F=1 x x x D’ x x 1 0 D’ x

6 D frontier G5 x x x D’ x x 1 0 D’ D’

7 Justification F =1 x x 1 D’ 1 x 0 D’ D'

8 Justification X=1 0 0 1 D’ 1 x 0 D’ D'

X/0

G2

G3

G4

G5

W = 1

U = 0

Z

Y

HF

G

G1B = 0

A = 0


Output Z sa0 Fault

1 Operation Gate A B X Y W U F G H Z

2 PDCF G5 x x x x x x x 1 x D

3 Justification G x x x x x 0 0 1 x D

4 Justification F x x x x 0 0 0 1 x D

5 Justification F x x 0 x x 0 0 1 x D

6 Justification X x 1 0 x x 0 0 1 x D

X/0

G2

G3

G4

G5

W = 1

U = 0

Z

Y

HF

G

G1B = 0

A = 0

Multiple-Valued AlgebrasMultiple-Valued AlgebrasSymbol

DD01X

G0G1F0F1

AlternativeRepresentation

1/00/10/01/1X/X0/X1/XX/0X/1

FaultyCircuit

0101XXX01

Fault-freecircuit

1001X01XX

Roth’sAlgebra

Muth’sAdditions

Complexity of D-Algorithm

Signal values on all lines (PIs and internal lines) are manipulated using 5-valued algebra.

Worst-case combinations of signals that may be tried is 5#lines

• For XOR circuit, 512 = 244,140,625.

Podem: A reduced-complexity ATPG algorithm• Recognizes that internal signals depend on PIs.• Only PIs are independent variables and should be

manipulated.• Because faults are internal, a PI can assume only 3

values (0, 1, X).• Worst-case combinations = 3#PI; for XOR circuit, 32 = 8.

Podem: Path oriented decision makingStep 1: Define an objective (fault activation, D-drive, or line justification)Step 2: Backtrace from site of objective to PIs (use testability measure guidance) to determine a value for a PIStep 3: Simulate logic with new PI value

• If objective not accomplished but is possible, then continue backtrace to another PI (step 2)

• If objective accomplished and test not found, then define new objective (step 1)

• If objective becomes impossible, try alternative backtrace (step 2)

Use X-PATH-CHECK to test whether D-frontier still there – a path of X’s from a D-frontier to a PO must exist.

Podem Algorithm

XOR Example Again

(1,1)6

(1,1)6

(3,2)5

(4,2)3

(4,2)3

(5,5)0

6

6

5

5

Compute SCOAP testability measures: (CC0,CC1)CO

7

7

Podem: Objective and Backtrace

(1,1)6

(1,1)6

(3,2)5

(4,2)3

(4,2)3

(5,5)0

6

6

5

5

sa0

1. Objective 1: set fault site to 1

0

2&3. Backtrace to a PI and simulate

1

1

D

X-path check fails→ Back up:Erase effects of steps 2&3Try alternative backtrace

7

7

Podem: Back up

(1,1)6

(1,1)6

(3,2)5

(4,2)3

(4,2)3

(5,5)0

6

6

5

5

sa0

1. Objective 1: set fault site to 1

0

4&5. Alt. backtrace to a PIand simulate

1

1

D

X-path check: OKObjective 1 achieved

X-path

7

7

Podem: D-Drive

(1,1)6

(1,1)6

(3,2)5

(4,2)3

(4,2)3

(5,5)0

6

6

5

5

sa0

4. Objective 2: D-drive, set line to 1

1

5. Backtrace to a PI and simulate

1

1

D

1 D

D0

D at PO→Test found

7

7

Another Podem Example

1. Objective “0”2. Backtrace “A=0”3. Logic simulation for A=0

(9, 2)

S-a-1

0

4. Objective possible but not accomplished yet

Podem Example (Cont.)

1. Objective “0”5. Backtrace “B=0”6. Logic simulation for A=0, B=0


(9, 2)

S-a-1

0

00

0


9. Logic simulation for E=0


(9, 2)0

S-a-1

1. Objective “0”

0

8. Backtrace “E=0”

00

0

0


11. Backtrace “D=0”

12. Logic simulation for D=0

13. Objective accomplished

(9, 2)

S-a-1

1. Objective “0”

0

00

0

0

0

0

0


PODEM Flowchart

START

Assign a binary value to anunassigned primary input

Determine implications of allprimary inputs

Is there a D or a Don any primary ouput?

Test possiblewith the additional assigned primary

inputs?

Is there anuntried combination of

values on assigned primary inputs?

Set untried combination ofvalues on assigned primary

inputs

Test has beengenerated

yes

no

no

maybe

no

yes

No PatternExists


PODEM Example E sa1 Fault

U

W

X

0

1

00 1

1

1. Assign x to all inputs

2. Assigning 0 to the primary input, U, causes E = 1; hence, this choice does not further our goal and it is discarded. Then U =1

3. We proceed with W = 1. The implication of this value is not furthering the objective nor is it blocking it.

4. X = 1 is rejected and X=0 is selected.

5. This Implies F=0, H=0 and we can propagate D’ on G, then D on the primary output, Z.

=D’

G2

G3

G1

G4

G5X

W

U

Z

YH

F

G

E=D

=D


PODEM Example G sa1 Fault

G2

G3

G1

G4

G5

XW

Z

YF

G

EV H

I

U

W

0

1

0

XV 1

1E1

1. Assign x to all inputs

2. Assigning 0 to the primary input, W, causes G = 1; hence, this choice is discarded. Then W =1 which causes F=0.

3. We proceed with X = 1. The implication of this value is not furthering the objective nor is it blocking it.

4. Similarly V=1 is selected.

5. E=1 is rejected, so E=0 which implies I=1 and we can propagate D on the primary output, Z.

=D’

=D


Other Algorithms

FANA variation of PODEM with better heuristic to prune the search tree for backtracking

SocratesA variation of FAN using testability analysis to cut down on backtracking


Comparing FAN to PODEM

Computing Time Average Backtracks %age of Faults Aborted

Circuit PODEM FAN PODEM FAN PODEM FAN

1 1.3 1 4.9 1.2 0.32 0.37

2 3.6 1 42.3 15.2 2.26 3.13

3 5.6 1 61.9 0.6 2.42 4.00

4 1.9 1 5.0 0.2 0.99 1.10

5 4.8 1 53.0 23.2 0.82 1.02

Multi fault detection with 01 sequence (Dr. Janusz Rajski)

1, Drive backward from output 01 to establish 2 test vectors

2, Propagate forward (with fault effects)

3, Analyze the results (backward)

Rajski’s method

Example : ABCE = (00, 11, 01, 11)

G701,11,00

E=11,00

A=00,11

B’=00,11

C=01,00,11

B=11,00

G2=01,00,11

G3=00,11

G4=10,11,00

G5=01,11,00

G1=01,00,11

G8=00,11

G6=00,10,11

If single fault

Rajski’s method

Example : ABCE = (00, 11, 00, 10)

G7=01

E=10,11

A=00

B’=00,11

C=00

B=11

G1=00

G2=00

G3=01,00,11

G4=11,00

G6=01,00

G8=01,00,11

G5=00

Rajski’s method

Example : ABCE = (10, 00, 00, xx)

G7=01

E=xx

A=10

B’=11

C=00

B=00,11

G1=00

G2=10

G3=11

G4=01

G5=00,10

G6=01

Rajski’s method

Example :multiple faultscoverage

sa1 sa0A x 3B 3 xC x xE 2 xG1 x xG2 x xG3 x 2G4 3 2G5 x xG6 x 2G7 x xG8 x 2

Rajski’s method

Example :

01,11,00

a

b

c

d

e

f

Z

g

h

00,11

01,11,00

11,00

01,00,11

00,1101,11,00

01,11,00

00,11

11,00

01,11,0000,11

h1= 01,11,00

h2= 01,11,00

i

jk

001010

000010abcdef

Multiple faults

sa0 sa1a xb xc x xd xe xf xg xh x xh1 xh2 xi xj xk x xZ x x

Rajski’s method

01,00,11

a

b

c

d

e

f

Z

g

h

10,00,11

11,00

01,00,11

00,11

11,0001,00,11

11,00

00,11

11,00

01,00,1100,11

h1= 11,00

h2= 11,00

i

jk

if single fault

000110

100110abcdef

sa0 sa1a 2 xb xc x xd xe xf xg x 2h x xh1 xh2 xi x 2j xk x xZ x x

Example :

Rajski’s method

G701,11,00

Example : ABCE = (00, 11, 01, 11) single fault test – critical signals areunderlined

E=11,00

A=00,11

B’=00,11

C=01,00,11

B=11,00

G2=01,00,11

G3=00,11

G4=10,11,00

G5=01,11,00

G1=01,00,11

G8=00,11

G6=00,10,11

Example :UsingRajski’smethod

01,00,11

10,00,11

00,11

00,11

10,00,11

01,00,11

00,11

11,00

00,11

00,11

00,11

00,11

11,00

11,00

11,00

11

00,11

Example :UsingRajski’smethod

Documents

12/3/2015 Based on text by S. Mourad "Priciples of Electronic Systems" and M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital,