28
(12) United States Patent Ludwig US008396701B2 US 8,396,701 B2 Mar. 12, 2013 (10) Patent N0.: (45) Date of Patent: (54) SOFTWARE SYSTEMS FOR DEVELOPMENT, CONTROL, PROGRAMMING, SIMULATION, AND EMULATION OF FIXED AND RECONFIGURABLE LAB-ON-A-CHIP DEVICES (76) Inventor: Lester F. Ludwig, Redwood Shores, CA (Us) ( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 857 days. (21) Appl.No.: 12/328,726 (22) Filed: Dec. 4, 2008 (65) Prior Publication Data US 2009/0150130 A1 Jun. 11,2009 Related US. Application Data (60) Provisional application No. 61/005,460, ?led on Dec. 4, 2007. (51) Int. Cl. G06F 17/50 (2006.01) (52) US. Cl. ............................... .. 703/13; 703/1; 703/14 (58) Field of Classi?cation Search .............. .. 703/1, 13, 703/ 14 See application ?le for complete search history. (56) References Cited U.S. PATENT DOCUMENTS 2002/0100714 A1* 8/2002 Staats ........................... .. 210/85 2008/0223721 A1 9/2008 Cohen et al. 2009/0121476 A1 5/2009 Malito et al. OTHER PUBLICATIONS SystemC Version 2.0, User’s Guide. Update for SystemC 2.0.1 Copy right 1996-2002.* Fixed LoC Design 1 7 Fixed LoC Design n “Micro?uidic lab-on-a-chip systems based on polymers-fabrication and application”, Guber, et al. Chemical Engineering Journal 101. 2004* “Lab-on-a-chip: A Revolution in Biological and Medical Sciences”, Figeys, et al. Analytical Chemistry, May 1, 2000.* “Disposable Smart Lab on a Chip for Point-of-Care Clinical Diag nostics”, Ahn, et al. 2004 IEEE.* “Lab on a Chip for Live-Cell Manipulation”, Medoro, et al. 2007 IEEE.* “System-Oriented Modeling and Simulation of Bio?uidic Lab-on-a Chip”, Wang et al. 2005 IEEE.* “Automated Design of Pin-Constrained Digital Micro?uidic Arrays for Lab-on-a-Chip Applications”, Hwang, et al. Jul. 24-28, 2006.* “Composable Behavioral Models and Schematic-Based Simulation of Electrokinetic Lab-on-a-Chip Systems”, Wang, et al. Feb. 2006.* Uni?ed High-Level Synthesis and Module Placement for Defect Tolerant Micro?uidic Biochips*. Fei Su and Krishnendu Chakrabarty, 2005, available at http://people.ee.dul<e.edu/~krish/ p825.pdf. Heterogeneous System-Level Speci?cation in Systemc, Fernando Herrera, Pablo Sanchez and Eugenio Villar Advances in Design and Speci?cation Languages for SoCs, Pierre Boulet, 2006, Abstract only. (Continued) Primary Examiner * Omar Fernandez Rivas Assistant Examiner * Nithya J Moll (74) Attorney, Agent, or Firm * Procopio, Cory, Hargreaves & Savitch LLP (57) ABSTRACT A software system for development, control, programming, simulation, and emulation of ?xed, software-con?gurable, software-recon?gurable, and software-controlled Lab-on-a chip (“LoC”) devices. Files may be used to specify LoC con?gurations for models, emulation, and fabrication, and scripts can be implemented to control numerical simulations as well as physical emulations of modeled LoC devices. Other features include a control software design tool, fabri cation design systems, and an authoring/editing tool for speci?cation ?les. In some cases, an active data visualization system provides visualizations of real-time data generated by past and current simulations and emulations. 20 Claims, 16 Drawing Sheets Recon?gurable Design Cycles Reconfigurable Emulation Environment . _ _ _ _ _ _ _ _ _ _ _ , | | | | | | | I | LOG I | | | | | | | | | |

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Page 1: (12) United States Patent Ludwig (45) Date of Patent

(12) United States Patent Ludwig

US008396701B2

US 8,396,701 B2 Mar. 12, 2013

(10) Patent N0.: (45) Date of Patent:

(54) SOFTWARE SYSTEMS FOR DEVELOPMENT, CONTROL, PROGRAMMING, SIMULATION, AND EMULATION OF FIXED AND RECONFIGURABLE LAB-ON-A-CHIP DEVICES

(76) Inventor: Lester F. Ludwig, Redwood Shores, CA (Us)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 857 days.

(21) Appl.No.: 12/328,726

(22) Filed: Dec. 4, 2008

(65) Prior Publication Data

US 2009/0150130 A1 Jun. 11,2009

Related US. Application Data

(60) Provisional application No. 61/005,460, ?led on Dec. 4, 2007.

(51) Int. Cl. G06F 17/50 (2006.01)

(52) US. Cl. ............................... .. 703/13; 703/1; 703/14

(58) Field of Classi?cation Search .............. .. 703/1, 13, 703/ 14

See application ?le for complete search history.

(56) References Cited

U.S. PATENT DOCUMENTS

2002/0100714 A1* 8/2002 Staats ........................... .. 210/85

2008/0223721 A1 9/2008 Cohen et al. 2009/0121476 A1 5/2009 Malito et al.

OTHER PUBLICATIONS

SystemC Version 2.0, User’s Guide. Update for SystemC 2.0.1 Copy right 1996-2002.*

Fixed LoC Design 1

7 Fixed LoC Design n

“Micro?uidic lab-on-a-chip systems based on polymers-fabrication and application”, Guber, et al. Chemical Engineering Journal 101. 2004* “Lab-on-a-chip: A Revolution in Biological and Medical Sciences”, Figeys, et al. Analytical Chemistry, May 1, 2000.* “Disposable Smart Lab on a Chip for Point-of-Care Clinical Diag nostics”, Ahn, et al. 2004 IEEE.* “Lab on a Chip for Live-Cell Manipulation”, Medoro, et al. 2007 IEEE.* “System-Oriented Modeling and Simulation of Bio?uidic Lab-on-a Chip”, Wang et al. 2005 IEEE.* “Automated Design of Pin-Constrained Digital Micro?uidic Arrays for Lab-on-a-Chip Applications”, Hwang, et al. Jul. 24-28, 2006.* “Composable Behavioral Models and Schematic-Based Simulation of Electrokinetic Lab-on-a-Chip Systems”, Wang, et al. Feb. 2006.* Uni?ed High-Level Synthesis and Module Placement for Defect Tolerant Micro?uidic Biochips*. Fei Su and Krishnendu Chakrabarty, 2005, available at http://people.ee.dul<e.edu/~krish/ p825.pdf. Heterogeneous System-Level Speci?cation in Systemc, Fernando Herrera, Pablo Sanchez and Eugenio Villar Advances in Design and Speci?cation Languages for SoCs, Pierre Boulet, 2006, Abstract only.

(Continued)

Primary Examiner * Omar Fernandez Rivas

Assistant Examiner * Nithya J Moll

(74) Attorney, Agent, or Firm * Procopio, Cory, Hargreaves & Savitch LLP

(57) ABSTRACT

A software system for development, control, programming, simulation, and emulation of ?xed, software-con?gurable, software-recon?gurable, and software-controlled Lab-on-a chip (“LoC”) devices. Files may be used to specify LoC con?gurations for models, emulation, and fabrication, and scripts can be implemented to control numerical simulations as well as physical emulations of modeled LoC devices. Other features include a control software design tool, fabri cation design systems, and an authoring/editing tool for speci?cation ?les. In some cases, an active data visualization system provides visualizations of real-time data generated by past and current simulations and emulations.

20 Claims, 16 Drawing Sheets

Recon?gurable Design Cycles

Reconfigurable Emulation Environment . _ _ _ _ _ _ _ _ _ _ _ ,

|

|

| | | |

|

I |

LOG I | |

| | |

|

| | | |

Page 2: (12) United States Patent Ludwig (45) Date of Patent

US 8,396,701 B2 Page 2

OTHER PUBLICATIONS

Development of a Micro?uidic Unit for Sequencing Fluid Samples for Composition Analysis, V. Tesar*, J. R. Tippetts, Y. Y. LOWand R. W. K. Allen, Institution of Chemical Engineers, Trans IChemE, Part A, Jun. 2004, Chemical Engineering Research and Design, 82(A6): 708-718, available at http://eprints.whiterose.ac.uld468/1/tesarv2. pdf. A Toy Model of Chemical Reaction Networks, Gil Benk 0, Nov. 2002, available at http://www.tbi.univie.ac.at/papers/Abstracts/gili dipl.pdf. Electric Power Generated from Waste Heat, Translation of the AIST press released on May 31, 2005, available at http://www.aist.go.jp/ aistie/latestiresearch/2005/20050617/20050617.html, accessed on Jun. 12,2006. AquaCore: A Programmable Architecture for Micro?uidics, Ahmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar Steven Wereley:, and Stephen C. Jacobsoni, 2007, available at https://engineering. purdue.edu/ploc/publications/isca07. pdf. Uni?ed High-Level Synthesis and Module Placement for Defect Tolerant Micro?uidic Biochips*. Fei Su and Krishnendu Chakrabarty, 2005, available at http://people.ee.duke.edu/~krish/ p825.pdf. Architectural-Level Synthesis of Digital Micro?uidics-Based Biochips, Fei Su and Krishnendu Chakrabarty, Published in Proc. IEEE International Conference on CAD, pp. 223-228, 2004, avail able at http://www.sigda.org/daforum/abs/44iattachment.pdf. A Scheduling and Routing Algorithm for Digital Micro?uidic Ring Layouts with Bus-phase Addressing. Megha Gupta and Srinivas Akella, Proceedings of the 2007 IEEE/RSJ International Conference on Intelligent Robots and Systems San Diego, CA, USA, Oct. 29-Nov. 2, 2007, available at http://www.cs.rpi.edu/twiki/pub/ RoboticsWeb/LabPublications/GAiros07.pdf. Digital micro?uidics: is a true lab-on-a-chip possible?, Micro?uidics and Nano?uidics, vol. 3, No. 3 / Jun. 2007. Digital micro?uidic design and optimization of classic and new ?u idic functions for lab on a chip systems, Micro?uidics and Nano?uid ics, vol. 4, No. 3 /Mar. 2008. Arrays for Digital Signal Processing Functions: Fault Tolerance and Functional Recon?guration, A. Antola, R. Negrini, M.G. Sami andN. Scarabottolo, Recon?gurable Massively Parallel Computers, Hungwen Li and Quentin F. Stout, pp. 170-222, 1991. Motivation: Mission-critical Computing, Problems and Solutions, Svetlana P. Kartashev and Steven I. Kartashev, Designing and Pro gramming Modern Computer Systems: Supercomputing Systems : Recon?gurable Architectures, pp. 1-17, 1989. Nonrobotic Automated Workstations for Solution Phase Synthesis, Laboratory Automation in the Chemical Industries, David G. Cork and Tohru Sugawara, pp. 41-72, 2002. Heterogeneous System-Level Speci?cation in Systemc, Fernando Herrera, Pablo Sanchez and Eugenio Villar Advances in Design and Speci?cation Languages for SoCs, Pierre Boulet, pp. 199-206, 2006. Introduction to Recon?gurable Hardware, Nikolaos Voros and Konstantinos Masselos, System Level Design of Recon?gurable Sys tems-on-Chip, pp. 15-26, 2005. Design Flow for Recon?gurable Systems-on-Chip, Nikolaos Voros and Konstantinos Masselos, System Level Design of Recon?gurable Systems-on-Chip, pp. 107-131, 2005. SystemC Based Approach, Yang Qu and Kari Tiensyrja, System Level Design of Recon?gurable Systems-on-Chip, pp. 87-105, 2005. Synthesis of Multiplexed Bio?uidic Microchips, Anton Pfeiffer, Tamal Mukherjee and Steinar Hauan, Design Automation Methods and Tools for Micro?uidics-Based Biochips, pp. 271-300, 2006. Modeling and Controlling Parallel Tasks in Droplet-Based Micro?uidic Systems, Karl Bohringer, Design Automation Methods and Tools for Micro?uidics-Based Biochips, pp. 301-327, 2006. Performance Characterization of a Recon?gurable Planar Array Digital Micro?uidic System, Eric Griffth, Srinivas Akella and Mark Goldberg, Design Automation Methods and Tools for Micro?uidics Based Biochips, pp. 329-356, 2006. Fluidic Valves for Variable-Con?guration Gas Treatment, V.Tesar, Institution of Chemical Engineers, Trans IChemE, Part A, Sep. 2005,

Chemical Engineering Research and Design, 83(A9): 1111-1121, available at http://eprints.whiterose.ac.uk/758/1/tesarv6.pdf. Development of a Micro?uidic Unit for Sequencing Fluid Samples for Composition Analysis, V. Tesar*, J. R. Tippetts, Y. Y LOWand R. W. K. Allen, Institution of Chemical Engineers, Trans IChemE, Part A, Jun. 2004, Chemical Engineering Research and Design, 82(A6): 708-718, available at http://eprints.whiterose.ac.uk/468/1/tesarv2. pdf. Sampling by Fluidics and Micro?uidics, V. Tesar, Acta Polytechnica vol. 42 No. 2/2002. Lectures on Chemical Reaction Networks: Introduction, Martin Feinberg,1979, available at http://www.che.eng.ohio-state.edu/ ~feinberg/LecturesOnReactionNetworks/images/FeinbergLecture1 .

pdf, accessed on Jun. 12, 2006. Lectures 2: Reaction Networks, Kinetics, and the Induced Differen tial Equations, Martin Feinberg,1979, available at http://www.che. eng.ohio-state.edu/~feinberg/LecturesOnReactionNetworks/im ages/FeinbergLecture2.pdf, accessed on Jun. 12, 2006. Lectures 3: Two Theorems, Martin Feinberg, 1979, available at http:// www.che.eng.ohio-state.edu/~feinberg/LecturesOnReaction Networks/images/FeinbergLecture3.pdf, accessed on Jun. 12, 2006. Lectures 4: Some De?nitions and Propositions, Martin Feinberg,1979, available at http://www.che.eng.ohio-state.edu/ ~feinberg/LecturesOnReactionNetworks/images/FeinbergLecture4. pdf, accessed on Jun. 12, 2006. Lectures 5: Proof of the De?ciency Zero Theorem, Martin Feinberg,1979, available at http://www.che.eng.ohio-state.edu/ ~feinberg/LecturesOnReactionNetworks/images/FeinbergLecture5. pdf, accessed on Jun. 12, 2006. A Toy Model of Chemical Reaction Networks, Gil Benko, Nov. 2002, available at http://www.tbi.univie.ac.at/papers/Abstracts/gilidipl. pdf. Development of a MEMS Microvalve Array for Fluid Flow Control, NelsimarVandelli, Donald Wroblewski, Margo Velonis, and Thomas Bifano, Journal of Microelectromechanical Systems, vol. 7, No. 4, Dec. 1998, available at http://sws1.bu.edu/bifano/PDFi?les/23i Flow.pdf. The Chemical Reaction Network Toolbox: Downloads and Instruc tions, Martin Feinberg, available at http://www.chbmeng.ohio-state. edu/~feinberg/crnt/, accessed on Jun. 12, 2006. Device could convert waste heat into electricity, Elizabeth A. Thomson, MIT Tech Talk, Dec. 5, 2001, available at http://web.mit. edu/newsof?ce/2001/electricity-1205.html, accessed on Jun. 12, 2006. Development of a Rapid-Response Flow-Control System Using MEMS Microvalve Arrays, John Collier, Donald Wroblewski, and Thomas Bifano, Journal of Microelectromechanical Systems, vol. 13, No. 6, Dec. 2004, available at http://128.197.153.21/tgb/PDFL ?les/Valves.pdf. A Novel Pressure Balanced Micro?uidic Valve, J. M. Quero, A. Luque, L. G. Franquelo, Proc. ISCAS 2002, May 26-29, available at http ://woody.us . es/~aluque/doc/pressureibalancedimicrovalve. pdf. Fabrication of Polysilicon Micro Valve Array, Jermaine White, 22rd Annual Microelectronic Engineering Conference, May 2004, avail able at http://www.rit.edu/~w-ue/ameccontent/17iJWhite.pdf. Parker R-maxTM Stream Switching System, Parker Instrumentation, Catalog 4140-R, Revised, Jun. 2002, available at http://www.plesner. as/mod/products/upload/4140-R.pdf. Fast Switching Valves: Ultra Fast and Highly Repeatable, FESTO Corp, Info 96 207 US, Jun. 2005, available at http://www.zycon.com/ Literature/219948/75280/Info207iFastSwitchingV.pdf. Electric Power Generated from Waste Heat, Translation of the AIST press released on May 31, 2005, available at http://www.aistgo.jp/ aistie/latestiresearch/2005/20050617/20050617.html, accessed on Jun. 12,2006. Flow Selection Valves: Series 105TValve, Bio-Chem Fluidics, 2010, available at https://www.biochem?uidics.com/cart/store/comersusi listOneCategory.asp?idCategory:393, accessed on Jun. 12, 2006. Flow Selection Valves: Series 080TValve, Bio-Chem Fluidics, 2010, available at https://www.biochem?uidics.com/cart/store/comersusi listOneCategory.asp?idCategory:392, accessed on Jun. 12, 2006.

Page 3: (12) United States Patent Ludwig (45) Date of Patent

US 8,396,701 B2 Page 3

Cheminert® Valves for Flow Injection Analysis, FIAlab Instruments, 2010, available at http://WWW.?oWinjection.com/valves.html, accessed on Jun. 12, 2006. Solenoid valves and eletric valve, Peter Paul Electronics Co., Inc., 2010, available at http://WWW.peterpaul.com/whatsinewidisplay2. php4?catiid:6, accessed on Jun. 12, 2006. Gems Predyne Pneumatic Solenoid Valves & Miniature Solenoid Valves: general-purpose-valves, Gems Sensors & Controls, 2010, available at http://WWW.gemssensors.com/Search.aspx?q:general purpose-valves, accessed on Jun. 12, 2006. Gems Predyne Pneumatic Solenoid Valves & Miniature Solenoid Valves: isolation-valves, Gems Sensors & Controls, 2010, available at http://WWW.gemssensors.com/Search.aspx?q:isolation-valves, accessed on Jun. 12, 2006.

1200 Series Valve Solutions, Agilent Technologies, 2000-2010, available at http://WWW.chem.agilent.com/en-us/products/instru ments/lc/l200seriesvalvesolutions/pages/default.aspx, accessed on Jun. 12, 2006. Valve matrix takes squeeze out of juice production, Prepared Foods, Oct. 1997, available at http://?ndarticles.com/p/aIticles/miim3289/ isinllivl66/aii20224l64/, accessed on Jun. 12, 2006. Valve Matrix Operating Instructions, GEA Process Equipment Divi sion, 2003, available at http://WWW.tuchenhagencom/tuchenhagen/ cmsdoc.nsf/Webdoc/nd1<W73 galZ. Solenoid Valve Manifolds, Precision Dynamics, 2004, exercised on Jun. 12, 2006 at http://WWW.predyne.com/manifolshtml, accessed on Jun. 12,2006.

* cited by examiner

Page 4: (12) United States Patent Ludwig (45) Date of Patent

US. Patent Mar. 12, 2013 Sheet 1 0f 16 US 8,396,701 B2

Actively Controlled

LoC

Purely Passive LoC

La rg e-scale Moderate

Complexity Simple

Complexity Figure 1

Fixed LoC Design n

Fixed LoC Design 1

Reconfigurable Emulation Environment - - -

Figure 2a

:' l

l

l

l l

Reconfigurable LOC 856 298G

Reconfigurable Emulation Environment- _ _ _ _ _ _ _ _ _ _ _

Fixed LoC Design n

? Fixed LoC Design 1

O

?

Figure 2b

Page 5: (12) United States Patent Ludwig (45) Date of Patent

Mar. 12, 2013 Sheet 2 0f 16 US 8,396,701 B2

- - Sufficient market size

to justify manufacturing costs

- — Sufficient market size

to justify creditable R&D costs

Candidate Lab-on-a-Chip Applications

Type 3 Type 5 . Reconfigurable Reconfigurable

Lab'on'a'ch'p Type 2 Lab-on-a-Chip Type 4 Lab-on-a-Chip Reconfigurable Reconfigurable Lab'on'a'clMLab-on-a-Chw

_ _ Sufficient market size

Type 1 Reconfigurable

36 “9:22

US. Patent

Figure 3a

9 S 16.2 19. S S O m a c ygmeww Tun at. ..&.H mSR Um tiWm .] nob mm .mtm

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_ _ Sufficient market size

to justify manufacturing costs

Sufficient market size to justify creditable R&D costs

Type 5 Reconfigurable

Candidate Lab-on-a-Chip Applications

Type 3 Reconfigurable Lab-on-a-Chip Type 4 Lab-on-a-Chip

Reconfigurable Lab-on-a-Chip Lab-on-a-Chlp Reconfigurable

Figure 3b

Type 1 Reconfigurable Lab-on-a-Chip Type 2

Figure 3c

Page 6: (12) United States Patent Ludwig (45) Date of Patent

US. Patent Mar. 12, 2013 Sheet 3 0f 16 US 8,396,701 B2

/ /Recon?gurab\le / ’ I _ \ \

' LOCTYPQB Li Rizeigyzzaé'e ‘; / I ’/ \_\\ \ \ / , / \ \ \ I /

_ (' Recon?gurable?- - '

\ LoC Type 4 /’ \ , \ ____’ \__ ’,

\

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\ /

/

Figure 3d

// Recon?gurable \\ /’ \\ LOC Type 3 \ I Recon?gurable

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‘\ LoC Type 1 I LOC Type 2 _ _ Refocnfigura‘ble “ ' T \ \ o ype

Figure 3e

/ .

/ Recon?gurable ‘ ,/ Reconfigurable \ \ LoC Type 5 I‘

LoC Type 3

Reconfigurable LoC Type 1 LoC Type 4

Reconfigurable LoC Type 6

Figure 3f

/ Reconfigurable Reconfigurable\\l LOC Type 5 LoC Type 3

I

Reconfigurabl r LoC Type 1 Reconfigurable

LoC Type 7

Reconfigurable LoC Type 8

Figure 39

Page 7: (12) United States Patent Ludwig (45) Date of Patent
Page 8: (12) United States Patent Ludwig (45) Date of Patent

US. Patent Mar. 12, 2013 Sheet 5 0f 16 US 8,396,701 B2

Imagined \ \ \ \ \

Realized

Figure 5

Page 9: (12) United States Patent Ludwig (45) Date of Patent

US. Patent Mar. 12, 2013 Sheet 6 0f 16 US 8,396,701 B2

Control Software _> .

Desrgn Tool Simulated 4 Data Reporting + > Numerical

0th S > S|mulat|on

er Ource Operational Actlve- Data Language Script / Vlsuahzatlon

Physical Emulation

Specification I > Measured Language File Data Reporting

¢ h' | —> . b Gaga/O5? Graphrcal Authoring/Editing Rendering

Tool T Fabrication . Preliminaries ‘—> Fabrication Fabrication

<- — - Layout > Specification

Figure 6a

Control Software —> - <- - — - — — — — — — — — — -.

Desrgn Tool : Simulated ‘ | Data Reporting

* > Numerical | S|mulat|on I

other Source Operational 'F_ _> Active Data Language Scrrpt | V|sual|zat|on

t Physical : ' l

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Tool |

‘ Fabrication : p Preliminaries ‘ ’ Fabrication ' Fabrication

<- — — Layout > Specification

Figure 6b

Page 10: (12) United States Patent Ludwig (45) Date of Patent

US. Patent Mar. 12, 2013 Sheet 7 0f 16 US 8,396,701 B2

|_ — — — — — — _| r _ _ _ _ _ _ __1

l l

I Mode|$ Visualization I I I l l

. . . A I Table-Scale : Actual-Scale : Dyn'\a"I?I§§"|{}%§e|s I LoC Process I Physical LoC I S M dl Emulation I System I ensor 0 es - Simulation I ' '

Reaction Models —> I I I Physics Models —> I I _ _ _ _ _ _ _ HI

|_ _ _ _ _ _ _ J Hardware

Driver Driver Driver

Configuration Process Control

Software . _ + Scrlpts. C) . . . C)

Figure 7a

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l l

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Reactlon Models—> I I

I Physics Models—> I I _ _ _ _ _ _ __I

|_ _ _ _ _ J Hardware

Driver Driver Driver

l l

Configuration Process Control Control

Software . _ ‘ Scrlpts. (I) . . . C)

Figure 7b

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US. Patent Mar. 12, 2013 Sheet 8 0f 16 US 8,396,701 B2

l% (“2-way”) on/off valve (SPST)

(“3-way”) SPDT valve

Storage or venction volume

i Point-to-point conduit

(gangable) N-port Joint

? l

g

Figure 8a

Fill ent F||| Vent F||| Fill ent

Clean

w Out 1

Out 2

Out 3

Out 4

Figure 8b

Page 12: (12) United States Patent Ludwig (45) Date of Patent

US. Patent Mar. 12, 2013 Sheet 9 0f 16 US 8,396,701 B2

Out 1

Out 2

1 | | | l l l l l | | l ll

3

t 4 m m

0

Drain

Page 13: (12) United States Patent Ludwig (45) Date of Patent
Page 14: (12) United States Patent Ludwig (45) Date of Patent

US. Patent Mar. 12, 2013 Sheet 11 0f 16 US 8,396,701 B2

Figure 12

Page 15: (12) United States Patent Ludwig (45) Date of Patent

US. Patent Mar. 12, 2013 Sheet 12 0f 16 US 8,396,701 B2

Higher Level Control -—> Actual, Emulated, or Simulated System

Figure 13

l‘ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ‘l

| Multi-Threaded Operation | |_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ l_ _ _ _l

i i | Sequential Procedures v

I‘ _ _ _ _ _ _ _ ‘l

<- — -| Resource Allocation |

v r L ————— — — J

Combinations of Elements

0 O O

V V Elements

Figure 14

Higher Level Control

L I‘ _ _ _ _ ‘l

Procedural _ _ _ _ _ _ _ _>| Procedural |

Control Procedural Commands l LOQIC | I |_ _ _|_ _ J

I‘ _ _ _ _ ‘l I‘ _ _ _ _ ‘l

l Macro | _ _ _ _ _ _ _ lCombinationall

| COntrOl | Macro Commands | Logic I

l___|___l l___|___l

I- — —v— — ‘I I- — —v— — ‘I (Physical

l Primitive | _ _ _ _ _ _ _ | Low Level | or

| Control | primitive commands_>| Elements | ' Simulated) |_____J |_____J System

Command Contro| Software Protocol Protocol Interface Communications Target Target

System System Image Image

Figure 15

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US. Patent Mar. 12, 2013

Procedural Control

| Primitive _ _ _

| Control | l_ _ _ _ _ J

Figure 16a

Procedural Control

F__ ‘I

|

l__ Macro Control |

l___|___|

Procedural Commands

Macro Commands

Primitive Commands

Sheet 13 0f 16

______>

Procedural Commands

Macro Control |____l

l

Primitive Control |____l /

Slower Logical

Operations

Figure 16b

1 Macro Commands

L Primitive Commands

_____l

US 8,396,701 B2

/ Light message flux

/ Moderate message flux

/ Heavy message flux

I- _ _ _ _ _l

| Procedural | | Logic | |_ _ _ _ _ _|

l

| l

l- _ _ _ _ _|

| Combinational | | Logic | l___|___l

l l- _ _ _ _ ‘I

| Low Level | | Elements |

l_ _ _f_ _ _l

Quicker

Logical Operations

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US. Patent Mar. 12, 2013 Sheet 14 0f 16 US 8,396,701 B2

Tasks List & Constraints

Scheduling & Optimization

Scheduling —>

Management Library

High-level Operations —>

Operations Library

Resource Allocation —>

and Release

Configuration Library

Local Subsystem Definition —>

and Operation

High-Level Function Library

va|ve Chemical Complex—> ‘— System Mode Element

Mode Low-Level Low-Level Function Function Library Library _

valve Chemical Complex—> 4— System Primitives E|.er.n.ent

Primitives Raw Raw

Function Function Set Set Individual

Individual Chemical valve <— System Control E|ement

" " Control

Chemical System Elements

Valves within Valve Complexes

Figure 17

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US. Patent Mar. 12, 2013 Sheet 15 0f 16 US 8,396,701 B2

LCD Alphanumeric Display

|2c Bus Loop-Through

® 6 2

o o SPDTValve

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US 8,396,701 B2 1

SOFTWARE SYSTEMS FOR DEVELOPMENT, CONTROL, PROGRAMMING, SIMULATION,

AND EMULATION OF FIXED AND RECONFIGURABLE LAB-ON-A-CHIP

DEVICES

CROSS-REFERENCE TO RELATED APPLICATIONS

Pursuant to 35 U.S.C. Section 119(e), this application claims bene?t of priority from provisional patent application Ser. No. 61/005,460, ?led Dec. 4, 2007, the contents of Which are hereby incorporated by reference herein in their entirety.

FIELD OF THE INVENTION

The present invention generally pertains to the design of lab-on-a-chip devices, and in particular to the speci?cation, numerical simulation and physical emulation of chemical processing systems therein operating under softWare control.

SUMMARY OF THE INVENTION

Features and advantages of the invention Will be set forth in the description Which folloWs, and in part Will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the inven tion Will be realiZed and attained by the structure particularly pointed out in the Written description and claims hereof as Well as the appended draWings. An embodiment includes a system for the development of

a softWare-controlled Lab-on-a-chip (“LoC”) device. The system includes a speci?cation language ?le for specifying LoC element attributes of elements and interconnections among elements, the speci?cation ?le for determining a model for an LoC device; an authoring/editing tool for creat ing and/or editing the speci?cation ?le; an operating language script for controlling the operation of a modeled LoC device; a control design tool for creating and/or editing the opera tional language script; a numerical simulation system for producing a real-time numerical simulation of the operation of the model LoC device; a data visualiZation system for creating real-time visualizations of data from the numerical simulation; Wherein the authoring/ editing tool, control design tool, numerical simulation system, and data visualiZation sys tem are integrated into a common system sharing the speci ?cation language ?le and operational language script.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features, and advantages of the present invention Will become more apparent upon con sideration of the folloWing description of preferred embodi ments, taken in conjunction With the accompanying ?gures.

FIG. 1 shoWs an exemplary tWo-dimensional attribute space (tWo-attribute demographic landscape) for LoC devices.

FIG. 2a shoWs use of a recon?gurable physical chemical process emulation setup as a tool for developing and concep tual testing of a plurality of ?xed LoC systems.

FIG. 2b shoWs use of a recon?gurable physical chemical process emulation setup as a tool for developing and concep tual testing of recon?gurable LoC systems.

FIG. 3a depicts the situation Where With potential candi date applications, very feW can demonstrate enough market siZe to justify siZable R&D and manufacturing costs and risks.

20

25

30

35

40

45

50

55

60

65

2 FIG. 3b shoWs potential candidate applications of FIG. 3a

clustered into ?ve such potential recon?gurable LoC prod ucts.

FIG. 30 depicts an example Where several potential recon ?gurable LoC products immediately demonstrate enough potential market to merit both R&D and manufacturing With others de?ned to aggregate enough market siZe to merit at least R&D.

FIGS. 3d-3g depict steps in an exemplary commercializa tion-enabled scenario demonstrating immense value in pur suing recon?gurable LoC design.

FIG. 4 shoWs the construction of another attribute space relevant to the inclusion of recon?gurable LoC devices and emulation systems emulating LoC devices.

FIG. 5 shoWs a softWare-controlled recon?gurable LoC emulation system that can be used to emulate a Wide range of differing imagined, planned, designed, prototyped, and/or realiZed LoC devices.

FIGS. 6a-6b shoW exemplary overvieWs of the functional elements of an embodiment of the invention.

FIG. 7a shoWs a global vieW of an integrated system for simulation, emulation, and in some applications direct con trol of a ?xed-design LoC device from one or more common scripts and/or ?les.

FIG. 7b shoWs a global vieW of an integrated system for simulation, emulation, and in some applications direct con trol of a con?gurable or recon?gurable LoC device from one or more common scripts and/ or ?les.

FIG. 8a depicts exemplary primitive elements that may be used in the design of larger chemical process systems as may be used in lab-on-a-chip devices.

FIG. 8b depicts an exemplary subsystem design that may be assembled from the exemplary primitive elements of FIG. 811 such as may be used in the design of a larger chemical process systems as may be used in lab-on-a-chip devices.

FIGS. 9a-9c depict hoW the exemplary subsystem design of FIG. 8b may be constructed in steps from the exemplary primitive elements of FIG. 8a to assemble larger subassembly designs, and using these and copies of them to assemble the FIG. 8b subsystem design.

FIG. 10a depicts a subassembly design that may be con structed from exemplary primitive elements of FIG. 8a and that may be used in constructing designs for larger subassem blies and subsystems.

FIG. 10b depicts a multi-channel chemical delivery bus design that may be constructed from multiple copies of the subassembly of FIG. 1011.

FIG. 11 depicts an exemplary recon?gurable lab-on-a-chip system design that may be constructed from an instance of the design ofFIG. 10a, an instance ofthe design ofFIG. 10a, and multiple instances of a modi?ed version of the subassembly of FIG. 90.

FIG. 12 depicts a graphical layout as may be used in fab rication design and/or an animated visualiZation of a simu lated or emulated operation of the design of FIG. 11.

FIG. 13 shoWs a high-level vieW of an exemplary softWare architecture Wherein a higher-level control system controls any one or more of a target actual, emulated, or simulated system.

FIG. 14 shoWs an exemplary control hierarchy of such an exemplary softWare architecture.

FIG. 15 shoWs an exemplary transactional organiZation for an exemplary hierarchy of control.

FIG. 1611 shows an exemplary message ?ux typically asso ciated With a task at various levels in the hierarchy of com mands.

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