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Switch-Level Modeling

Chap. 11 in

Verilog HDL A Guide to Digital Design and Synthesis

by Samir Palnitkar

Switch-Level Modeling Dept. of CSIE, DYU 2

Learning Objectives Describe basic MOS switches nmos, pmos, and cmos

Understand modeling of bidirectional pass switches,power, and ground

Identify resistive MOS switches

Explain the method to specify delays on basic MOSswitches and bidirectional pass switches

Build basic switch-level circuits in Verilog, usingavailable switches

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Switch-Modeling Elements MOS switches CMOS switches Bidirectional Switches Power and Ground Resistive Switches Delay specification on switches

Examples CMOS inverter CMOS nor gate 2-to-1 multiplexer simple CMOS flip-flop


MOS Switches

two types of MOS switches can be defined with thekeywords, nmos and pmos nmos n1(out,data,control);

pmos p1(out,data,control);

data

control

out

NMOS

data out

controlPMOS

zxHLx z10

controlpmos

zzzzxzxxHz11Lz00

zxHLx z10

controlnmos

zzzzxxzxH1z1L0z0

data

dataL: 0 or z

H: 1 or z

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CMOS Switches

CMOS switches are declared with the keywordcmos

the ncontrol and pcontrol arenormally complements of each other

when ncontrol signal is 1and pcontrol signal is 0the switch conducts

when ncontrol signal is 0and pcontrol signal is 1the output of the switch is z

cmos c1(out,data,ncontrol,pcontrol);

nmos (out,data,ncontrol);

pmos (out,data,pcontrol);

data

ncontrol

out

CMOS

pcontrol


Bidirectional Switches

three keywords are used to define bidirectionalswitches tran: acts as a buffer between inout1 and inout2

tranif0: connects inout1 and inout2 only if controlsignal is 0

tranif1: connects inout1 and inout2 only if control

signal is 1

tran t1(inout1,inout2);

tranif0 (inout1,inout2,control);

tranif1 (inout1,inout2,control);

inout2

tran

inout1

control

inout2

tranif0

inout1

control

inout2

tranif1

inout1

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Power and Ground

the power (Vdd, logic 1) andground (Vss, logic 0) sources

needed when transistor-level circuits are designed

defined with keywords supply1 and supply0

place logical 1 and 0 continuously on nets

supply1 vdd;supply0 vss;

assign a = vdd; // connect a to vdd

assign b = vss; // connect b to vss


Resistive Switches

MOS, CMOS, and bidirectional

switches can be modeled ascorresponding resistive switches

have higher source-to-drain

impedance reduce the strengthof signals

passing through

declared with

rnmos, rpmos, and rcmos

rtran, rtranif0, and rtranif1highzhighz

smallsmall

smallmedium

mediumweak

mediumlarge

weakpull

pullstrong

pullsupply

Output

Strength

Input

Strength

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Delay specification on switches

MOS and CMOS switches delays are optional and appear immediately after the

keyword for the switch rise, fall, and turn-offdelays

zero, one, two, or three delays

cmos #(5) c1(out,data,nctrl,pctrl);cmos #(1,2) c2(out,data,nctrl,pctrl);

Zero, One, Two, or

Three delays (same as

above)

cmos, rcmos

pmos p1(out,data,control);pmos #(1) p1(out,data,control);nmos #(1,2) p2(out,data,control);nmos #(1,3,2) p2(out,data,control);

Examples

Zero (no delay)

One (same delays on all)

Two (rise, fall)

Three (rise,fall,turnoff)

pmos, nmos

rpmos, rnmos

Delay SpecificationSwitch element


Delay specification on switches (Contd)

Bidirectional pass switches

do not delay signals passing through them

have turn-on and turn-offdelays while switching

Specify blocks

pin-to-pin delays and timing checks can also be specified

rtranif0 rt1(inout1,inout2,control);tranif0 #(3) t1(inout1,inout2,control);tranif1 #(1,2) t1(inout1,inout2,control);

Zero, (no delay)

One (both t-on and t-off)

Two (turn-on, turn-off)

tranif1,rtranif1

tranif0,rtranif0

Examples

no delay specification

allowedtran, rtran

Delay SpecificationSwitch element

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Switch-Modeling Elements MOS switches CMOS switches Bidirectional Switches Power and Ground Resistive Switches Delay specification on switches

Examples CMOS inverter CMOS nor gate 2-to-1 multiplexer simple CMOS flip-flop


Examples

CMOS Inverter

// Define CMOS inverter

module my_inv(out,in);

output out;input in;

supply1 pwr;supply0 gnd;

pmos p1(out,pwr,in);nmos n1(out,gnd,in);

endmodule

Vdd

gnd

in out

pwr

in out

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Examples (Contd)

CMOS Nor Gatea

bout

b

Vdd

gnd

a

out

c

pwr

// Define nor gate

module my_nor(out,a,b);output out;input a,b;wire c;

supply1 pwr;supply0 gnd;

pmos pb(c,pwr,b);pmos pa(out,c,a);nmos na(out,gnd,a);nmos nb(out,gnd,b);

endmodule

module stimulus;wire OUT;reg A,B;wire c;

my_nor nor1(OUT,A,B);

initialbegin

A=1b0; B=1b0;#5 A=1b0; B=1b1;#5 A=1b1; B=1b0;#5 A=1b1; B=1b1;

end

endmodule


Examples (Contd)

a 2-to-1 multiplexer using CMOS Switches

//2-to-1 mux using switches

module mux_2to1(out,s,i0,i1);output out;input s,i0,i1;wire sbar;

my_inv not1(sbar,s);

cmos c1(out,i0,sbar,s);cmos c2(out,i1,s,sbar);

endmodule

2-to-1

Mux

i0

i1

S

out

2-to-1 Mux

i0

i1

S

outsbar

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Exercise 4-to-1 MUX

Switch-level multiplexer a 4-to-1 multiplexer with 2 select signals

4-to-1

Mux

i0

i1

i2

i3

s1 s0

out

i3

i2

i1

i0

outs0s1

11

01

10

00

//4-to-1 mux using switches

module mux_4to1(out,s0,s1,i0,i1,i2,i3);output out;input s0,s1,i0,i1,i2,i3;. . .endmodule


Examples (Contd) a level-sensitive CMOS flip-flop

switches C1 and C2 are CMOS switches complement of the clock is fed to the ncontrol input of C2

C1 is closed if clock = 1

C2 is closed if clock = 0

module cff(q,qbar,d,clk);

output q,qbar;input d,clk;wire e, nclk;

my_inv not1(nclk,clk);

cmos c1(e,d,clk,nclk);cmos c2(e,q,nclk,clk);

my_inv not2(qbar,e);my_inv not3(q,qbar);

endmodule

FFd

clock

qbar

q

d e

C2

q

qbarC1

clock

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Exercises1. draw the circuit diagrams for the following 2-input gates

(using nmos and pmos switches), andwrite the Verilog descriptions for the circuitsa) xor

b) and

c) or

2. Design the 1-bit full-adder shown below using the xor, and andor gates built above

a

b

c_in

c_out

sum

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