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Creating a 12 x 8 MAC Using VHDL

For Academic Use Only

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Creating a 12 x 8 MAC Using VHDL

IntroductionIn this lab, you will create a 12-bit x 8-bit MAC (Multiplier Accumulator). You will consider

some of the decisions you are required to make when you code a MAC, and this will help you

become more familiar with the Xilinx implementation tools. This lab is completed using the

Xilinx ISE 6 software. You will use a typical HDL flow, write the HDL code, run a functional

HDL simulation, synthesize your design with XST, and take the synthesized design through the

Xilinx implementation tools.

Note: For non-VHDL users, or for help with writing the MAC, the completed file and project is

provided in the c:\xup\dsp_flow\labs\lab1\lab1_soln directory.

Objectives

After completing this lab, you will be able to:

Perform the basic design flow for generating a VHDL MAC

Simulate a VHDL file

Synthesize a design using XST

Implement a design using the Xilinx implementation tools

Design Description

Create a 12 x 8 MAC using VHDL that has the following behavior:

Multiplier input data widths of 12-bits and 8-bits

Accumulator output width of 27-bits

Multiplier input signal that indicates when to perform a multiply

Handshaking signal from the multiplier that indicates when to accumulate

You will do this by behaviorally describing a multiplier and an accumulator individually in

VHDL.

Creating a 12 x 8 MAC Using VHDL university.xilinx.com 11-3For Academic Use Only

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Multiplier Accumulator

mult_int

rdy_int

20 2712

B8

AA

CLK

ND

CLR

Q

Figure 11-1. Block Diagram of the Multiply Accumulator

Procedure

This lab comprises five primary steps: you will start the project navigator and open the project;

simulate the design using ModelSim simulator; synthesize the design using XST; implement the

design using ISE 6, and finally, read and understand the results generated by the implementationtools. Below each general instruction for a given procedure, you will find accompanying step-by-

step directions and illustrated figures providing more detail for performing the general instruction.

If you feel confident about a specific instruction, feel free to skip the step-by-step directions and

move on to the next general instruction in the procedure.

Note: If you are unable to complete the lab at this time, you can download the lab files for this

module from the Xilinx University Program site athttp://university.xilinx.com

Start the Project Navigator and Open the Project Step 1

Launch the ISE Project Navigator and open the mac_vhdl project.

Open the Xilinx ISE 6 software: Go to Start MenuProgramsXilinx ISE 6Project Navigator

Open the mac_vhdl project: In the Project Navigator, select FileOpen Project

Browse to c:\xup\workshop\dsp_flow\labs\lab1 using the pull-down arrow

Select mac_vhdl.npl project file

ClickOK


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Generate the Behavioral VHDL Code for the MAC Step 2

Open the mac_vhdl.vhd file and modify it to perform the 12 x 8 multiply

accumulate. Refer to Figure 11-1 block diagram to understand the provided code.The comments in the code will guide you to complete this step. Spend 15 minutes

working on your VHDL code, then move on and use the solution provided in

lab1_soln directory.

Open the mac_vhdl.vhd file: In the Sources in Project window, double-clickmac_vhdl.vhd

Read through the VHDL file and add code to the following sections:

Generating the Multiplier Generating the Accumulator

Select mac_vhdl.vhd in the Sources in Project window

In the Processes forCurrent Source window, expand Synthesis

Double-click the Check Syntax option to perform syntax check

Fix any reported errors

Simulate the Design Using MTI Step 3

Simulate your VHDL code to verify that it is functioning correctly. If after

simulating the design you find an error, you can go back and make changes,recompile the code, and re-simulate

Select the mac_vhdl_tb.vhd file in the Sources in Project window

Expand the ModelSim Simulator in the Processes for Current Source window


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Figure 11-2. Expanding the ModeSim Simulator in project Navigator

Run behavioral simulation: Double-clickSimulate Behavioral VHDL Model

Verify the operation of the MAC by looking at the input and output signals in the testbenchnamed *_tb

Figure 11-3. Simulating the MAC in ModelSim Simulator


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Note: It may be easier to view the input and output in decimal. This can be done by

highlighting the appropriate signals in the waveform viewer, then use the pulldown menus

Format Radix Decimal Close the simulator: After you have verified the operation, close the simulator by using File

Quit from the simulators command window

Synthesize the Design Using XST Step 4

Synthesize the mac_vhdl.vhd design using Xilinx Synthesis Technology (XST)tool

Note: We have turned off inference of Virtex-IIP Embedded Multipliers in synthesis to get a

better comparable result with the CORE Generator MAC, which will be configured to be

implemented in LUTs.

Select the mac_vhdl.vhd file in the Sources in Project window

Run synthesis: Right-clickSynthesis in the Processes for Current Source window andselect the Run option

Alternatively, double-clickSynthesize in the Processes for Current Source window


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Figure 11-4. Running XST to Synthesis in Project Navigator

Note: A green check will appear next to Synthesize when it is successfully completed. A

yellow exclamation mark indicates that a warning was generated, and a red cross indicates

that an error was generated. Warnings are OK

If there are any errors, you can View Synthesis Report by expanding Synthesis, right-click

and choose the View option; otherwise, continue to the next step


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Figure 11-5. Viewing the Synthesis Report in Project Navigator

Note: The following are synthesis tool attributes to control embedded multiplier inference:

XST VHDL attribute/command line: mult_style = {auto | block | lut} default is auto

LeonardoSpectrum - script variable: virtex2P_multipliers = {true | false} default is true

Synplify VHDL attribute/command line: syn_multstyle = {block_mult | logic} default

is block_mult


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Implement the MAC Design Step 5

Implement yourmac_vhdl.vhd design using Xilinx implementation tools with thefollowing information and view the Post-place & Route Static Timing Report.

Device Family: Virtex2P

Device: xc2vp4

Speed Grade: 7

Package: FG456

Right-clickImplement Design, and choose the Run option, or double left-clickImplement

Design


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Figure 11-6. Running Implementation from Project Navigator

Note: This runs the design through Place and Route. You will notice green check marks (orwarning exclamations) next to the processes that have finished successfully. It will also run

Post-Place & Route Static Timing and generate the static timing report.

View the Post-Place & Route Timing Report: Expand and open the Text Based Post Place

& Route Static Timing Report

Questions

1. Open the Place and Route report file, and fill in the information requested below.

Number of Slices:

Number of BUFGMUXs:

Number of external IOBs:

2. Open the Post-Place and Route Timing report, and fill in the information

requested below.

Maximum clock frequency:

Note: We will be using this information to compare with the results of the CORE Generator andthe System Generator.

Bonus Activity

If you have finished the lab early and have time, you can look into the following:

3. How would you implement saturation logic for the accumulator?

Implement this in your VHDL code, and verify that it works for both positive and

negative numbers Open the Place and Route report file, and fill in the information

requested below.


?

?

?

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4. Fill in the information requested below.

Number of Slices:

Number of BUFGMUXs:

Number of external IOBs:

Maximum clock frequency:


?

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Conclusion

In this lab, you learned what the basic design flow entails from writing a VHDL code through

implementation. You have experienced some challenges in writing the VHDL MAC. You ran a

piece of VHDL code through simulation. Next, you synthesized the code using XST and

implemented the design using the Xilinx implementation tools running under Xilinx ISE 6

software environment.

Answers

Your results may differ from the numbers provided below, depending on how your design was

coded.

1. Open the Place and Route report file, and fill in the information requested below.

Number of Slices: 15

Number of Mult18x18s _______1_____________

Number of BUFGMUXs: 1

Number of external IOBs: 50

2. Open the Post-Place and Route Timing report, and fill in the information

requested below.

Maximum clock frequency: ~135 MHz

3. How would you implement saturation logic for the accumulator?

You need to create a check value by summing the current multiply output with

the last accumulator value, and determine if the value exceeds the range of the

accumulator (27 bits). If so, then hold the accumulator to the max value. The

check signal has to be one-bit larger to accommodate a check value that is larger

than the accumulator width.

Example VHDL code for saturation can be found in the

c:\xup\dsp_flow\labs\lab1\lab1_soln\mac_vhdl_sat.vhd

4. Fill in the information requested below.

Number of Slices: 106

Number of Mult18x18s ________1____________

Number of BUFGMUXs: 3


A

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Number of external IOBs: 55

Maximum clock frequency: ~ 135 MHz

Creating a 12 x 8 MAC Using VHDL university.xilinx.com 11-14

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