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Lecture 11:Lecture 11:PipeliningPipelining

COS 471a, COS 471b / ELE 375

Computer Architecture and Organization

Princeton University

Fall 2005

Prof. David August

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Program NotesProgram Notes

HW #2 due Friday (tomorrow) 5PM

Midterm is in class one week from Today! One 8.5x11 sheet (front+back OK) ofhandwritten notes

allowed

No book or other material

Project #1 due Tuesday

Reading 1-6, A-C.

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Review: PipelinedReview: Pipelined DatapathDatapath

Note that all R-Type Instructions have a NULL stage!

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Review: Pipeline HazardsReview: Pipeline Hazards

Structural HazardsStructural HazardsResource oversubscription:

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Review: Pipeline HazardsReview: Pipeline Hazards

Control HazardsControl Hazards What is the next instruction?

Branch instructions take time to compute this.

Stall, Predict, or Delay:

Pipeline Stall - only 1 cycle/stage delay

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Review: Pipeline HazardsReview: Pipeline Hazards

Control HazardsControl Hazards What is the next instruction?

Branch instructions take time to compute this.

Delayed Decision (Used in MIPS):

More about Branch Prediction/Delayed Branching Later

50% Fil l Rate

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Review: Pipeline HazardsReview: Pipeline Hazards

Data HazardsData HazardsValue from prior instruction is needed before write back

Data Hazard:

Solution: Bypassing

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Review: Pipeline HazardsReview: Pipeline Hazards

Data HazardsData HazardsValue from prior instruction is needed before write back

Load-Use Data Hazard: Options: Delayed Load or Bubble

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Dependences and Dependence GraphsDependences and Dependence Graphs

On the Blackboard

Flow - RAW

Anti - WAR (a false dependence - use renaming) Output - WAW (a false dependence - use renaming)

Control

Clarification: For our purposes, we can draw control depsbetween each branch and ALL other instructions. Thisis conservative, but will maintain correctness.

Hazards: Can always just stall

Expose stall to compiler/assembly language programmer

Revisit: Delayed Branching

Revisit: Delayed Loads

C

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Compiler Avoidance of Load StallsCompiler Avoidance of Load Stalls

% loads stalling pipeline0% 20% 40% 60% 80%

tex

spice

gcc

25%

14%

31%

65%

42%

54%

scheduled unscheduled

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Pipeline ControlPipeline Control

Control is divided into 5 stages Signal values same as unicycle case!

Timing is different

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Pipeline ControlPipeline Control

Signal values same as unicycle case!

Timing is different

Simplest method: Extend pipe registers

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Pipeline ControlPipeline Control

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What About Data Hazards?What About Data Hazards?

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What About Data Hazards?What About Data Hazards?

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Forwarding UnitForwarding Unit

How does the Forwarding Unit know when to forward?

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Forwarding UnitForwarding Unit

EX Hazard:

EX/MEM.RegWrite AND EX/MEM.RegisterRd != 0 ANDEX/MEM.RegisterRd == ID/EX.RegisterReadRs(Rt)

MEM Hazard very similar, but prefer MEM over WB value

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What About LoadWhat About Load--Use Stall?Use Stall?

Forwarding cant save the day Need to introduce stall in hardware or compiler

Time Travel Necessary!

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Hazard Detection UnitHazard Detection Unit

How does the Hazard Detection Unit know when to forward?

Nop is all zeros!!

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Hazard Detection UnitHazard Detection Unit

ID/EX.MemRead AND(ID/EX.RegisterRt == IF/ID.RegisterRs OR

ID/EX.RegisterRt == IF/ID.RegisterRt)

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What About Control Hazards?What About Control Hazards?

(Predict Not(Predict Not--Taken Machine)Taken Machine)

Architectural

State Change?

We are OK, as long as we squash. Can we reduce delay?

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Reduce Branch DelayReduce Branch Delay

1. Move branch address calculation to decode stage(from MEM stage)

2. Move branch decision up (Harder

Bitwise-XOR, test for zero

Only need Equality testing

Much faster: No carry

Everything is done in decode stage!!

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What About Control Hazards?What About Control Hazards?

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What About Control Hazards?What About Control Hazards?

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Review: ExceptionsReview: Exceptions

What happens if instruction encoding is not valid?

What about arithmetic overflow?

Exception

An event that disrupts program execution.

When an exception occurs:

Save the current PC in the EPC

Cause = 0 for Undefined Instruction, 1 for Overflow

Jump to the OS at C000000016 (not vectored)

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Review:Review: MulticycleMulticycle Exception HandlingException Handling

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Exceptions in PipelinesExceptions in Pipelines

Exception must appear to programmer/OS as it wouldin unicycle/multicycle

Must squash in-flight instructions after excepting inst

Looks a lot like a branch

Dont Forget

EPC and

Cause!!!

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Pipeline Exception HandlingPipeline Exception Handling

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Look at this mess!!!Look at this mess!!!

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Precise vs. Imprecise ExceptionsPrecise vs. Imprecise Exceptions

Precise Exceptions

EPC has value ofexcepting instruction PC

Easy for OS to handle We have been looking at precise exception machine

Imprecise Exceptions

Reduce pipeline complexity by putting current PC orother approximation into EPC

OS figures it out