2L3L INVERTER

E. C. dos Santos Jr. and J. H. G. Muniz and E. R. C. da SilvaElectrical Engineering Department

Federal University of Campina Grande58109-970 Campina Grande - PB - Brazil

e-mail: euzeli@dee.ufcg.edu.br

Abstract- This paper proposes a single-phase in-verter with four levels at the output converterside. The proposed inverter can be considered asan intermediate configuration between the 3-level4-switch H-bridge and 5-level 8-switch H-bridgetopologies. It is called as 2L3L inverter, since itis composed of one two-level leg and one three-level leg. The most important characteristics ofthe proposed configuration are: reduced numberof semiconductor devices, the same blocking volt-age for all switching devices, and no low frequencycurrent circulating in dc-link capacitors. Detailsregarding the operation of the configuration andmodulation strategy is presented, as well as thecomparison between the proposed H-bridge in-verter and the conventional NPC four-level in-verter. Simulated and experimental results arepresented to validate the theoretical expectations.

I. Introduction

Multi-level converters were first conceived for high-voltage and high-power applications beginning with theNPC inverter proposed by [1]. Since then, many config-urations have been proposed [2,3] to establish the highlydesirable characteristics for high-power applications, suchas reduced waveform distortion and low blocking voltageby switching devices [4] . The three principal configura-tions are diode-clamped (or NPC), flying capacitor andcascade multi-level inverters [5, 6].

More recently, the multi-level converters has found ac-ceptance in low power applications, especially in pho-tovoltaic applications, since it is possible to generatehigh-quality voltage waveforms with power semiconduc-tor switches operating at a frequency near the fundamen-tal [7] and the number of the input dc-sources, for thisapplication, is not longer restricted [8]. Even consideringjust one dc voltage source available, it is possible to em-ploy multi-level converters with different dc-link voltagesusing additional circuitry [9].

Dc-ac multi-level converters for single-phase outputvoltage has been also explored in the technical literaturedue to its importance in low power applications [10–15].In [16] was proposed a single-phase multilevel converterfor application in electrified railway, while in [17] was pro-posed a family of single-phase multi-level inverters with-out clamping diodes and flying capacitors. The single-

phase converter in [18] uses two asymmetrical 4-levelconverters to generate the proposed hybrid cascade con-verter. Four-level inverters conceived for single-phase ap-plications were explored in [6, 19–21].

This paper proposes a single-phase inverter with four-levels at the output converter side. The proposed H-bridge topology is depicted in Fig. 1. Such configurationneeds three dc sources, which can be obtained through aset of PV arrays, as in [22], or from a unique PV arrayand with additional circuitry, as in [6].

The proposed inverter can be considered as an interme-diate configuration between the 3-level 4-switch H-bridgetopology, as observed in Fig. 2(a) and the 5-level 8-switchH-bridge topology, as observed in Fig. 2(b). Then, fol-lowing this nomenclature, the proposed 2L3L inverter isa 4-level 6-switch H-Bridge topology.

The most important characteristics of the proposed cir-cuit is: reduced number of semiconductor devices, specif-ically of the diodes, the same blocking voltage for allswitching devices, and no low frequency current circu-lating in dc-link capacitors. Details regarding the config-uration model, operation and modulation strategy is pre-sented, as well as the comparison between the proposedinverter and the conventional single-phase four-level NPCinverter, as observed in Fig. 3. This topology was consid-ered in the comparison, since it has the same number ofswitches and generates the same number of levels. Sim-ulated and experimental results are presented to validate

Fig. 1. : 2L3L inverter topology.

978-1-4577-1646-1/11/$26.00 ©2011 IEEE 924

(a) (b)

Fig. 2. : Conventional configuration and its output voltage waveform. (a) 3-level 4-switch H-bridge topology. (b)5-level 8-switch H-bridge topology.

the theoretical expectations.

II. Operation of the 2L3L Inverter

The proposed H-bridge is constituted by six controlledswitches (S1, S1, S2, S2, S3, S3), two clamping diodes,three dc sources, and four dc-link capacitors. Theswitches S1, S1, S2 and S2 are used to compose the three-level leg (3L), while the switches S3 and S3 are used tocompose the two-level leg (2L), the switches S1, S2, S3

are complementary to the switches S1, S2, S3, respec-tively. To guarantee a symmetrical output voltage, it isnecessary to make V1 = V3 = 0.5V2 = V . As observed inFig. 1, the single-phase load is connected to the points aand b, then

vl = va0 − vb0 (1)

where

va0 = 2V if {s1=s2=1}va0 = 0 if {s1=s2=1}va0 = −2V if {s1=s2=0}

Fig. 3. : Conventional four-level NPC configuration.

TABLE I: Output voltage considering all switchingstates available.

State {S1 S2 S3} vl

1 {0 0 0} −V2 {0 0 1} −3V3 {0 1 0} V4 {0 1 1} −V5 {1 1 0} 3V6 {1 1 1} V

and

vb0 = V if {s3=1}vb0 = −V if {s3=0}

with sj (j = 1, 2, 3) representing the conduction states ofthe switches Sj (j = 1, 2, 3), with sj = 1 for the turned-onswitch and sj = 0 for the turned-off switch (sj = 1− sj).

Considering all possibilities of switching states avail-able, the output voltage is determined by Table I. Fromthis table is possible to observe that there are four levelsfor vl. Considering dc sources with different values, it ispossible to increase the number of levels at the output sideof the proposed H-bridge. However, this is not consideredin this paper since the voltage ratings of the switches willbe different, implying in an irregular distribution of thestress in the switches.

III. Modulation Strategy

The modulation strategy employed for the 2L3L in-verter topology is a combination of the two-level andthree-level PWM approaches, which means that, for thetwo-level leg (2L) it will be employed just one triangu-lar carrier signal, while for the three-level leg (3L) it willbe employed two triangular carrier signals, as observedin Fig. 4. From (1) is possible to write the followingrelations for the reference pole voltage

v∗a0 = v∗l /2 (2)

v∗b0 = −v∗l /2. (3)

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(a) (b) (c)

Fig. 4. : Sine-triangle modulation waveforms for: (a) v∗l > 0. (b) v∗l = 0. (c) v∗l < 0.

The switching states of the power switches are obtainedby comparing the reference pole voltage with the trian-gular waveforms, i.e., the voltage v∗a0 will be compared tovt1 and vt2 to define the switching states of S1 and S2,respectively; while the voltage v∗b0 will be compared tovt3 to define the switching state of S3.

Fig. 4 shows, from top to bottom, the reference polevoltage (v∗a0 and v∗b0), state of the switches (S1, S2 andS3), pole voltages (va0 and vb0) and load voltage (vl).Figs. 4(a), 4(b) and 4(c) show these variables for v∗l > 0,v∗l = 0 and v∗l < 0, respectively. From this figure ispossible to observe the generation of the four levels.

IV. Capacitor Voltage balance

The capacitor voltage balance of the capacitors C2 andC3 is obtained naturally with the modulation strategyused in Fig. 4. Such natural balance can be explained bythe capacitor current, which guarantees capacitor charg-ing and discharging, as observed in Fig. 5. This figureshows the capacitor current path considering all switch-ing states. Figs. 5(a)-(d) highlight the capacitor currentfor il > 0, while Figs. 5(e)-(h) highlight the capacitorcurrent for il < 0. Notice that, after a sinusoidal period,the charging and discharging of the capacitors C2 and C3

are guaranteed by il. As far as the capacitors C1 and

C4 are connected directly to individual dc sources (V1

and V3, respectively) their balance strategy is no longernecessary.

V. General Comparison

In this section will be presented a comparison betweenthe proposed configuration (see Fig. 1) and the conven-tional one (see Fig. 3). Three aspects will be consideredin this comparison, i.e., the number of semiconductor de-vices, the WTHD (Weighted Total Harmonic Distortion)of the load voltage, and the capacitor current in the dc-link capacitors.

A. Number of devices

By a direct comparison, the proposed configurationpresents a reduced number of components, with a reduc-tion of two diodes. Furthermore, the dc-link mid-pointconnection of the proposed configuration is conceived justto guarantee the zero voltage in the three-level leg, whichmeans no low frequency current flowing through the ca-pacitors. On the other hand, the dc-link mid-point con-nection in the conventional configurational is conceived toguarantee the load connection, which means that a lowfrequency current (il) flowing through the capacitors C2

and C3.

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il

S1-on S2-on S3-on

S1

S2

S1

S2

S3

S3

(a)

il

S1-on S2-on S3-on

S1

S2

S1

S2

S3

S3

(b)

il

S1-on S2-on S3-on

S1

S2

S1

S2

S3

S3

(c)

il

S1-on S2-on S3-on

S1

S2

S1

S2

S3

S3

(d)

il

S1-on S2-on S3-on

S1

S2

S1

S2

S3

S3

(e)

il

S1-on S2-on S3-on

S1

S2

S1

S2

S3

S3

(f)

il

S1-on S2-on S3-on

S1

S2

S1

S2

S3

S3

(g)

il

S1-on S2-on S3-on

S1

S2

S1

S2

S3

S3

(h)

Fig. 5. : Capacitor current path considering all switchingstates: (a)-(d) for il > 0 and (e)-(h) for il < 0.

Fig. 6. : WTHD of the load voltage as a function of themodulation index obtained by simulation.

B. Harmonic Distortion of the load voltage

The WTHD (Weighted Total Harmonic Distortion) hasbeen computed by using

WTHD(p) =100a1

√√√√p∑

i=2

(ai

i

)2

(4)

where a1 is the amplitude of the fundamental voltage, ai

is the amplitude of ith harmonic and p is the number ofharmonics taken into consideration.

Fig. 6 shows the WTHD of load voltage (vl) of theconventional and proposed configurations as a functionof the modulation index.

As expected, the harmonic distortion reduces as far asthe index modulation increases for both proposed andconventional converters. For all modulation indexes con-sidered, the proposed converter presents always lowervalues of WTHD compared with the conventional ones,which can be explained by lower oscillation in the dc-linkcapacitor voltages for the proposed circuit.

C. Capacitor Currents

The RMS (Root Mean Square) current observed in thecapacitors of the extremities (C1 and C4) are almost thesame for both 2L3L inverter and conventional NPC topol-ogy, while the current of the interior capacitors (C2 andC3) present a reduction of 36% in the proposed topology,which could be explained through the connection of theload directly to those capacitors in the NPC configura-tion.

VI. Simulated and Experimental Results

To verify the validity of the proposed H-bridge config-uration with four levels, experimental set-up was imple-mented by IGBTs from SEMIKRON controlled by DSPTMS320F28335. The single-phase RL load was connected

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to the output converter with R=65Ω and L=7mH . Threedc sources with 75V each have been also employed. Thedc-link capacitors were of C = 2200µF each.

Fig. 7(a) shows the simulated results for the proposedH-bridge configuration. The waveforms presented in thisfigure are, from top to bottom: pole voltage in the two-level leg (vb0); pole voltage in the three-level leg (va0);load voltage (vl) and load current (il). The same set ofwaveforms are shown in Fig. 8(a) for the experimentalresults.

Figs. 7(b) and 8(b) show simulated and experimentalresults indicating the load voltage (vl), capacitor voltages(vc2 and vc3) and load current (il). From Figs. 7 and 8it is evident the agreement between simulated and exper-imental results. It is worth to mention that the dc-linkcapacitor voltages of C2 and C3 are balanced without anyspecial technique. As discussed in the theoretical analy-sis, the capacitor balancing is naturally achieved with themodulation strategy employed.

(a)

(b)

Fig. 7. : Simulated results. (a) (From top to bottom)pole voltage in the two-level leg, pole voltage in the three-level leg, load voltage and load current. (b) (From top tobottom) load voltage, capacitor voltages vc2 and vc3 andload current.

(a)

(b)

Fig. 8. : Experimental results. (a) (From top to bottom)pole voltage in the two-level leg, pole voltage in the three-level leg, load voltage and load current. (b) (From top tobottom) load voltage, capacitor voltages vc2 and vc3 andload current.

VII. Conclusion

A single-phase inverter with four levels at the outputconverter side is proposed in this paper, it is called as2L3L inverter. The proposed inverter is constituted byone two-level leg and three-level leg presenting the sameblocking voltage for all switching devices. A comparisonbetween the proposed configuration and the conventionalfour-level inverter is presented, where three advantagesare observed for the 2L3L inverter, i.e., the number ofsemiconductor devices, the WTHD of the load voltageand the capacitor current in the dc-link capacitors. Simu-lated and experimental results demonstrate the feasibilityof the proposed converter.

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