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Microprocessor-based systemsCourse 2

General structure of a computer

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Components of a computer system Classic computer model (J. von Neumann)

Control unit (CU) Arithmetical and logical unit (ALU) Memory (M) Input device(s) (ID) Output device(s) (OD)

M

CUDI

DE

ALU

Data and program input

Data output

CPU=CU+ALU

Central Processing Unit

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Components of a computer system

Microprocessor-based computer system – a bus-based system

μP

I/O Interface I/O Interface I/O Interface

Memory Memory

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The Central Processing Unit (CPU) Control Unit (CU)

Responsible for: Instruction fetch (read) Instruction decoding (interpretation) Generation of command signals needed to

execute the instruction It is a sequential circuit (state automatom)

The Arithmetical and Logical Unit (ALU) Executes arithmetical and logical operations:

Arithmetic: +,-,/,*, modulo, comparisons Logic: SI, SAU, NU, Shifts and rotations

Usually it is a combinational circuit Registers

General purpose registers (GR) Holds data Take part in arithmetic and logic operations

Special purpose registers (): Addressing registers Status register Test registers Control registers

CPUCU

PhG CG RI

ID + CCB PC

SR

GR

R1 Rn

System Bus

R2 …

ALU

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Control Unit (CU) The brain of the computer It is composed of:

Clock generator (CG) Generates the clock (synchronization)

signal Phase generator (PhG)

Generates the phases needed for instruction execution

The Instruction Decoder (ID) and the Command and Control Block (CCB)

Interpret the instructions and generate command signals needed for instruction execution

Instruction register IR Keeps the current instruction

Program counter PC Keeps the address of the next

instruction (to be executed) (Program) Status Register (SR)

UC

PhG

CG

IR

ID + CCB

PC

SR

Commands

Address

Instructions

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Arithmetical and Logical Unit

Ac – Accumulator register Keeps one of the operands

and the result R – register for the 2nd

operand SR Status register

R Ac

ALU

n n

n

n n

Operation

SR

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Arithmetical and Logical Unit

One bit adder with carry Si = Ai + Bi + Ti-1

Ci = Ai*Bi +Ci-1*(Ai + Bi)

Ti-1 Si

Ci

Ai

Bi

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n bits adder

n-1

Sn-1

Bn-1 An-1

Cn-1 Cn-2

1

S1

B1 A1

C1 C0

0

S0

B0 A0

C-1

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Adding operation with 2 registers

0

D0

1

D1

A1

n-1

Dn-1

A n-1 A0

B0B1Bn-1

CLKB

Ad

CLKA

Step Operation Commands

1 Clear A

Transfer D → B (operand 1) Ad = 0, CLKA = П (impuls)

CLKB = П 2 Transfer B → A , D → B (operand 2) Ad = 1, CLKA = П, CLKB = П

3 A ← A + B Ad = 1, CLKA = П

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Circuit for adding and subtraction in 2th complement

For adding: Ad/Sub = 0 For subtraction the second operand is complemented

Ad/Sub=1

0

D0

1

D1

A1

n-1

Dn-1

A n-1 A0

B0B1Bn-1

CLKB

CLKA

Ad / Sub

T0T1Tn-1

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Logical unit with 4 operations

MUX 4:1

Ci-1

Ai-1

Operation code

Bi-1

MUX 4:1

Ci

Ai Bi

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Multiply operation

1100 * 12 * 1010 10

0000 1100 00001100

1111000 = 78H = 120

Modified multiply operation:

00000000 Acumulator (AC)“0” → 0000000 0 Shift right“1” → 1100 Adding

0001100 0 Partial product 000110 00 Shift right“0” → 00011 000 Shift right“1” → 1100 Adding

1111 000 Final product

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Implementation of the multiply operation

(n+1)

Command DeviceShift right

X

Q0Q1Q n-1. . .

B0B1Bn-1. . .BS

A0A1An-1. . .AS

Q S

Y

Clear

Write

Write

Test

Shift right

Write

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Multiply algorithm

1. Write the operands into the registers B ← X, Q ← Y, clear the accumulator A ← 0

2. Complement the operands if they are negative

3. Test Q0

1. Q0 = 0, shift A and Q to the right

2. Q0 = 1, add A = B + A and shift A and Q to the right

Repeat step 3 until Yn-1 get into Q0. In the last step the shift is not necessary

AS = BS + QS

Complement the result if AS = 1

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Division circuit

Sum, Diference Control device

X

Q0Q1Q n-1. . .

B0B1Bn-1. . .BS

A0A1An-1. . .AS

Q S

Y

Ad / Sc

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Division algorithm 1. Load the first operand in registers A and Q

Load the second operand in register B2. Memorize AS + BS in QS. If

AS = 1, complement A, Q

BS = 1, complement B

3. Tests:• A ≥ B, overflow• B = 0, division by 0• A = 0 and Q < B, result = 0

4. Shift A, Q to the left and put 0 in Q0

5. Subtract B from A and put the result in A. IfAS = 0, shift left A, Q and put 1 in Q0

AS = 1, add B to A, shift left A, Q and put 0 în Q0

6. Repeat step 5 for n times7. Round the result: if A ≥ B, add 1 to Q8. If QS = 1 complement register Q

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Adding in floating point representation

1. Load the operands into registers2. Compare the exponents (5 cases):

ex = ey, add mantissas and copy the exponentex > ey and (ex – ey) < mantissa’s bits, than my is aligned by

shifting to the rights with ex-ey positions and than add mx with my

ex >> ey and (ex – ey) ≥ mantissa’s bits, than copy X into the result

ex < ey şi (ey – ex) < mantissa’s bits, than mantisa mx is aligned by shifting to the rights with ey-ex positions and than add mx with my

ex << ey şi (ey – ex) ≥ mantissa’s bits, than copy Y into the result3. Normalize the result. Test the bits around the decimal

point and if necessary shift the mantissa to the right or to the left and increment or decrement the exponent

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Adder circuit for floating point numbers

Σ

X

exp mantissaS

Y

A

exp mantissaSBShiftLoad

Shift

Load

Control device

Exp A

Exp BIncrement

Increment

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Multiply and division in floating point

representation Multiply is made as follows:

add the exponents multiply the mantissas normalize the result

Division is made as follows: subtract exponents divide mantissas normalize the result

Σ / Δ

expmantissa A

A

mantissa B

Inc/Dec A

ShiftLeft/right A

Ad/ Sc

S

expB

Inc/Dec B

S

Comand device

Shiftleft/right B

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Design of a simple computer

Design steps:1. Establish the destination and the domain of use for the

computer;2 Define the instruction set and instruction format;3 Design the block scheme of the central processing unit;4 Decompose instructions into micro-operations and phases;5 Define the logical equations/functions for the micro-

commands;6 Design the logical scheme for the PhG and CCB;7 design the other modules: IR, PC, GR, ALU, SR, CG;8 Design of memory modules;9 Design of I/O interfaces;10 Optimize the scheme through steps 2-9

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Simple computer:Design steps

Destination: General purpose computer Special destination computers:

embedded computers signal processing computers control systems

High performance computers: Parallel and distributed systems (GRID, Cloud, etc.)

Instruction set: Instruction format: (length and fields)

Fixed: Variable

Operation Types: Arithmetic Logic Transfer Jump and branch Stack operations, etc.