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Microprocessor and Interfacing Techniques SE/Computer Engg. Department of Computer Engineering ZES’s DCOER, Pune-411041 Page1 Zeal Education Society’s Dnyanganga College of Engineering and Research, Pune Department of Computer Engineering Lab Manual Microprocessor Interfacing & Techniques Second Year (2012 Pattern) SEM II

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Page 1: Microprocessor Interfacing & Techniques · PDF fileMicroprocessor and Interfacing Techniques SE/Computer Engg. Department of Computer Engineering

Microprocessor and Interfacing Techniques SE/Computer Engg.

Department of Computer Engineering ZES’s DCOER, Pune-411041 Page1

Zeal Education Society’s

Dnyanganga College of Engineering

and Research, Pune

Department of Computer Engineering

Lab Manual

Microprocessor Interfacing &

Techniques

Second Year (2012 Pattern)

SEM – II

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Experiment No: 1

Title: Addition of Array

Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _

Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff Member

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Experiment No: 1

Title: Addition of Array

Aim: Write X86/64 Assembly language program (ALP) to add array of N

hexadecimal numbers stored in the memory. Accept input from the user

Prerequisite: Microprocessor Architecture

Objectives: To learn the instructions of 8086

To learn the addition of array

Theory:

The arithmetic instructions of the 80386 processor simplify the

manipulation of numeric data that is encoded in binary. Operations

include the standard add, subtract, multiply, and divide as well as

increment, decrement, compare, and change sign. Both signed and

unsigned binary integers are supported. The binary arithmetic

instructions may also be used as one step in the process of performing

arithmetic on decimal integers. Many of the arithmetic instructions

operate on both signed and unsigned integers. These instructions update

the flags ZF, CF, SF, and OF in such a manner that subsequent

instructions can interpret the results of the arithmetic as either signed or

unsigned. CF contains information relevant to unsigned integers; SF

and OF contain information relevant to signed integers. ZF is relevant

to both signed and unsigned integers; ZF is set when all bits of the result

are zero.

ADD Instructions:

ADD replaces the destination operand with the sum of the source and

destination operands.

Syntax: ADD destination, source

Modifies flags: AF CF OF PF SF ZF.

int 80h : System Call 4:System Write.

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EAX = 4 indicates system write operation.

EBX represent file descriptor: 0- Standard Input device. 1- Standard

Output device. 2- Standard

Error.

ECX represents the variable/parameter whose value one want to display.

EDX represents the length of the variable/parameter

Algorithm 1. In initialized data segment, declare the variables arr32 to hold

the array elements, n holds

Number of elements. In uninitialized data segment declare the

variable char sum.

2. Define the macro print with 2 parameters. Call interrupt 80h

with function EAX = 4 &

EBX as file descriptor 1for standard output device.

3. Define the macro exit with 2 parameters to take the exit.

4. Move the effective address of array into ESI register.

5. Move the value of n into EDI.

6. Initialize EAX & EDX with 0.

7. Add the contents of memory location pointed be ESI with EAX

& store the result back

into EAX.

8. If carry generated, Increment the value of EDX.

9. Else go to the step 10.

10. Increment the ESI with 4 to point to net number in the array.

11. Decrement EDI by 1.

12. If jump on not zero condition true go to step 7.

13. Else load EBX with value of n.

14. Call the procedure disp32_proc.

15. To take the exit use macro expansion

Procedure disp8num:

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15) Move ESI with effective address of char_sum + 7.

16) Move ECX with 8.

17) Move EDX with 0.

18) Move EBX with 16.

19) Divide EBX by EAX. Register dl hold the result.

20) Compare dl with 09h.

21) Check jump below or equal goto step 9.

22) Else add dl with 07h.

23) Add dl with 30h.

24) Move the contents of dl into memory pointed by ESI.

25) Decrement ESI.

26) Repeat the steps 3 to 11 till ECX is equal to 0.

27) Expand macro print with the parameters char _num & 8.

28) Return.

Conclusion: Hence We have studied ALP to addition of array of N hexadecimal

numbers stored in the memory.

Questions: 1) What are the interrupts used in above program. Explain in

detail.

2) What is the assembler directives used in above program?

3) Explain the flag register of 8086 and 80386 microprocessor?

4) Define the logic used in above program

5) How to run program?

.

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Experiment No: 2

Title: Block Transfer

Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _

Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff Member

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Experiment No: 2

Title: Block Transfer with string and without string

Aim: Write X86/64 ALP to perform non-overlapped and overlapped block

transfer (with and without string specific instructions). Block

containing data can be defined in the data segment

Prerequisite: Microprocessor Architecture

Objectives: To Study String related instruction used in program

To learn the logic to transfer a block

Theory:

The 80x86 String Instructions

All members of the 80x86 family support five different string

instructions: movs, cmps, scas, lods, and stos. They are the string

primitives since you can build most other string operations from these

five instructions. How you use these five instructions is the topic of the

next several sections

This sequence of instructions treats CharArray1 and CharArray2 as a

pair of 384 byte strings. However, the last 383 bytes in

the CharArray1 array overlap the first 383 bytes in

theCharArray2 array. Let's trace the operation of this code byte by byte.

When the CPU executes the MOVSB instruction, it copies the byte at

ESI (CharArray1) to the byte pointed at by EDI (CharArray2). Then it

increments ESI and EDI, decrements ECX by one, and repeats this

process. Now the ESI register points at CharArray1+1 (which is the

address of CharArray2) and the EDI register points at CharArray2+1.

The MOVSB instruction copies the byte pointed at by ESI to the byte

pointed at by EDI. However, this is the byte originally copied from

location CharArray1. So the MOVSB instruction copies the value

originally in location CharArray1 to both

locations CharArray2 and CharArray2+1. Again, the CPU increments

ESI and EDI, decrements ECX, and repeats this operation. Now the

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movsb instruction copies the byte from

location CharArray1+2 (CharArray2+1) to location CharArray2+2. But

once again, this is the value that originally appeared in

location CharArray1. Each repetition of the loop copies the next element

in CharArray1 [0] to the next available location in the C

charArray2 array. Pictorially, it looks something like that shown in

Figure 1 Copying Data Between Two Overlapping Arrays (forward

direction)

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The end result is that the MOVSB instruction replicates X throughout

the string. The MOVSB instruction copies the source operand into the

memory location which will become the source operand for the very next

move operation, which causes the replication.

If you really want to move one array into another when they overlap, you

should move each element of the source string to the destination string

starting at the end of the two strings as shown in

Figure 2 Using a Backwards Copy to Copy Data in Overlapping Arrays

Setting the direction flag and pointing ESI and EDI at the end of the

strings will allow you to (correctly) move one string to another when the

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two strings overlap and the source string begins at a lower address than

the destination string. If the two strings overlap and the source string

begins at a higher address than the destination string, then clear the

direction flag and point ESI and EDI at the beginning of the two strings.

If the two strings do not overlap, then you can use either technique to

move the strings around in memory. Generally, operating with the

direction flag clear is the easiest, so that makes the most sense in this

case.

You shouldn't use the MOVSx instruction to fill an array with a single

byte, word, or double word value. Another string instruction, STOS, is

much better for this purpose. However, for arrays whose elements are

larger than four bytes, you can use the MOVS instruction to initialize

the entire array to the content of the first element.

The MOVS instruction is generally more efficient when copying double

words than it is copying bytes or words. In fact, it typically takes the

same amount of time to copy a byte using MOVSB as it does to copy a

double word using MOVSD3. Therefore, if you are moving a large

number of bytes from one array to another, the copy operation will be

faster if you can use the MOVSD instruction rather than the MOVSB

instruction. Of course, if the number of bytes you wish to move is an

even multiple of four, this is a trivial change; just divide the number of

bytes to copy by four, load this value into ECX, and then use the

MOVSB instruction. If the number of bytes is not evenly divisible by

four, then you can use the MOVSD instruction to copy all but the last

one, two, or three bytes of the array (that is, the remainder after you

divide the byte count by four). For example, if you want to efficiently

move 4099 bytes, you can do so with the following instruction sequence:

lea( esi, Source );

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lea( edi, Destination );

mov( 1024, ecx ); // Copy 1024 dwords = 4096 bytes

rep.movsd();

movsw(); // Copy bytes 4097 and 4098.

movsb(); // Copy the last byte.

Using this technique to copy data never requires more than three

MOVSx instructions since you can copy one, two, or three bytes with no

more than two MOVSB and MOVSW instructions. The scheme above is

most efficient if the two arrays are aligned on double word boundaries. If

not, you might want to move the MOVSB or MOVSW instruction (or

both) before the MOVSD so that the MOVSD instruction works with

dword-aligned data (see Chapter Three for an explanation of the

performance benefits of double word aligned data).

If you do not know the size of the block you are copying until the

program executes, you can still use code like the following to improve the

performance of a block move of bytes:

lea( esi, Source );

lea( edi, Dest );

mov( Length, ecx );

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shr( 2, ecx ); // divide by four. if( @nz ) then // Only execute MOVSD if four or more bytes. rep.movsd(); // Copy the dwords. endif; mov( Length, ecx ); and( %11, ecx ); // Compute (Length mod 4). if( @nz ) then // Only execute MOVSB if #bytes/4 <> 0. rep.movsb(); // Copy the remaining one, two, or three bytes. endif;

On most computer systems, the MOVSD instruction provides about the

fastest way to copy bulk data from one location to another. While there

are, arguably, faster ways to copy the data on certain CPUs, ultimately

the memory bus performance is the limiting factor and the CPUs are

generally much faster than the memory bus. Therefore, unless you have a

special system, writing fancy code to improve memory to memory

transfers is probably a waste of time. Also note that Intel has improved

the performance of the MOVSx instructions on later processors so that

MOVSB operates almost as efficiently as MOVSW and MOVSD when

copying the same number of bytes. Therefore, when working on a later

x86 processor, it may be more efficient to simply use MOVSB to copy the

specified number of bytes rather than go through all the complexity

outlined above.

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Algorithm ALGORITHM FOR NON OVERLAPPING BLOCK

TRANSFER :-

1. Physical initialization of data segment.

2. Initialization of memory pointer to first element of

destination array.

3. Initialization of memory pointer to first element of

source array.

4. Initialize counter to no. of elements in source array.

5. Copy element in a source array pointed by source

memory pointer to a location in a destination array

pointed by destination memory pointer.

6. Increment source memory pointer by 1. Increment

destination memory pointer by 1 and decrement

counter by 1.

7. If (counter 0), goto step 5.

8. Terminate program and exit to DOS.

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ALGORITHM FOR OVERLAPPING BLOCK TRANSFER :-

(TYPE A : Latter half of source overlapped)

1. Physical initialization of data segment.

2. Initialization of source memory pointer to last element in source

array.

3. Initialization of destination memory pointer to last element in

destination array.

4. Initialize counter to no. of elements in source array.

5. Copy element in a source array pointed by source memory pointer to

a location in a destination array pointed by destination memory

pointer.

6. Decrement destination memory pointer, decrement source memory

pointer and decrement counter by 1.

7. If (counter 0), goto step 5.

8. Terminate program and exit to DOS.

ALGORITHM FOR OVERLAPPING BLOCK TRANSFER :-

(TYPE B : Prior half of source overlapped)

1. Physical initialization of data segment.

2. Initialization of memory pointer to first element of source.

3. Initialization of memory pointer to first element of destination.

4. Initialization of counter to no. of elements in source array.

5. Copy element in a source array pointed by source memory pointer to a

location in a destination array pointed by destination memory pointer.

6. Increment destination memory pointer, Increment source memory

pointer and decrement counter.

7. If (counter 0), goto step 5.

8. Terminate program and exit to DOS.

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.

Conclusion: Hence we have studied ALP to perform non-overlapped and

overlapped block transfer (with and without string specific

instructions).

Questions: 6) What are the interrupts used in above program. Explain in detail.

7) What is the assembler directives used in above program? 8) Explain the flag register of 8086 and 80386

microprocessor? 9) Define the logic used in above program? 10) Which string related instructions used and explain that

briefly?

.

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Experiment No: 3

Title: Conversion of Numbers

Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _

Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff Member

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Experiment No: 3

Title: HEX To BCD & BCD To HEX Conversion

Aim: Write 64 bit ALP to convert 4-digit Hex number into its equivalent

BCD number and 5-digit BCD number into its equivalent HEX

number. Make your program user friendly to accept the choice from

user for: (a) HEX to BCD b) BCD to HEX (c) EXIT.

Display proper strings to prompt the user while accepting the input

and displaying the result. (use of 64-bit registers is expected)

Prerequisites: Microprocessor Architecture

Objectives: To learn the conversion logic

To study

Theory:

BCD TO HEX CONVERSION

We are given a five digit BCD number whose HEX equivalent is to

be found i.e. 65535 whose HEX equivalent is to be found. First we

will find the Hex equivalent of 60,000. We will compare 60,000H

with 10,000H. Each time we compare a counter is decremented by

10,000 and we add 10,000 decimal (2710 Hex). Then we will find

the equivalent of 5000. Now we will compare 5000H with 1000H.

Each time we compare the counter decrements by 1000 and we add

1000 decimal (3E8 H). Then we find the equivalent of 500H by

comparing it with 100H. Each time counter decrements by 100 and

we add decimal 100 (64 H). Then we find equivalent of 30H by

comparing it with 10H. Each time counter decrements by 10 and we

add 10 decimal (0A H). Then, equivalent of 5 is 5H.

Finally, all the equivalents obtained are added to get the equivalent

of 65535

HEX TO BCD CONVERSION

We have a 4 digit Hex number whose equivalent binary number

is to be found i.e. FFFF H. Initially we compare FFFF H with

decimal 10000 ( 2710 H in Hex ). If number is greater than 10,000

we add it to DH register. Also, we subtract decimal 10,000 from

FFFF H, each time comparison is made. Then we compare the

number obtained in AX by 1000 decimal. Each time we subtract

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1000 decimal from AX and add 1000 decimal to BX. Then we

compare number obtained in AX by 100 decimals. Each time we

subtract 100 decimal from AX and add 100 decimal to BX to obtain

BCD equivalent. Then we compare number obtained in AX with 10

decimal. Each time we subtract 10 decimal from AX and we add 10

decimal to BX. Finally we add the result in BX with remainder in

AX. The final result is present in register DH with contains the

5th bit if present and register AX

Algorithm Algorithm For BCD to Hex Conversion Step I : Initialize the data segment. Step II : Load the MSB of word in register AX. Step III : Compare it with 0, if zero goto step VII else goto step IV. Step IV : decrement AX and initialize BX = 0000. Step V : add 10000 decimal to BX. Step VI : Jump to step III. Step VII : Load LSB of word in register AX. Step VIII : Compare it with 1000, if below go to step XII else go to step IX. Step IX : subtract 1000 H from AX. Step X : Add 1000 decimal to BX. Step XI : Jump to step VIII Step XII : Compare number in AX now with 100 H, if below go to step XVI, else go to step XIII. Step XIII : Subtract 100 H from AX. Step XIV : Add 100 decimal to BX. Step XV : Jump to step XII. Step XVI : Compare number in AX with 10H, if below go to step XX, else go to step XVII. Step XVII : Subtract 10 H from AX Step XVIII : Add 10 decimal to BX Step XIX : Jump to step XVI Step XX : Add contents of AX and BX. Step XXI : Display the result. Step XXII : Stop. Algorithm For Hex to BCD Conversion

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Step I : Initialize the data segment. Step II : Initialize BX = 0000 H and DH = 00H. Step III : Load the number in AX. Step IV : Compare number with 10000 decimal. If below go to step VII else go to step V. Step V : Subtract 10,000 decimal from AX and add 1 decimal to DH Step VI : Jump to step IV. Step VII : Compare number in AX with 1000, if below go to step X else go to step VIII. Step VIII : Subtract 1000 decimal from AX and add 1000 decimal to BX. Step IX : Jump to step VII. Step X : Compare the number in AX with 100 decimal if below goto step XIII Step XI : Subtract 100 decimal from AX and add 100 decimal to BX. Step XII : Jump to step X Step XIII : Compare number in AX with 10. If below goto step XVI Step XIV : Subtract 10 decimal from AX and add 10 decimal to BX.. Step XV : Jump to step XIII. Step XVI : Add remainder in AX with result in BX. Step XVII : Display the result in DH and BX. Step XVIII : Stop.

Conclusion: Hence we have studied the conversion of number from HEX to BCD

&BCD to HEX

Questions: 1) What are the interrupts used in above program. Explain in detail.

2) What is the assembler directives used in above program?

3) What is logic used to convert BCD TO HEX number?

4) What is logic used to convert HEX TO BCD number

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Experiment No: 4 Title: String Operation

Roll No:_ _ _ Batch:_ _ _ Date of Performance:_ _ /_ _/_ _ _ _ Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff Member

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Experiment No: 4

Title: String operations using near procedure

Aim: Write an assembly language program to perform the string

operations - LENGTH, REVERSE & To check for

PALINDROME.

Prerequisites:

Basic knowledge about String operations

Knowledge about procedure in ALP

Objectives:

1. To study basics of assembly language programming i.e. Software

development tools required commands to use them, format of alp,

assembler directives.

2. To study step in assembly language programming.

3. To study dos-debug to execute program and to check the results.

To study basic 8086 instruction and as interrupt instructions, addressing

modes.

Theory:

Near CALL and RET Operation When executing a near call, the processor does the following (see Figure 4.1): 1. Pushes the current value of the EIP register on the stack. 2. Loads the offset of the called procedure in the EIP register. 3. Begins execution of the called procedure. When executing a near return, the processor performs these actions: 1. Pops the top-of-stack value (the return instruction pointer) into the EIP register. 2. (If the RET instruction has an optional n argument.) Increments the stack pointer by the number of bytes specified with the n operand to release

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parameters from the stack. 3. Resumes execution of the calling procedure.

4.1

ASSEMBER DIRECTIVES USED:-

1. SEGMENT

2. ENDS

3. ASSUME

4. END

5. MACRO & ENDM

6. PROC & ENDP

LIST OF PROCESDURES USED:-

1. ACCEPT PROC

2. LENGTHS PROC

3. REVERSE PROC

4. PALIN PROC

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LIST OF MACROS USED:-

MACRO TO DISPLAY A STRING:-

DISP MACRO MESSAGE

MOV AH, 09H

LEA DX, MESSAGE

INT 21H

ENDM

Algorithm:

ALGORITHMS FOR PROCEDURE MAIN:-

1. Physical initialization of data segment

2. Display the following menu for user :-

**** STRING OPERATIONS ****

1. Accept the string

2. Length

3. Reverse

4. Palindrome

5. Exit

3. Accept the choice from user.

4. If (choice =1), then call to procedure „ACCEPT‟.

5. If (choice =2), then call to procedure „LENGTHS.

6. If (choice =3), then call to procedure „REVERSE‟.

7. If (choice =4), then call to procedure „PALIN‟.

8. If (choice =5), then go to step (10).

9. If (choice >5), then print message for invalid choice.

10. Exit to DOS

ALGORITHMS FOR PROCEDURE LENGTHS:-

1. Start

2. Accept the string from user.

3. Load the length of string in data register

4. Convert data in data register from HEX to DECIMAL.

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5. Display the Result

6. Stop.

ALGORITHMS FOR PROCEDURE REVERSE:-

1. Start

2. Initialize the source pointer at the start of the string.

3. Initialize the count with „length‟ of the string.

4. Add the length of string to the location of source pointer,

so that source pointer will point next to last character of

the string

5. Decrement the source pointer.

6. Display the character at pointed location.

7. Decrement the count.

8. If (count≠0), then go to step (5) else go to step (9).

9. Stop.

ALGORITHMS FOR PROCEDURE PALINDROME:-

1. Start

2. Initialize the source pointer at the start of the string & the

destination pointer to the last character of the string.

3. Initialize the count with length of the string

4. Shift the bits in „count right by one position to get half of

the length.

5. Compare the characters pointed by source pointer &

destination pointer. If they are equal, go to step (6) else go

to step (10).

6. Increment the source pointer & decrement the destination

pointer and decrement the count.

7. If (count≠0), then go to step (5) else go to step (8).

8. Print “STRING IS A PALINDROME……!”

9. Print “STRING IS NOT A PALINDROME……!”

10. STOP / RETURN.

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Conclusion:

Thus we implemented string operations using far procedure.

Questions:

Q. 1 Explain which instructions are used for string operations

in ALP

Q.2 Explain logic for the program.

Q.3 Explain What is procedure in ALP

Q.4 Explain NEAR procedure.

Q.5 Which interrupts are used in the program.

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Experiment No: 5 Title: String Operation Using far

procedure Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _ Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff

Member

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Experiment No: 5

Title: String operations using far procedure

Aim: Write an assembly language program to perform the string

operations using FAR procedure: - concatenation, substring, compare,

no. of words, no. of chars. no. of capital letters etc.

Prerequisites:

Basic knowledge about String operations

Knowledge about procedure in ALP

Objectives:

1. To study basics of assembly language programming i.e. Software development tools required commands to use them, format of alp, assembler directives.

2. To study step in assembly language programming.

3. To study dos-debug to execute program and to check the results.

4. To study basic 8086 instructions & interrupt instruction & addressing modes.

Theory:

Far CALL and RET Operation When executing a far call, the processor performs these actions (see Figure 4.1): 1. Pushes current value of the CS register on the stack. 2. Pushes the current value of the EIP register on the stack. 3. Loads the segment selector of the segment that contains the called procedure in the CS register. 4. Loads the offset of the called procedure in the EIP register. 5. Begins execution of the called procedure. When executing a far return, the processor does the following: 1. Pops the top-of-stack value (the return instruction pointer) into the EIP register. 2. Pops the top-of-stack value (the segment selector for the code segment being returned to) into the CS register.

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3. (If the RET instruction has an optional n argument.) Increments the stack pointer by the number of bytes specified with the n operand to release parameters from the stack. 4. Resumes execution of the calling procedure.

ASSEMBER DIRECTIVES USED:-

1. MACRO & ENDM

2. PROC & ENDP

3. EXTRN

4. PUBLIC

LIST OF PROCESDURES USED:-

1. ACCEPT PROC

2. CONCAT PROC

3. COMPARE PROC

4. SUBSTR PROC

5. NO_WORD PROC

6. NO_CHAR PROC

LIST OF MACROS USED:-

MACRO IS USED TO DISPLAY A STRING:-

DISP MACRO MESSAGE

MOV AH, 09H

LEA DX, MESSAGE

INT 21H

ENDM

ALGORITHMS:-

ALGORITHMS FOR PROCEDURE MAIN:-

1. Start

2. Physical initialization of data segment

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3. Display the following menu using macro :-

**** STRING OPERATIONS ****

1. Accept the string

2. Concatenation

3. Check for substring

4. Compare the strings

5. Number of words

6. Number of characters

7. Number of digits

8. Number of Capital characters

9. Exit

Select your option ::

4. Accept the choice from user.

5. If (choice =1), then call FAR procedure „ACCEPT‟.

6. If (choice =2), then call FAR procedure „CONCAT‟.

7. If (choice =3), then call FAR procedure „SUBSTR‟.

8. If (choice =4), then call FAR procedure „COMPARE‟.

9. If (choice =5), then call FAR procedure „NO_WORDS‟.

10. If (choice =6), then call FAR procedure „NO_CHAR‟.

11. If (choice =7), then call FAR procedure „NO_DIGIT‟.

12. If (choice =8), then call FAR procedure „NO_CAP‟.

13. If (choice =9), then Exit to DOS, terminating the

program.

14. If (choice!=9), repeat the steps (3), (4) & (5).

15. Stop.

ALGORITHMS FOR PROCEDURE ‘CONCAT’:-

1. Start

2. Initialization of pointer1 to first string & pointer2 to

second string.

3. Initialize the count1 & count2 to length of first &

second string respectively.

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4. Display the character pointed by pointer1.

5. Increment the pointer1 & decrement the count1.

6. If count1 is not zero, goto step (4).

7. Display the character pointed by pointer2.

8. Increment the pointer2 & decrement the count2.

9. If count2 is not zero, gotostep(7).

10. Stop.

ALGORITHMS FOR PROCEDURE ‘SUBSTR’:-

1. Start

2. Initialize the source pointer to main string & destination

pointer to substring.

3. Initialize the count1 & count2 to length of main string &

substring respectively.

4. Compare the characters pointed by source & destination

pointer.

5. If they are equal, goto step (6), else goto ( ).

6. Increment the source pointer & destination pointer.

Decrement the count1 & count2.

7. If (count2!=0), then goto step (4) else goto step (9).

8. Increment the source pointer & reinitialize the destination

pointer. Decrement the count1 & reinitialize the count2

&goto step (4).

9. Increment the count for number of occurrences.

10. If (count1!=0), then goto step (10) else goto step (12).

11. Reinitialize the destination pointer & count2 &goto step

(4).

12. If count for no. of occurrences of substring is „zero‟, then

print “NOT SUBSTRING”, else print “SUBSTRING” &

print the number of occurrences of string.

13. Stop.

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ALGORITHMS FOR PROCEDURE COMPARE:-

1. Start

2. Initialize the source pointer the source pointer to string1 &

destination pointer to string2.

Initialize the count1 & count2 to the length of string1 &

string2 respectively.

3. If length of string1 & string2 are not same, goto step (9).

4. Compare the characters pointed by source & destination

pointer.

5. If they are equal, goto step (6), else goto(9).

6. Increment the source pointer & destination pointer.

Decrement count1.

7. If (count1!=0), goto step (4), else goto (8).

8. Print “STRING ARE EQUAL……!” &goto (10).

9. Print “STRING IS NOT EQUAL……!”

10. STOP.

ALGORITHMS FOR PROCEDURE ‘NO_WORD’:-

1. Start

2. Initialize the source pointer to the given string & the

count to length of string.

3. Compare the character pointed by source pointer to “ “

(space).

4. If equal, increment the count for no. of words & increment

source pointer.

Else increment the source pointer, goto step (3) till

count!=0.

5. Print the no. of words.

6. STOP.

ALGORITHMS FOR PROCEDURE ‘NO_CHAR’:-

1. Start

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2. Initialize the source pointer to the given string & the

count to length of string.

3. Compare the character with „30H‟. If below, goto step (8).

If greater, goto step (4).

4. Compare the character with „39H‟. If below or equal,

„increment the count for no. of digits‟. If greater, goto step

(5).

5. Compare the character with „5AH‟. If below or equal,

„increment the count for no. of capital letters‟ & also

increment the count for no. of characters. If greater, goto

step (6).

6. Compare the character with „60H‟, If below or equal, goto

step (8). If

greater, goto step (7).

7. Compare the character with „7AH‟. If below or equal,

„increment the count for no. of characters‟.

8. Decrement the count and increment the source pointer

&goto step (9).

9. If count is not zero, goto step (3). Else goto step (10).

10. Display the result i.e. no. of words, no. of characters, no. of

capital letters.

11. STOP.

Conclusion:

Thus we implemented string operations using far procedure.

Questions:

Q. 1 Explain which instructions are used for string operations in ALP

Q.2 Explain logic for the program.

Q.3 Explain What is the Procedure in ALP

Q.4 Explain FAR procedure.

Q.5 Which interrupts are used in the program.

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Experiment No: 6 Title: Multiplication of Hexadecimal numbers. Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _

Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff

Member

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Experiment No: 6

Title: Multiplication of Hexadecimal numbers.

Aim: Write an 8086 assembly language program to perform the

multiplication of two 8 bit Hex numbers by

1) Successive Addition

2) Shift & Add Method

Prerequisites:

Knowledge about number system

Objectives:

1. To study basics of assembly language programming i.e. Software development tools required commands to use them,

format of alp, assembler directives.

2. To study step in assembly language programming.

3. To study DOS-DEBUG to execute program and to check the results.

4. To study basic 8086 instructions & an interrupt instruction & addressing modes.

Assember directives used:-

1. segment

2. ends

3. macro & endm

4. proc & endp

List of procesdures used:-

1. accept proc

2. succ proc

3. shift proc

List of macros used:-

macro used:-

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disp macro msg

mov ah, 09h

lea dx, msg

int 21h

endm

ALGORITHMS:-

ALGORITHMS FOR PROCEDURE MAIN:-

1. Start

2. Physical initialization of data segment

3. Display the following menu for user :-

**** MULTIPLICATION ****

1. Accept the numbers

2. Successive Addition

3. Shift & add method

4. Exit

Enter your choice::

4. Accept the choice from user.

5. If (choice =1), then call procedure „ACCEPT‟.

6. If (choice =2), then call procedure „SUCC‟.

7. If (choice =3), then call procedure „SHIFT‟.

8. STOP / Exit to DOS.

ALGORITHMS FOR PROCEDURE ‘SUCC’:-

1. Start

2. Copy the multiplicand in count register & copy the

multiplier in base register.

3. Add the content of base register with itself.

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4. Decrement the contents in count register.

5. If (choice !=0), then goto step (3)

6. Display the result in base register.

7. STOP / Exit to DOS.

ALGORITHMS FOR PROCEDURE ‘SHIFT’:-

1. Start

2. Get the LSB of multiplier.

3. Do the multiplication of LSB of multiplier with

multiplicand by Successive Addition Method.

4. Store the result in accumulator.

5. Get the MSB of multiplier.

6. Do the multiplication of MSB of multiplier with

multiplicand by successive addition method.

7. Store the result in base register. Shift the contents of base

register towards left by 4 bits.

8. Add the contents of accumulator & base register.

9. Display the result.

10. RETURN.

Conclusion:

Thus we performed multiplication using successive addition &

Shift & add Method

Questions:

Q. 1 Explain Logic for the program

Q. 2 Explain Successive addition process

Q.3 Explain Shift & rotate method

Q.4 What is macro?

Q.5 Which interrupts are used?

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Experiment No: 7 Title: NDP program for

mean, Variance, Standard Deviation

Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _

Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff

Member

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Experiment No: 7

Title: NDP program for mean, Variance, Standard Deviation

Aim: Write 8087ALP to obtain:

i) Mean ii) Variance iii) Standard Deviation

For a given set of data elements defined in data segment. Also display

result.

Prerequisites:

Knowledge about coprocessor

Objectives:

5. To study basics of assembly language programming i.e. Software

development tools required commands to use them, format of alp,

assembler directives.

6. To study step in assembly language programming.

7. To study DOS-DEBUG to execute program and to check the

results.

8. To study basic 8086 instructions & an interrupt instruction &

addressing modes

Theory:

1.a) Features of 8087: Fabricated using HMOS III technology and packaged in a 40-pin cerdip

package, 68- instructions, Instruction set includes both simple and complex floating point

instructions, By interfacing 8087 NDP with 8086 processor, programmer can

perform various powerful arithmetic floating point operations. e.g. add, sub, div, square root, logarithm etc.,

8087 support 7 data types: 16-, 32-, 64-bit integers, 32-, 64-, 80-bit floating point and 18-Digit BCD operands,

Having 8 X 80 bit individually addressable register stack Available in

5MHz (8087),

8MHz (8087-2) and

10MHz (8087-1), 7- built-in exception handling functions

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Compatible with IEEE floating point standard 754, The data information inside 8087 is always stored in temporary real

format (80-bit floating point representation) Use of 8087 in 8086/8088 system increases processing speed to perform

different mathematical operations required in CAM, numeric controllers, CAD or Graphics,

b) Architecture of 8087 co-processor

b) Programmers model of co-processor

c) Data types supported:

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d) Status Register:

e) Control Word

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f) Instruction of co-processor used in the assignment: FINIT: Initialise Co-processor FLDZ: Load zero on stack top FILD: Load Integer on stack FIDIV: Divide stack top by an integer value FIMUL: Multiply stack top by an integer value FST: Store stack top FADD: Add in stack top FBSTP: Store integer part of stack top in 10 byte packed BCD

format FMUL: Multiply stack top FSQRT: Square Root of Stack Top d) Concept of Mean: It is the average of numbers, Variance: It is the

average of squared difference from mean and Standard Deviation: It is square

root of variance. 2. Algorithms for program

A1: Algorithm for program to calculate mean i. Start ii. Initialise the co-processor iii. Load zero on stack top iv. Add data elements from data segment on top of stack v. Divide the result by count of elements added to get

mean vi. Display result message vii. Display result viii. Stop

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A2: Algorithm for program to find variance

i. Start ii. Initialise the co-processor ix. Load zero on stack top x. Add data elements from data segment on top of stack xi. Divide the result by count of elements added to get

mean xii. Store mean in the memory xiii. Load zero on stack top xiv. Load element on stack top and subtract the mean

from it and square the difference xv. Repeat step xiii to xiv for all elements xvi. Add all squares xvii. Divide the addition by count of elements xviii. Display result message iii. Display result iv. Stop

A2: Algorithm for program to find standard deviation

v. Start vi. Initialise the co-processor xix. Load zero on stack top xx. Add data elements from data segment on top of stack xxi. Divide the result by count of elements added to get

mean xxii. Store mean in the memory xxiii. Load zero on stack top xxiv. Load element on stack top and subtract the mean

from it and square the difference xxv. Repeat step xiii to xiv for all elements xxvi. Add all squares xxvii. Divide the addition by count of elements xxviii. Calculate square root xxix. Display result message vii. Display result viii. Stop

Conclusion:

Thus we calculated mean, variance & standard deviation

using 8087 microprocessor.

Questions:

Q1. Explain Logic for the program

Q.2 Explain interrupts which are used in program

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Q.3 Explain various instructions of NDP.

Q.4 Explain block diagram of 8087

Q.5 Explain control word.

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.

Experiment No:8(A)

Title: Study of DAC 0808.

Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _

Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff Member

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Experiment No: 8 (A) Title: Study of DAC 0808.

Aim: Write 8086 ALP to interface DAC and generate following

waveforms on oscilloscope, (i) Square wave - Variable

Duty Cycle and Frequency. (ii) Ramp wave - Variable

direction, (iii) Trapezoidal wave (iv) Stair case wave

Prerequisites:

Cathode Ray Display(CRO), 8255 Programmable Peripheral Interface, 8086

interfacing with 8255.

Objectives:

1. To understand the interfacing of DAC 0808 kit to 8086 kit, 2. To understand the operation of DAC 0808 to generate different waveforms.

Theory:

1. Performance parameters a. Resolution: This is the number of possible

output levels the DAC is designed to reproduce. This is usually stated as the number of bits it uses, which is the base two logarithm of the number of levels.

b. Maximum sampling rate: This is a measurement of the maximum speed at which the DACs circuitry can operate and still produce the correct output.

c. Monotonicity: This refers to the ability of a DAC's analog output to move only in the direction that the digital input moves

d. Settling time: settling time is the interval between a command to update (change) its output value and the instant it reaches its final value, within a specified percentage.

2. Different techniques of conversions: a. Binary weighted resistor D/A converter

b. R/2R Ladder D/A converter,

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3. Sources of errors in DAC: a. Differential Nonlinearity error: DNL error is

the difference between the ideal and the measured output responses for successive DAC codes. An ideal DAC response would have analog output values exactly one code (LSB) apart (DNL = 0).

b. Offset error: Offset error, often called 'zero-scale' error, indicates how well the actual transfer function matches the ideal transfer function at a single point. For an ideal data converter, the first transition occurs at 0.5LSB above zero. For a DAC, offset error is the analog output response to an input code of all zeros.

c. Gain error: indicates how well the slope of an actual transfer function matches the slope of the ideal transfer function. Gain error is usually expressed in LSB or as a percent of full-scale range (%FSR), and it can be calibrated out with hardware or in software. Gain error is the full-scale error minus the offset error.

4. Block Diagram of DAC 0808:

5. Pin Diagram & Features of DAC 0808

Pin Diagram

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Features:

o Relative accuracy: ±0.19% error maximum o Full scale current match: ±1 LSB typ o Fast settling time: 150 ns typ o Noninverting digital inputs are TTL and

CMOS compatible o High speed multiplying input slew rate: 8

mA/μs o Power supply voltage range: ±4.5V to ±18V o Low power consumption: 33 mW @ ±5V

1. Square wave – variable duty cycle and frequency.

We are asked to generate a square wave using DAC interface. To generate square

wave we will output FFH and then 00H on port A of 8255. The output of 8255

(port A) is compulsory connected to the DAC 0808. We also have to vary duty

cycle. Variation in Duty cycle will automatically change the frequency as:

Duty cycle = Ton / Ton + Toff = Ton / Tfrequency

According to output duty cycle requirement, we can change the Delay between the

two outputs FFH (for output high) and 00H (for output low.)

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2. Ramp Wave: variable direction.

We are asked to generate a ramp wave using DAC interface. To generate ramp

wave we will output 00 to FFH. If we want a ramp wave with reverse direction

then, we output in reverse manner. If we want ramp wave in forward direction, we

will initialize, al = 00H, otherwise AL = FFH for reverse direction

3. Trapezoidal Wave

A TRAPEZOIDAL wave looks like a sawtooth wave on top of a square or

rectangular wave. The leading edge of a trapezoidal wave is called the JUMP

voltage. The next portion of the wave is the linear rise or SLOPE. The trailing edge

is called the FALL or DECAY. A trapezoidal wave is used to furnish deflection

current in the electromagnetic cathode ray tube and is found in television and radar

display systems. Electromagnetic cathode ray tubes use coils for the deflection

system, and a linear rise in current is required for an accurate horizontal display.

The square or rectangular wave portion provides the jump voltage for a linear rise

in current through the resistance of the coil.

Apparatus: 8086 Microprocessor Kit, CRO, SMPS, Keyboard,

DAC 0808 Card, Interfacing Cables.

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Diagram:

Procedure:

Square wave Step 1 : Initialize 8255 Step 2 : Initialize latch Step 3 : Display 00 . Step 4 : Call delay Step 5 : Display FF. Step 6 : Call delay Step 7 : Goto step 3

Ramp wave 1. Initialize 8255 2. Initialize latch 3. Send 00 on port A 4. Display on CRO. 5. Increment the content by 1 6. Go to step 4

Program:

Square Wave:

MOV CX,1100

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MOV DX,8006

; Address of Control

Word Register

MOV AL,80H

OUT DX,AL

MOV DX,8000

;Address of Port A

XX: MOV AL,00H

OUT DX,AL

INT AAH

MOV AL,FFH

OUT DX,AL

INT AAH

JMP XX

Ramp Wave:

MOV CX,1100

MOV DX,8006

; Address of Control

Word Register

MOV AL,80H

OUT DX,AL

UP: MOV DX,8000

;Address of Port A

MOV AL,00H

XX: OUT DX,AL

INC AL

CMP AL,FFH

JNE XX

JMP UP

Triangular Wave:

MOV CX,1100

MOV DX,8006

; Address of Control

Word Register

MOV AL,80H

OUT DX,AL

MOV AL,00H

MOV DX,8000

;Address of Port A

XX: OUT DX,AL

INC AL

CMP AL,FFH

JB XX

BACK:OUT DX,AL

DEC AL

CMP AL,00H

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JA BACK

JMP XX

Trapezoidal Wave:

MOV CX,1100

MOV DX,8006

; Address of Control

Word Register

MOV AL,80H

OUT DX,AL

MOV DX,8000

;Address of Port A

BACK:MOV AL,00H

OUT DX,AL

INT AAH

A1: INC AL

OUT DX,AL

CMP AL,FFH

JNE A1

INT AAH

A2: DEC AL

OUT DX,AL

CMP AL,00H

JNE A2

JMP BACK

Conclusion:

Hence we have performed the practical to generate different waveforms using 8086

kit and DAC card.

Questions:

1. Discuss the organization and architecture of 8255 PPI with a functional

block diagram.

2. Explain various modes of operations of 8255PPI.

3. Explain in detail: Centronics Printer Parallel Interfacing using 8255.

4. Explain control word of 8255 for I/O mode and BSR mode.

5. Explain:

a. Resolution b. Maximum sampling rate c. Monotonicity d. Settling time

6. Explain with the diagram R/2R Ladder D/A converter

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7. List Sources of errors in DAC & explain

8. Draw & explain Block Diagram of DAC 0808

9. List the Features of DAC 0808

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Experiment No:8(B)

Title: Stepper Motor

Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _

Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff Member

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Experiment No: 8(B)

Title: Stepper Motor

Aim: Write 8086 ALP to rotate a stepper motor for

given number of steps at a given angle and in

the given direction of rotation based on the

user choice such as (i) If 'C' key is pressed -

clockwise rotation, (ii) If 'A' key is pressed -

anticlockwise rotation. (iii) If 'B' is pressed -

1/2 clockwise and Vz Anti-clock wise rotation,

(iv) If 'S' key is pressed - stop rotation. Also

write routines to accelerate and deaccelerate

the motor.

Prerequisites:

8255 Programmable Peripheral Interface, 8086 interfacing with 8255.

Objectives:

1. To understand 8086 interfacing with 8255

2. To understand stepper motor rotation in clockwise & anticlockwise direction.

Theory:

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A stepper motor (or step motor) is a brushless DC electric motor that divides a full rotation into a number of equal steps. The motor's position can then be commanded to move and hold at one of these steps without any feedback sensor (an open-loop controller), as long as the motor is carefully sized to the application. Stepping Modes The following are the most common drive modes. • Wave Drive (1 phase on) • Full Step Drive (2 phases on) • Half Step Drive (1 & 2 phases on) • Microstepping (Continuously varying motor currents)

In Wave Drive only one winding is energized at any given time. The stator is

energized according to the sequence A → B → A# → B# and the rotor steps from position 8 → 2 → 4 → 6. For unipolar and bipolar wound motors with the same winding parameters this excitation mode would result in the same mechanical position. The disadvantage of this drive mode is that in the unipolar wound motor you are only using 25% and in the bipolar motor only 50% of the total motor winding at any given time. This means that you are not getting the maximum torque output from the motor.

In Full Step Drive you are energizing two phases at any given time. The stator is energized according to the sequence AB → A#B → A#B# → AB# and the rotor steps from position 1 → 3 → 5 → 7 . Full step mode results in the same angular movement as 1 phase on drive but the mechanical position is offset by one half of a full step. The torque output of the unipolar wound motor is lower than the bipolar motor (for motors with the same winding parameters) since the unipolar motor uses only 50% of the available winding while the bipolar motor uses the entire winding.

Half Step Drive combines both wave and full step (1&2 phases on) drive modes. Every second step only one phase is energized and during the other steps one phase on each stator. The stator is energized according to the sequence AB → B → A#B → A# → A#B# → B# → AB# → A and the rotor steps from position 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8. These results in angular movements that are half of those in 1- or 2-phases-on drive modes. Half stepping can reduce a phenomena referred to as resonance which can be experienced in 1- or 2- phases-on drive modes.

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Figure: Unipolar & Bipolar Wound Stepper Motor

Apparatus: 8086 Microprocessor, Stepper Motor, Data

Cable, SMPS, Keyboard

Diagram:

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Procedure:

Clockwise Direction: 1. Move CX with 8000 i.e. address of Port A 2. Load AL with 80 i.e. control word of 8255 3. Move DX with 8006 i.e. address of control word register 4. Out AL on DX 5. Move AL with 00 6. Load DX with 8000 i.e. address of Port A 7. Out AL on DX 8. Move AL with 06 9. Out AL on DX 10. Move AL with 0C 11. Out AL on DX 12. Move AL with 09 13. Out AL on DX 14. Move AL with 03 15. Out AL on DX 16. Goto step 8 Anticlockwise Direction: 1. Move CX with 8000 i.e. address of Port A 2. Load AL with 80 i.e. control word of 8255 3. Move DX with 8006 i.e. address of control word register 4. Out AL on DX 5. Move AL with 00 6. Load DX with 8000 i.e. address of Port A 7. Out AL on DX 8. Move AL with 03 9. Out AL on DX 10. Move AL with 09 11. Out AL on DX 12. Move AL with 0C 13. Out AL on DX 14. Move AL with 06 15. Out AL on DX 16. Goto step 8

Program:

Clockwise Direction: MOV CX,8000 MOV AL,80 MOV DX, 8006 OUT DX,AL

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MOV AL,00 MOV DX,8000 OUT DX,AL AGAIN:MOV AL,06 OUT DX,AL INT AAH MOV AL,0C OUT DX,AL INT AAH MOV AL,09 OUT DX,AL INT AAH MOV AL,03 OUT D,AL INT AAH JMP AGAIN Anticlockwise Direction: MOV CX,8000 MOV AL,80 MOV DX, 8006 OUT DX,AL MOV AL,00 MOV DX,8000 OUT DX,AL AGAIN:MOV AL,03 OUT DX,AL INT AAH MOV AL,09 OUT DX,AL INT AAH MOV AL,0C OUT DX,AL INT AAH MOV AL,06 OUT D,AL INT AAH JMP AGAIN

Conclusion: Thus, we rotate a stepper motor for given

number of steps at a given angle and in the given direction.

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Questions:

1. What is a stepper motor? How it work?

2. Discuss the organization and architecture of 8255 PPI with a functional block

diagram.

3. Explain various modes of operations of 8255PPI.

4. Explain in detail: Centronics Printer Parallel Interfacing using 8255.

5. Explain control word of 8255 for I/O mode and BSR mode.

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Experiment No:9

Title: 8253/8254 with 3 counters

Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _

Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff Member

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Experiment No:9

Title: Study operation of 8253/8254 with 3 counters

Aim: Write 8086 ALP to program 8253 in Mode 0, modify the program for hardware retriggerable Mono shot mode. Generate a square wave with a pulse of 1 ms. Comment on the difference between Hardware Triggered and software triggered strobe mode. Observe the waveform at GATE & out pin of 1C 8254 on CRO.

Prerequisites: Interfacing of 8253 with 8086 Microprocessor

Objectives:

1. To understand the interfacing of 8254 kit to 8086 kit, 2. To understand the operation of 8254 IC in different modes.

Theory:

Features of programmable interval timer:

1. Three independent 16 bit down counter . 2. Counter can be programmed in 6 different programmable counter mode . 3. Counting facility in both binary or BCD no system . 4. Compatible with Intel and other up 5. Signal +5V supply. 6. 24 pin 01 p. 7. It is completely TTL compatible

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Pin Description: D0-D7 Data bus there are 8 bit bidirectional data bus lines ,connected to system data bus for data transfer between 8086 & 8254 used to select 254 IC. If CS=0 then 8254 will be active. RD Read This is activate low input signal used in co- ordination with A0-A1 to send data from appropriate counter to data lines. WR Write This is an active low i/p signal used in co-ordination with A0A to load counters or to initiate the counter. A0-A1 Address line these are i/p address lines used to distinguish different parts of 8254 such as counter 0, counter 1, counter 2, CW register

A1 A0 Selection

0 0 Counter 0

0 1 Counter1

1 0 Counter 2

1 1 CW Register

CLK0 -2 (Clock input ) These are clock i/p to 3rd counters . the pulses applied at these pins will be counted by respective counters. Gate0-2 (Gate Control) These are active high , input signals, used to allow external h/w used to control respective counters. OUT0-2 These are active high ,input Signals, used to allow external h/w used to control respective counter.

Control Word Register:

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Apparatus: 8086 Microprocessor, 8253(PIT), Cable with converter card,

SMPS, Keyboard.

Diagram:

Different modes of operation of 8254 with proper waveforms, 1. MODE 0 – Interrupt on Terminal Count

2. MODE 1: Hardware Retriggerable One Shot.

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3. MODE 2: Rate Generator

4. MODE 3: Square Wave Mode

5. MODE 4: Software Triggered Strobe

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6. MODE 5 : Hardware Triggered Strobe

Procedure:

Mode 0:

a. Initialize the CW with 10 i.e mode0 b. Move 04 in al .i.e counter c. OUT AL at port of counter 0. d. Move 00 in al e. Count it at counter 0 f. Terminate program.

Mode 1:

a. Initialize the CW with 12 i.e mode1 b. Move 03 in al .i.e counter c. OUT AL at port of counter 0. d. Move 00 in al e. Count it at counter 0

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Program:

f. Terminate program.

Mode 2: a. Initialize the CW with 14 i.e mode2 b. Move 04in al .i.e counter c. OUT AL at port of counter 0. d. Move 00 in al e. Count it at counter 0 f. Terminate program.

Mode 3: a. Initialize the CW with 16 i.e mode3 b. Load the count c. Move 00 in al d. OUT it at counter 0 e. Terminate program.

Mode 4

a. Initialize the CW with 18 i.e mode4 b. Load the count c. Move 00 in al d. OUT it at counter 0 e. Terminate program.

MOV AL,10 ;MODE 0 SET MOV DX,01E6 ;ADDRESS OF CWR OUT DX,AL MOV AL,04 ;COUNTER VALUE MOV DX, 01E0 ; ADDRESS OF COUNTER 0 OUT DX,AL MOV DX,01E6 IN AL,DX ;DELAY OR NOP IN AL,DX ;DELAY OR NOP MOV DX, 01E0 BACK:IN AL,DX CMP AL,00 JNZ BACK INT A5H

Conclusion: Thus we studied operation of 8253/8254 and 3 counters which work in 6 different modes. We implement the different waves of each mode.

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Questions: 1. Draw and explain the functional block diagram of 8253/8254. 2. Draw the control word register of 8253PIT 3. Explain: INT A5H 4. Explain the following instruction: JNZ CMP OUT IN 5. Mention the use of various modes of 8253? 6. What are the mode 0, 2, and 4 in 8253? Explain with the help of waveform? 7. With the help of neat timing diagram, explain the mode 0,1 and 2of 8253? 8. Draw the block diagram of 8254 timer. Also explain the control word format of 8253?

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Experiment No:10

Title: Study of 8279

Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _

Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff Member

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Experiment No:10

Title: Study of 8279

Aim: Write 8086 ALP to initialize 8279 and to display

characters in right entry mode. Provide also the

facility to display

• Character in left entry mode.

• Rolling display.

• Flashing display

Prerequisites: Interfacing of 8279 with 8086 Microprocessor

Objectives:

1. To understand the interfacing of 8279 kit to 8086 kit,

2. To understand the operation of 8279 IC in different modes.

Theory:

Features of Keyboard Display Interface: 1. Scans and encodes up to a 64-key keyboard. 2. Controls up to a 16-digit numerical display. 3. Keyboard has a built-in FIFO 8 character buffer to store the keyboard Entries and

an Interrupt signal with each Entry. 4. The display is controlled from an internal 16x8 RAM that stores the coded

display information.

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Pin Description: 1. A0: Selects data (0) or control/status (1) for reads and writes between

microprocessor and 8279. 2. BD: Output that blanks the displays. 3. CLK: Used internally for timing. Maximum is 3 MHz 4. CN/ST: Control/strobe, connected to the control key on the keyboard. 5. CS: Chip select that enables programming, reading the keyboard, etc. 6. DB7-DB0: Consists of bidirectional pins that connect to data bus on

microprocessor. 7. IRQ: Interrupt request, becomes 1 when a key is pressed, data is available. 8. OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least

significant nibble of display. 9. RD(WR): Connects to microprocessor's IORC or RD signal, reads data/status

registers. 10. RESET: Connects to system RESET. 11. RL7-RL0: Return lines are inputs used to sense key depression in the keyboard

matrix. 12. Shift: Shift connects to Shift key on keyboard. 13. SL3-SL0: Scan line outputs scan both the keyboard and displays.

Control Word Register:

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AI: Autoincrement AAAA: Specify the address of 16byte Display RAM

8279 Programmable Keyboard Display Interface,

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Apparatus: 8086 Microprocessor, Cable with converter card,

SMPS, Keyboard

Diagram:

Procedure:

1 Set a control word (10h) at control port address 01E2h. 2 Issue the clear command & Initialise 8279 in write display mode 3 Initialize counter CL to 05h 4 Set pointer BX to memory location 0132 which contains ASCII value of character

to be displayed 5 Call the delay routine 6 Send contents of memory location pointer by BX, decrement CL 7 Increment BX & decrement CL. 8 If CL ≠ 0 goto step 4 9 Return

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Algorithm for rolling display:

1 Start 2 Get command word format i.e initialize 8274 3 Send it to command port address. 4 Set pointer 5 Set counter in CL reg. 6 Get character & send it to data port. 7 Call delay procedure. 8 Increment counter decrement CL 9 If not zero goto step 6 10 Stop.

Program:

MOV AX,10FF MOV SP,AX ;INITIALIZE STACK SEGMENT PUSH CS POP AX MOV DS,AX MOV AL,10 ; INITIALIZE KEYBOARD & DISPLAY MOV DX,01E2 OUT DX,AL MOV AL,DF ; ISSUE CLEAR COMMAND OUT DX,AL MOV AL,90 ;INITIALIZE 8279 IN WRITE DISPLAY OUT DX,AL MOV CL,05H MOV BX,01E2 BACK:PUSH CX MOV CX,8000 INT AAH ;DELAY ROUTINE POP CX MOV AL,[BX] MOV DX,01E0 OUT DX,AL INC BX DEC CL JNZ BACK RET DB 89 ;”H” DB 86 ;”E” DB C7 ;”L” DB C7 ;”L” DB C0 ;”O”

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Conclusion: Thus we have performed rolling & stable mode display using 8279.

Questions:

1. Draw and explain the following 8279 commands:

(i) Keyboard/display mode set command

(ii) Read FIFO/sensor Ram command

2. Draw and explain the complete interface diagram between 8086 and 8279

keyboard/display controller with 4x4 keyboard matrix.

3. Explain the following terms related to8279:

(i) Two key lockout

(ii) N key Rollover

(iii) display Ram

(iv) FIFO status word

4. Explain the command word/control words of 8279?

5. What is a key Debounce?

6. Explain the software and hardware key debounce techniques in brief?

7. Draw and explain internal block diagram of 8279? Write 8086 instruction to

initialize8279?

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Experiment No:11

Title: Study of 8251

Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _

Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff Member

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Experiment No:11

Title: Study of 8251

Aim: Perform an experiment to establish communication between two 8251 systems A and B. Program 8251 system A in asynchronous transmitter mode and 8251 system B in asynchronous receiver mode. Write an ALP to transmit the data from system A and receive the data at system B. The requirements are as follows: Transmission: • message is stored as ASCII characters in the memory. • message specifies the number of characters to be transmitted as the first byte. Reception: • Message is retrieved and stored in the memory. • Successful reception should be indicated.

Prerequisites: Interfacing of 8251 with 8086 Microprocessor

Objectives:

1. To understand the interfacing of 8251 kit to 8086 kit, 2. To understand the operation of 8251 IC in different modes.

Theory:

8251 is a universal synchronous, asynchronous receiver transmitter IC. It is basically used for

i) Parallel to serial converter ii) Serial to parallel converter

8251 supports standard synchronous protocol with

i) 5-8 bit mode ii) Odd / even or no parity format generations deletion iii) Band rate from 01 to 192k. iv) Automatic break deleted handling v) False start bit deletion vi) It has built in rate generator

8251 supports synchronous protocol with:

i) 5-8 bit character format ii) Internal /external character format iii) Automatic synchronous in section iv) Band rate from DC to clk band

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Pin Description:

1. D0 - D7 - This is bidirectional data bus which receive control words and transmits data from the CPU and sends status words and received data to CPU.

2. RESET - A "High" on this input forces the 8251 into "reset status”. The min. reset width is six clock inputs during the operating status of CLK.

3. CLK - CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC.

4. WR - This is the "active low" input terminal which receives a signal for writing transmit data and control words from the CPU into the 8251.

5. RD - This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251.

6. C/D - This is an input terminal which receives a signal for selecting data or command words and status words when the 8251 is accessed by the CPU.

7. CS - This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses.

8. TXD - This is an output terminal for transmitting data from which serial-converted data is sent out.

9. TXRDY - This is an output terminal which indicates that the 8251 is ready to accept a transmitted data character.

10. TXEMPTY - This is an output terminal which indicates that the 8251 has transmitted all the characters and had no data character.

11. TXC - This is a clock input signal (Active Low) which determines the transfer speed of transmitted data. • In "synchronous mode," the baud rate will be the same as the frequency of

TXC. In "asynchronous mode", it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64 the TXC.

12. RXD - This is a terminal which receives serial data. 13. RXRDY - This is a terminal which indicates that the 8251 contains a character

that is ready to READ. • If the CPU reads a data character, RXRDY will be reset by the leading edge of

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RD signal. Unless the CPU reads a data character before the next one is received completely, the preceding data will be lost. In such a case, an overrun error flag status word will be set.

14. RXC - This is a clock input signal which determines the transfer speed of received data. • In "synchronous mode," the baud rate is the same as the frequency of RXC. In

"asynchronous mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC.

15. SYNDET/BD - This is a terminal whose function changes according to mode. • In “internal synchronous mode“, this terminal is at high level, if sync characters

are received and synchronized. • If a status word is read, the terminal will be reset. • In “external synchronous mode”, this is an input terminal. A "High" on this

input forces the 8251 to start receiving data characters. • In “asynchronous mode”, this is an output terminal which generates "high

level“ output upon the detection of a "break" character if receiver data contains a "low-level" space between the stop bits of two continuous characters.

• The terminal will be reset, if RXD is at high level. After Reset is active, the terminal will be output at low level.

16. DSR - This is an input port for MODEM interface. The input status of the terminal can be recognized by the CPU reading status words.

17. DTR - This is an output port for MODEM interface. It is possible to set the status of DTR by a command.

18. CTS - This is an input terminal for MODEM interface which is used for controlling a transmit circuit.

• The terminal controls data transmission if the device is set in "TX Enable" status by a command. Data is transmittable if the terminal is at low level.

19. RTS - This is an output port for MODEM interface. It is possible to set the status RTS by a command.

Mode instruction word

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Command Word

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Apparatus:

Two 8086 Microprocessor, Two Keyboards, Two SMPS, One Connector

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Diagram:

Procedure:

Transmitter Mode Instruction = 4E Command Instruction = 23 Receiver Mode Instruction = 4E Command Instruction = 24 Group A transmitter

1. Mov BX with 014F i.e. the address of memory where the data is stored 2. Mov DX with 9002 i.e. address of Control Word Register 3. Mov 4E in AL i.e initialize mode register 4. Out contents of AL on DX 5. Mov 23 in AL register i.e. command instruction 6. Out contents of AL on DX 7. Mov CX with counter value 05

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8. Mov DX with 9002 i.e. address of Control Word Register 9. In the value pointed by DX in AL register 10. And AL with 01 11. Compare AL with 01 12. Jump on not zero then goto step 8 13. Load the contents pointed by BX in AL register 14. Mov in DX 9000 i.e. data address 15. Out contents of AL on DX 16. Increment BX 17. Goto step 8. 18. Stop

Group B receiver

1. Mov SI with 014F i.e. the address of memory where the data is stored 2. Mov DX with 9002 i.e. address of Control Word Register 3. Mov 4E in AL i.e initialize mode register 4. Out contents of AL on DX 5. Mov 24 in AL register i.e. command instruction 6. Out contents of AL on DX 7. Mov CX with counter value 05 8. Mov DX with 9002 i.e. address of Control Word Register 9. In the value pointed by DX in AL register 10. And AL with 02 11. Compare AL with 02 12. Jump on not zero then goto step 8 13. Mov in DX 9000 i.e. data address 14. In contents of DX in AL 15. Mov AL in memory pointed bi SI 16. Increment SI 17. Goto step 8. 18. Stop

Program:

For Transmitter: MOV AX,10FF ;Initialize SP MOV SP,AX PUSH CS POP DS NOP NOP NOP MOV BX,014F MOV AL,00 MOV DX,9002

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OUT DX,AL MOV CX,02 DO1: LOOP DO1 OUT DX,AL MOV CX,02 DO2: LOOP DO2 OUT DX,AL MOV CX,02 DO3: LOOP DO3 MOV AL,40 OUT DX,AL MOV CX,02 DO4: LOOP DO4 MOV AL,4E OUT DX,AL MOV CX,02 DO5: LOOP DO5 MOV AL,23 ;Command Instruction OUT DX,AL MOV CX,05 LOOP1:MOV DX,9002 ;Address of control word register IN AL,DX AND AL,01 CMP AL,01 JNZ LOOP1 MOV AL,[BX] MOV DX,9000 ;point to data address OUT DX,AL INC BX LOOP LOOP1 INT A5H DATA:DB 11 DB 22 DB 33 DB 44 DB 55 For Receiver: MOV AX,10FF ;Initialize SP MOV SP,AX PUSH CS POP DS NOP NOP NOP MOV BX,014F MOV AL,00

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MOV DX,9002 OUT DX,AL MOV CX,02 DO1: LOOP DO1 OUT DX,AL MOV CX,02 DO2: LOOP DO2 OUT DX,AL MOV CX,02 DO3: LOOP DO3 MOV AL,40 OUT DX,AL MOV CX,02 DO4: LOOP DO4 MOV AL,4E OUT DX,AL MOV CX,02 DO5: LOOP DO5 MOV AL,24 ;Command Instruction OUT DX,AL MOV CX,05 LOOP1:MOV DX,9002 ;Address of control word register IN AL,DX AND AL,02 CMP AL,02 JNZ LOOP2 MOV DX,9000 IN AL,DX MOV [SI],AL INC SI LOOP LOOP2 INT A5H

Conclusion:

Thus we have implemented communication between transmitter A and receiver B.

Questions:

1. Differentiate between Synchronous and Asynchronous data transfer?

2. Explain the various programmable features of 8251?

3. Draw the command instruction format of 8251 and explain it.

4. Draw a block diagram of 8251and explain in brief.

5. Draw the mode instruction format of 8251 and explain it.

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Experiment No: 12

Title: TSR for SCREENSAVER

Roll No:_ _ _ Batch:_ _ _

Date of Performance:_ _ /_ _/_ _ _ _

Date of Assessment: :_ _ /_ _/_ _ _ _

Particulars Marks

Attendance (05)

Journal (05)

Performance (05)

Understanding(05)

Total (20)

Signature of Staff Member

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Experiment No: 12

Title: TSR Program For Screensaver

Aim: Write a TSR program in 8086 ALP to implement Screen Saver. Screen

Saver should get activated if the keyboard is idle for 7 seconds. Access the

video RAM directly in your routine

Prerequisites: Microprocessor Architecture

Objectives: To learn the TSR and ISR

To learn the DOS and BIOS

To learn the IVT ,software interrupts

Theory:

Most MS-DOS applications are transient. They load into memory,

execute, terminate, and DOS uses the memory allocated to the application

for the next program the user executes. Resident programs follow these

same rules, except for the last. A resident program, upon termination, does

not return all memory back to DOS. Instead, a portion of the program

remains resident, ready to be reactivated by some other program at a

future time. Resident programs, also known as terminate and stay resident

programs or TSRs, provide a tiny amount of multitasking to an otherwise

single tasking operating system. Until Microsoft Windows became

popular, resident programs were the most popular way to allow multiple

applications to coexist in memory at one time. Although Windows has

diminished the need for TSRs for background processing, TSRs are still

valuable for writing device drivers, antiviral tools, and program patches

INSTALLING A TSR

Although we‟ve already discussed how to make a program go resident,

there are a few aspects to installing a TSR that we need to address. First,

what happens if a user installs a TSR and then tries to install it a second

time without first removing the one that is already resident? Second, how

can we assign a TSR identification number that won‟t conflict with a TSR

that is already installed? This section will address these issues. The first

problem to address is an attempt to reinstall a TSR program. Although

one could imagine a type of TSR that allows multiple copies of itself in

memory at one time, such TSRs are few and far in-between. In most cases,

having multiple copies of a TSR in memory will, at best, waste memory

and, at worst, crash the system. Therefore, unless you are specifically

written a TSR that allows multiple copies of itself in memory at one time,

you should check to see if the TSR is installed before actually installing it.

This code is identical to the code an application would use to see if the TSR

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is installed, the only difference is that the TSR should print a nasty

message and refuse to go TSR if it finds a copy of itself already installed in

memory

REMOVING A TSR

Removing a TSR is quite a bit more difficult that installing one. There are

three things the removal code must do in order to properly remove a TSR

from memory: first, it needs to stop any pending activities (e.g., the TSR

may have some flags set to start some activity at a future time); second it

needs to restore all interrupt vectors to their former values; third, it needs

to return all reserved memory back to DOS so other applications can make

use of it. The primary difficulty with these three activities is that it is not

always possible to properly restore the interrupt vectors. If your TSR

removal code simply restores the old interrupt vector values, you may

create a really big problem. What happens if the user runs some other

TSRs after running yours and they patch into the same interrupt vectors

as your TSR? This would produce interrupt chains that look something

like the following:

Interrupt Vector TSR #1 TSR #1 Your TSR Original TSR

If you restore the interrupt vector with your original value, you will create

the following:

Interrupt Vector TSR #1 TSR #1? Original TSR

This effectively disables the TSRs that chain into your code. Worse yet,

this only disable the interrupts that those TSRs have in common with

your TSR. the other interrupts those TSRs patch into are still active. Who

knows how those interrupts will behave under such circumstances? One

solution is to simply print an error message informing the user that they

cannot remove this TSR until they remove all TSRs installed prior to this

one. This is a common problem with TSRs and most DOS users who

install and remove TSRs should be comfortable with the fact that they

must remove TSRs in the reverse order that they install them. It would be

tempting to suggest a new convention that TSRs should obey; perhaps if

the function number is 0FFh, a TSR should store the value in es:bx away

in the interrupt vector specified in cl. This would allow a TSR that would

like to remove itself to pass the address of its original interrupt handler to

the previous TSR in the chain. There are only three problems with this

approach: first, almost no TSRs in existence currently support this

feature, so it would be of little value; second, some TSRs might use

function 0FFh for something else, calling them with this value, even if you

knew their ID number, could create problem; finally, just because you‟ve

removed the TSR from the interrupt chain doesn‟t mean you can (truly)

free up the memory the TSR uses. DOS‟ memory management scheme (the

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free pointer business) works like a stack. If there are other TSRs installed

above yours in memory, most applications wouldn‟t be able to use the

memory freed up by removing your TSR anyway. Therefore, we‟ll also

adopt the strategy of simply informing the user that they cannot remove a

TSR if there are others installed in shared interrupt chains. Of course, that

does bring up a good question, how can we determine if there are other

TSRs chained in to our interrupts? Well, this isn‟t so hard. We know that

the 80x86‟s interrupt vectors should still be pointing at our routines if

we‟re the last TSR run. So all we‟ve got to do is compare the patched

interrupt vectors against the addresses of our interrupt service routines. If

they all match, then we can safely remove our TSR from memory. If only

one of them does not match, then we cannot remove the TSR from memory

1. The timer interrupt TYPE 8 is initiated by the system 18.2 times per

second. Using this information, For 5 Seconds Can Be Calculated as:

18.2*5 =91

2. The video RAM is distributed in 4 pages of size 2K bytes. The base address of each is Page0 – B800H Page1 – b900h

Page 2- ba00h

Page3 – bb00h

By default page 0 is activated. This means the data written to this page

will be seen on monitor.

3. To display the data in any other page, the respective page has to be

activated first using BIOS interrupt.

Interrupt 21h function used:

Initializes a CPU interrupt vector to point to an interrupt handling routine.

Call with: AH = 25H AL = interrupt number DS:DX = segment: offset of interrupt handling routine

Terminate and stay resident Call with: AH = 31H AL = return code DX = amount of memory to reserve (in paragraphs) Returns: Nothing

Get interrupt vector Call with: AH = 35H

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AL = interrupt number Returns: ES:BX = segment:offset of interrupt handler

Algorithm 1. INIT ROUTINE

a. Read vector for interrupt (Type 9) from IVT.

b. Save the vector (CS:IP) in memory variable OLDINT9

c. Write BASE:OFFSET of “keyboard ISR” for “TYPE 9”

entry in IVT.

d. Read vector for interrupt (Type 8) from IVT.

e. Save the vector (CS:IP) in memory variable OLDINT8

f. Write BASE:OFFSET of “TIMER ISR” for “TYPE 8”

entry in IVT.

g. Instruct DOS to make the ISR part of the resident in

memory.

2. Keyboard ISR:

a. Push all registers

b. Reset the counter

c. Activate page 0(video RAM)

d. Pop all registers

e. Transfer the control to original system ISR using OLDINT9

3. TIMER ISR

a. Push all registers

b. Increment the counter

c. Check the counter .If <=91 then go to next step else go to

step b

d. Activate page1 of video RAM

e. Write string str to video RAM page1

f. Pop all registers

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g. Transfer control to original system ISR using OLDINT8

Conclusion: Hence we have studied 8086 ALP to implement screen saver using TSR

Questions: 5) What are the interrupts used in above program. Explain in

detail.

6) What is the assembler directives used in above program?

7) Explain the flag register of 8086 and 80386 microprocessor?

8) Define the logic used in above program

9) How to run program?

10) What is IVT? Draw structure of IVT

.