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Lucas-Lehmer Primality TesterPresentation 8

March 22nd 2006

Team: W-4

Nathan Stohs W4-1

Brian Johnson W4-2

Joe Hurley W4-3

Marques Johnson W4-4

Design Manager:

Prateek Goenka

Overall Objective: Modular Arithmetic unit with a creative use

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Status• Finished

– Project Chosen– C simulations– Behavioral Verilog– Structural Verilog– Floor Plan– Schematics– Pathmill Simulation of Top Level

• In Progress– Layout– Layout Simulations

• To Do– More Layout/Simulations

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Transistor CountsModule Transistor Count

Count 2,664

Mod_Multiply 11,006

Mod_Add 1,168

Partial Products 8,676

Register 896

Sub_16 704

Compare 36

Mod_P 1,280

Register 896

Counter 266

FSM 700

Total 17,286

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Sub_16

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Shift Left

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Mod Add

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Mod Add Schematic

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Mod Add Simulation

127 + 68 Mod 127 = 69

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Block Area Estimates (Updated)

Module Area (μm2)

Count 13,200

Partial Product 38,000

Sub 16 3,500

Compare 200

ModP 5,600

Register 4,000

Mod_add 6,528

FSM 3,000

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Updated Floorplan

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Partial Product Progress

Blocks Instances Status

Sub16 3 DRC/LVS/sim

Shift Left 2 50% Layout

Shift Right 2 50% Layout

Mux16 2 DRC/LVS

Logic (~200 transistors)

1 0% Layout

FullAdder16 1 DRC/LVS

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Overall Status

Blocks Instances Status

Mod Add 1 DRC/LVS/sim

ModP (shifter) 1 50% Layout

Sub 16 1 DRC/LVS/sim

FSM/Count 1 0% Layout

Register 2 0% Layout

Compare 1 0% Layout

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What’s Next

• Continue Layout

• Continue Simulating Layout

• Power Estimations on Layout

• Change Design of Registers

• Optimize

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Questions?