1 Company Confidential Statement of Confidentiality Renesas Confidential Information The following material contains Renesas confidential and proprietary

1 Company Confidential

Statement of Confidentiality

Renesas Confidential Information

The following material contains Renesas confidential and proprietary information. No part of this document may be disclosed, printed, copied, or disseminated in any form or by any means, without prior permission from Renesas Electronics America, Inc.

Renesas Electronics America Inc.

Company Confidential

CSoC Sales TrainingProduct Introduction

Sudhir Mallya / Steven KawamotoCSoC Group / Computing and Communications BU

00000-A

Rev. 1.0June, 2010

Company Confidential3

Focus Segments Storage ASICs (USB3.0/SSD)


Storage ASIC (SSD / USB3.0)

MarketUSB3.0 Device Bridge ChipsEnterprise Class SSD Controller Chips (SATA Gen 3)

Solution(Value)

Optimized chip design with single vendor interface• One stop shop with IDM Value PropositionIP and IP customization: • USB 3.0, SATA Gen 3, PCIe, Flash I/F (ONFI), UHS-2• ARM, DDR 2/3, custom I/O buffer designComplement customer ASIC/COT resources

CompetitionASICs and COTs using Foundry ecosystem • Design House, IP Vendor, Foundry, Package and Test

AdvantagesUnparalleled leadership in USB 3.0Superior Leakage current in CB55-L vs. TSMC 65nmIntegrated and deep service level

Target Customers

Fabless Semiconductor and System Companies

ContactSteven Kawamoto, [email protected]: 508-935-2083, Mobile: 508-735-5275


Renesas SSD Experience

HDD

High SSDExpress Card

ReadChannel

Flash I/F

PCI-ex

SDCard

SATA+RC ⇒ HDD

SATA

USB3.0

USB3 Flash USB3 Bridge

Low-Mid SSD

SATA+Flash I/F ⇒ Low-Mid SSD

PCI-Exp+Flash I/F ⇒ High-end SSD

USB3.0+Flash I/F ⇒ USB 3.0 Flash

I/O+Flash I/F ⇒ SD Card

USB3.0+SATA/SD ⇒ USB 3.0 Bridge

1st Gen

2nd Gen

3rd Gen


USB3.0 Device Market

1st Wave Products (in 2009/10) Storage (Ex-HDD, Flash Drives, SSD )

2nd Wave Products : Flash based DSC, DVC Cell phone

DSCCell Phone

Storage

DVC

0

50,000

100,000

150,000

200,000

250,000

300,000

350,000

400,000

2009 2010 2011 2012 2013

Desktop & Mobile PC TAM Total w/ SuperSpeed USB

Unit Shipments in Thousands

Source: In-Stat, 7/09

PC TAM and USB 3.0 Penetration


USB3.0 ASIC Solution

Renesas is a world leader for USB3.0 solutions World’s first and only certified USB3.0 Host Controller since Sept’ 09

USB3.0 IP PHY + LINK + EPC Unparalleled interoperability with Renesas USB3.0 Host

Fully-equipped USB3.0 interoperability lab Design support

Design Service to Customize the IP Core

Simulation/Verification Support

Strong IP line up for target application segment SATA 3G (now), 6G (55nm) Flash I/O DDR 2/3 Video macros (DAC, HDMI, DVI)

All IPs are available in CB90M Technology


Renesas USB3.0 ASIC Solution

DDR IO(DDR2/3)User Defined

Logic

Renesas Macro

ARM sub system

ARM Core

SRAM

DMA Int Peri.

USB3.0 I/F

SATA / Flash IF / Video

USB3.0 PHY

USB3.0 LINK

USB3.0 EPC

User logic

User logic

User logic

Use

r Logic

DDRDDR

DDRDDRe-DRAM

HDDFlash

FlashFlash

Flash

Data buffer


Renesas ASIC Solution for Flash Controller

NAND-Flash Memory

Sub-System

DDR IO(DDR2/3)

Host System

ECC

USB 3.0 SATA Gen1/2/3

PCIe Gen1/2

Wear-levelingand

Re-mapping engine

SRAM

Flash I/F

User Defined Logic

Renesas IP

ARMPlatform

ARM Core

SRAM

DMA IntC

Peri.

Host I/F

Flash IOONFI IO

etc

eDRAMBuffering

Cache

Crypto engine

RSA SHA-1

AES DES

NVRAM(key store)

Flash controller ASIC

FlashFlash

FlashFlash

DDRDDR

DDRDDR

Data buffer

ARM Platform


SATA Gen 3: Superior Leakage Current CB-55L vs. TSMC 65nm


Application Customers & Targets

Target Customers

External HDD

Flash Drive, SSD

Display/Imaging

http://www.sandisk.co.jp/

http://www.smsc.com/index.html

http://www.seagate.com/www/ja-jp/

http://www.displaylink.com/index.html

http://www.idt.com/japan/index.html

http://www.siliconimage.com/index.aspx


Focus Segments Intelligent Buffer IC (IBIC)


IBIC Summary

Market High end smartphone, smartbook, tablet devices

Solution(Value)

Bridge chip (between host and display module) with eDRAM frame buffer to allow Host to go to sleep when refreshing still images to save system power.MIPI-DSI and MDDI In, RGB Out (DSI and LVDS Out in development).Currently supports up to WSVGA/WXGA resolutions & refreshes display at 60fps (or more).

CompetitionToshiba, Epson. At lower end (~WVGA), also Smart Driver IC’s (driver IC’s with RAM) and Application Processors with stacked DDR.

Advantages

vs Smart driver: Availability/lower cost @ >WVGA, & low powervs App Proc: System power savingsvs Epson: edram for lower powervs Toshiba: Lower power edram and edram experience

Target Customers

OEM: RIM, Motorola, Dell, Microsoft, AppleReference: Qualcomm, Intel, Marvell

ContactGreg Kasprzak, [email protected]: 508-935-2083, Mobile: 508-735-5275

mailto:[email protected]


Concept of Intelligent Buffer IC

Large e-DRAM capacity for higher resolution & quality

Lower system power with new backlight control

Meet mobile display interface standard

Intelligent display functions & 3D display extension

Realize Higher display quality & Low power for any Mobile Platform (DBB/Application chip)

Hos

t I/F

Frame Buffere-DRAM

Image Processing

PictureAnalysis

LCD

Driv

er IF

Brightness Calculation

Gammaadjustment

LEDDrive


Tremolo Standard Product Roadmap

CY2009 CY2010 CY2011

AGCPS-II Display Ctrl & Power

savingDual input IF

MIPI DSI-RXLarge Frame Buffer

Q3（ ES ） Q1 Q1Tremolo-S Tremolo-M Tremolo-2

WSXGA(WSVGA x 2)(3D: WSVGA)

Intelligent func.

Enhanced Display

DataCompress

MIPI

Tremolo-S Tremolo-M

MDDI

WSVGA/qHD(VGA x 2)

Intelligent func.

MIPI-DSI

WXGA/qHD( WSVGA x 2)

Intelligent func.

Display Cont.

DPI DPIMIPI-DSI

MIPI-DSI

Tremolo- ２

CY2012

LVDS/miniLVDS

Intelligent func.

Enhanced Display

DataCompress

MIPI MIPI-DSI

Tremolo-NextSensorControl

Tremolo-NextQ2

LVDSLVDS/

miniLVDSeDP

Pixel-data Codec3DLarge Display

High resolutionTouch panel Cont.

WSXGA(WSVGA x 2)(3D: WXGA)

Tremolo-Z


Tremolo-M Block Diagram

MIPIDSIRx

MIPIDSIRx

D0PD0N

D1PD1N

CLPCLN

MDDIClientMDDIClient

DD0PDD0N

DD1PDD1N

STPSTN

EngineIF

EngineIF

FrameBuffer

14.8MbeDRAM

FrameBuffer

14.8MbeDRAM

FrameBuffer

14.8MbeDRAM

FrameBuffer

14.8MbeDRAM

Memory ControlMemory Control

EngineControlEngineControl

TimingControlTimingControl

AGCPSAGCPS

MIPI-DPI(24bit RGB)

PWM(BL LED CTL)

DBITypeC

IF

DBITypeC

IF

GBRegGBReg

CLKIN PLLPLL system clkpixel clk

/RESET

TE

DBI TypeC

1.8V

VoltageRegulatorVoltage

Regulator

1.8V

1.2V

SEL_IF

AGCPS: Auto Gamma Control and Power Saving, which includes both CABC (Content Adaptive Backlight Control) and Ambient-light based Backlight Control

VSYNC. HSYNC

SLEEP

DEPCLK

Tremolo-S differences• 16Mbit edram• MIPI-DSI only In• AGCPS not included


Strategy and Promotion Plan

Tremolo-S & M Evaluation Boards Use for customer demos,

interoperability testing Demonstrates basic function, power

savings, and image quality enhancement

Customer meetings/demos Target Motorola, RIM, Qualcomm, Intel,

Microsoft, Apple, Dell

Promotion Quarterly MIPI Mtgs to develop

relationships with key industry players UNH-IOL MIPI-DSI “plugfest”

participation B/Feb, very successful (next Nov/10)

Tradeshows such as CES and MWC

FPGA board emulates MIPI DSI Host Ambient light

sensor

2Lane MIPI DSI Tremolo-MPWM signal for LED

backlight control

WVGA panel


Focus Segments Intel Power Management IC (PMIC)


PMIC Summary

MarketPMIC for Intel Moorestown and Oak Trail platformsHigh-end smartphone, handhelds, tablets, netbooks

Solution(Value)

Rapid, pain-free development PMIC Applications Center of Excellence / Collateral & Support Schematic and Layout reviewsMost robust and widely adopted solution

Competition Freescale and Maxim

AdvantagesBetter solution for large form-factors. Scalable to smartphone.Unique PMIC GUI

Target North American Customers

Major OEMs: Dell, HP, CiscoEmbedded Applications – Battery Mobile Capable• Early Adopters now, working w/ C&I disti for go-to-market plan

ContactPatrick Yu, [email protected] Kawamoto, [email protected]


PMIC for Intel Moorestown and Oak Trail Platforms

Platforms require PMIC solution

PMIC = Power Management IC

Intel Atom Roadmap


Target Applications

Moorestown Oak Trail

OS support:OS support:


PMIC Solution for Intel’s Moorestown PlatformIntel® Atom™ Processor Z6xx Series & Intel® Platform Controller Hub MP20

Intel Moorestown Platform(Launched May 4, 2010)

RenesasPMIC

OS Support:

Z6xx Series ------Z6xx Series ------

MP20 ------MP20 ------

Battery Charger &5V OTG Boost

DAC

VoltageRegulators

SPIRegister Map

AudioClass A, B, D

RTC

GPIO

CommSPI

Driver

USB/Adapter

RGB

Display

Comms

DDR2

PowerButton

Crystal

MIC Speaker Headphone

BatteryPack

TouchScreen

Sensor

Lincroft

Langwell

Briertown PMIC*

*Generic block diagram – does not show Renesas 2-chip partitioning


17 LDOs6 DC-DC Bucks1 DC-DC Buck/Boost

6 LDOs2 DC-DC Bucks1 DC-DC Boost

Ball-pitch = 0.5mm

TouchScreen

White LEDDriver

(BOOST)

BuckConverter

Buck Converter

RGBLED

Driver6 LDOs

AUDIO/ VOICE

Head Phone

SpeakerEarPiece

Micro -Phone

R

Micro -Phone

L

Bri ghtnes sC

ontrol

2 VID Controlled

BuckConverters

4 Buck Converters

17 LDOs

CH

AR

GE

R(D

C/D

C)

Ba

ttery

RTC

SPI

LincroftLangwell

SPI

Coulomb Counter

(Fuel Gauge)

RF Module(2G/3G, WiMAX,

WiFi, GPS, Bluetooth)

ADC

SPI

Interrupt

3 2.768 KHz

32.768KHz

Vibrator

VID (7bits)

Sideband I/FCHIP1 CHIP2

ImageSemsor

PCM/I2S

Thermometer

Light SensorMisc Analog Inputs

LCD Backlight

Camera Scene Illum

PD9975 PD9976

TouchScreen

White LEDDriver

(BOOST)

BuckConverter

Buck Converter

RGBLED

Driver6 LDOs

AUDIO/ VOICE

Head Phone

SpeakerEarPiece

Micro -Phone

R

Micro -Phone

L

Bri ghtnes sC

ontrol

2 VID Controlled

BuckConverters

4 Buck Converters

17 LDOs

CH

AR

GE

R(D

C/D

C)

Ba

ttery

RTC

SPI

LincroftLangwell

SPI

Coulomb Counter

(Fuel Gauge)

RF Module(2G/3G, WiMAX,

WiFi, GPS, Bluetooth)

ADC

SPI

Interrupt

3 2.768 KHz

32.768KHz

Vibrator

VID (7bits)

Sideband I/FCHIP1 CHIP2

ImageSemsor

PCM/I2S

Thermometer

Light SensorMisc Analog Inputs

LCD Backlight

Camera Scene Illum

PD9975 PD9976

195-pin, 8.5mm2 BGAμPD9975


UX4 CMOS (in production since’04)Process

NEC Part # Package



UX4 CMOS (in production since’04)Process

NEC Part # Package

Renesas PMICMoorestown: uPD9975 & uPD9976Oak Trail: uPD9975

Most widely tested, robust PMIC solutionUnique PMIC GUI & technical supportBetter tablet features than competitionOptimized Oak Trail PMIC planned


Overview of WW Design-insHeavily engaged in Asia

Green : Menlow UserBlue : ARM UserBlack : UnknownGrey : MRST Project cancelled

OEM = Original Equipment ManufacturersODM = Original Design ManufacturersIDH = Independent Design House

* Customers with PMIC_NDA signed Customers of Renesas Moorestown PMIC Customers of Freescale PMIC Customers of Maxim PMIC Customers of Renesas Oak Trail PMIC

China Taiwan Korea Japan N. America Europe

Intel MPG * Inventec * Ajantech * Sony * OpenPeak * EB *

ZTE * Compal * Samsung * Sophia Systems * Cisco * Archos *

BYD * Quanta * Ocosmos/UMiD* Toshiba * HP Aava Mobile *

NFS-China * Wistron * Yukjung * Dell Nokia

Huawei * Gemtek * LG Motorola * Sony-E

Lenovo * ECS * Pioneer

Aigo USI *

BorQs/FBW * BenQ *

Cynovo * Pegatron

Asustek

CCI *

Foxconn


Sales Call to Action – Intel PMIC Target Customers

Major OEMs: HP, Dell Moorestown and Oak Trail plans Embedded – Oak Trail Early Adopters

Media Phone Home Energy Industrial / Medical Tablets and PDAs Gaming Computer on Module


Working with CSoCOpportunity Guidelines


CBIC Design Win Target Business Guideline

1. CSOC focus segments -- Smart Grid, Storage (USB3.0/SSD)

Aggressively consider all opportunities regardless of LTR.

2. General CBIC business:

CB90 and older technologies: target $5M or greater LTR

CB40/CB55: target $20M or greater LTR

Besides LTR, each opportunity evaluated for– Design complexity– IP requirement/match– Schedule– Risk


Gate Array Sales Guidelines

Product Simple Complex

LTR Guideline*

$1M LTRMinimum $250K / year75% LTR confidence

$2M LTRMinimum $250K /year75% LTR confidence

Channel Guideline

Avnet or Rockwell only Avnet or Rockwell only

CMOS-N5 All masters -

CMOS-9HD All masters -

EA-9HD - All masters

CMOS-12M SOG Type masters(uPD66211-14)

Embedded RAM masters(uPD66201-10)

LTR Guideline is based on Renesas selling price = disti cost One way to meet the LTR guideline is to raise the Renesas selling price

Additional Guidelines to Renesas Sales: Avnet business stays with Avnet Renesas will continue to encourage customers to use the Avnet model. If >$3M LTR opportunity is Renesas-generated and customer prefers, can consider

direct model as a 2nd option


Working with CSoCASIC Opportunity Profile


Working with CSOC for CBIC & G/A Opps

Initial Opportunity Discovery by Sales Contact CSoC

Smart Grid – Sudhir Mallya Storage – Steven Kawamoto General CBIC

– East: Mark Fox– West: Sudhir Mallya

General Gate-Array:– Chris Tennant

CSOC ASIC Program Manager (PM) will manage: Technical Profile for ASIC project and opportunity evaluation Quote / Proposal creation ASIC Contracts Project Execution with CSoC Project Manager


Initial Opportunity Discovery by Sales

Complete CBIC Business Profile Form Business Items

Customer contact info Application Schedule Volumes Target price Key issues to win Competition

Technical Major IP cores (in order to prepare for a follow-up meeting) Obtain customer RFQ (if available) Others may be gathered in the follow-up meeting with CSoC and

customer

CBIC Profile Business R32

Please see “Attachments” for CBIC Profile Form


Technical Profile Details (Example)

= Do Not Write in this space = Required Entry = Optional Entry. This may change to yellow (required) based on other data entered

Mass Prod. DateProduct Life (years)

Creation DateCreated By

First NETLIST DateFinal NETLIST DateES Delivery DateRisk Prod. Date

Modified ByApplicationDesign Start Date

Modification Date

Customer NameASIC Name

Basic Information

Who filled this out and when, initially and most recently

When does customer start needing support

CN

Yr Qty1 Qty2 Qty3Volumes to Quote

Will be filled out by CSoC PM

For Power Estimate. Typical value is 15-30%

Include Everything built out of primitive gates

Used for Clock tree estimates and Power estimates

Effects technology, library, utilization, Power. Must have.

Domain Name Total Gate Count Including FF

Toggle Rate # FF Clock Freq (MHz)

FPGA Based Gate #

Logic DetailsNotes

Handy way to organize Clock Domain info by naming them, but this is optional

If this gate count came from an FPGA tool/library, indicate “yes”

How many of this group of IO?

In, Out, IO?

CMOS, SSTL2, Drive. Schmidt, etc? OK to enter DDR2, QDR, etc. We know what kind of buffers these specs use

IO clocking Freq. If it is DDR, please specify in Description info at left

Pick any identifier. A, B, C, 1, 2, 3 etc

Name Quantity Type Description Freq(MHz)

Input Duty Cycle

Output Duty Cycle

Max. SSO

SSO group

Output Load(pF)

I/O

UnitsWatts

Other:Watts

Watts

°C

LFM

Volts

Volts

Package Type # Pins? Pins

Pins

Special Package Requirements

Voltage(s) : Core Voltage(s) : I/O

Number of Signal Pins

Power Consumtion (Active) Limit (if Applicable)Power Consumption (Leakage) Limit (if Applicable)Ambient Temp RangeAirflow (Indicate Units)

Power Consumption (Active) EstimateSource of Above Estimate

Package & PowerItem

FPBGA, FCBGA, etc

Include power, test , etcFor Example, package standoff height

•These fields need to be filled out if this is an FPGA conversion

•The fields change color coding based on how various questions are answered

RTL Available for Analyses during RFQ?OtherOther

Other

Design Language (Verilog, VHDL)

Customer Signoff Expectation

Description of IP

Synthesis script avail? Completely Synchronous Design?Timing Constraints Avail?

Format

Alternative if "No"Programming Emulation Req.?

FPGA Compatable Pinout Required?

Yes FPGA Vendor/Part #FPGA Conversion to ASIC?

Test Bench/Vector Handoff

FPGA Conversion Questions. These only need to be answered in the case of an FPGA conversion project

Netlist Handoff

Async. Description

FPGA Package Type/Pin #FPGA Vendor IP included?

FormatExternal Reset Available?


Working with CSoCExample Proposal Example Quotation

Confidential

Internal Use Only


Working with CSoCExample Proposal

Please see “Attachments” for complete example proposalExample Quotation

Confidential


Working with CSoCASIC Contracts


ASIC Contract Flow

NDA SLA

Master

DTO Risk-PTO

APT Safety StockAgmnt

Repeat for new ASIC

projects/parts

LOA (w/ Design Owner)

Master Production

Agreement (w/ new party)

APT (w/ new

party)

Once everOnce per every projectOccasionally, as needed

Safety StockAgmnt

Project Kickoff

Form

Approval to Start Final

P&R

DSSS Post Layout Approval

ES Approval


ASIC Contracts Usage (1)Document AKA Purpose When Use What’s Next Comment Related Doc

Non-Disclosure Agreement

NDA Describes the confidential information to be protected, allowed uses and restrictions, and procedures for handling. Protects IP with legal measures against misuse.

When REA will provide any confidential info. Customer may initiate when disclosing confidential info to REA. Typically before RFQ receipt.

Exchange and identification of the confidential information

Initiate with REA’s form, which allows disclosures to our parent company. List expected disclosures for both parties. Include “REA ASIC libraries”.

-

Software License Agreement

SLA Allows customers the right to use the OpenCAD software in an REA design kit. It protects REA’s IP.

Typically during RFQ stage, or after quote if customer is interested.

REA provides the design kit, and “FLEXlm” license which allows multiple user access. (FLEXlm alone allows access, not the legal right to use).

NDA is required also to protect our libraries. Ensure that a project NDA includes “REA ASIC libraries”.

-

Standard Terms & Conditions

T’s&C’s Prior to execution of a Master, this specifies T’s&C’s.

All quotes or proposals prior to a Master.

Master, depending on the situation.

May help prevent issues later.

-

Document AKA Purpose When Use What’s Next Comment Related Doc Master Development & Production Agreement

Master or Contract or MDAPA

Sets basic business terms for NRE and MP between REA and a customer that will be paying for development (either an OEM or fabless design owner, or a disti when the design owner pays a disti who pays REA) & MP. Covers IP infringement, warranties, etc.

Only one master per customer. Prior to start of, and PO for, the first design project with a customer.

Usually tied to DTO for first design project at a customer.

Master alone is not sufficient, a DTO for design & APT for MP are needed. Master includes all T’s &C’s, so the separate Std T’s&C’s do not apply after execution.

-

Development Task Order

DTO Agreement between REA and customer covering initial specs, cost and deliverables for a new design. Think of it as an accepted quote. (Quote is the offer, DTO is the “acceptance”.)

Once per project. If concurrent new designs, multiple projects can be on a single DTO.

Get the NRE PO and bill the first milestone (assuming standard NRE billing milestones).

Necessary for NRE payments.

o Project Start Meeting Summary Form

o Design Specification Summary Sheet

o Approval to Start Final Place&Route

o Post Layout Approval

o ES Approval

Document AKA Purpose When Use What’s Next Comment Related Doc Risk Production Task Order

Risk-PTO

Puts 100% financial liability on customer for an order placed prior to ES approval.

When a customer wishes to place MP order prior to ES approval.

Get the Risk PO.

Without this, a customer receiving non-working ES could cancel the risk order.

o ES Approval

Letter of Authorization

LOA Design Owner authorizes REA to sell their part to another entity. The other entity is typically a CM or a Disti.

o Disti buys for credit reasons.

o Sub buys, to build boards or systems for design owner.

o Occasionally a design owner licenses some other party to buy.

Get the Master Production Agreement signed by the new licensee. CSoC may negotiate terms with the new entity, or may extend prices and other terms in place with the Design Owner.

Newly authorized entity usually does not have the rights to make any changes (including marking) nor to approve PCN’s

-

Master Production Agreement

Same Similar to Master except it excludes design.

After an LOA. Get the APT signed.

For a party who buys MP only, not NRE.

-

Annual Production Terms

APT Agreement between REA and customer on production pricing, delivery, cancellation, and reschedules

When the customer wants to place an MP order after ES approval.

Get the MP PO.

Typical term is 1 year, but there is a provision to automatically renew

-

Document AKA Purpose When Use What’s Next Comment Related Doc Vendor Managed Inventory (Safety Stock) Agreement

VMI or Buffer Agmnt

For REA to build and inventory (rather than ship) a specific amount of product that customer takes liability for.

o Suggest if customer has frequent upsides with little leadtime

o Customer requests it

A blanket PO is needed.

Often we do not charge for this but costs are involved, so don’t assume there is no charge.

-

Change Order Same For changes to any term of any of the above, except for a Master

Anytime REA or the customer requests a changed term.

Change PO Master changes require an amendment or new Master

-

Project Start Meeting Summary Form

Kickoff Form

Documents that development work has started

At end of kickoff meeting or conf call

Design center starts work

First standard cancellation milestone

-

Design Specification Summary Sheet

DSSS Documents agreed final specs of the design

Ideally at start but typically prior to tapeout

-

Approval to Start Final Place & Route

First Signoff

Documents entry into Clean Netlist (CN) phase

Functionality is done & timing ~90% met

Move from LN (Layout Netlist) to CN

Third standard cancellation milestone

-

Post Layout Approval

Second Signoff

Documents authorization to tapeout

All conditions for tapeout are met

Start Mask Making for ES

Fifth standard cancellation milestone

-

ES Approval Prototype Approval

Non-risk MP may begin

Agreement that ES meet spec

APT -


Working with CSoCWhere to find Collateral


Collateral

Technology/application information

www2.renesas.com/asic /tech /ibic

www.renesas.com/app

ASIC Opportunity Profile FormREA Intranet>NECEL Intranet>Services>Core

>Business Services>Forms and Policies

ContractsREA Intranet>NECEL Intranet>Services>Core

>Business Services>Forms and Policies


Summary & Request to Sales


Summary

Ideal platform for power conscious products Industry leading low-power CBIC, eDRAM and PMIC technologies

Variety of ASIC/ASCP solutions ARM CPU’s, eDRAM, peripherals and high speed interfaces Gate Arrays for quick time-to-market IBIC / PMIC

IDM Value Proposition: One Stop Shopping Providing Solutions, Design, IP, Fabrication, Packaging, Test, Quality,

Reliability, …

Failure Analysis

Design for TestDesign for Analysis

High ReliabilityQuality Control

Shipment

Failed Chips

Stressed TestHigh Fault Coverage

Feedback for Quality Improvement

Testing

ProductionDesignProcess

ChipPackage


Sales Call to Action

Develop account strategies to build customer relationships and create opportunities based on our values and solutions Smart Grid (ARM SOC & PLM-1) Storage CBIC (USB3.0, SATA Gen3 ) IBIC PMIC

Identify ASIC opportunities in non-target segments that align with our values Low-power Solutions eDRAM ARM-based SOCs Interface IP One-stop shop (IDM Value)

Renesas Electronics America Inc.Company Confidential


Addendum


Working with CSoCExample Proposal

Please see “Attachments” for complete example proposalExample Quotation

Confidential