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Adaptive On-Chip Test Strategies for Complex Systems

V. Stopjaková

Department of Microelectronics, STU Bratislava, Slovakia

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Electronics Industry Trends Achieved successful penetration

in different domains

Emergence of technology

• Greater complexity• Increased performance• Higher density• Lower power dissipation

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Market-Driven Products Meet user Quality requirements

satisfying users to buy products

Created an unprecedented Dependency market-driven products

Maintain competitive by providing: Greater Product Functionality Lower Cost Reduced Interval (time to market) Higher Reliability

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High Complexity: Mixed Systems A single chip:

Logic, Analog, DRAM blocks

Embed advanced blocks: FPGA, Flash, RF/Microwave

Others MEMS Optical elements

FPGAFPGA

DRAMDRAM

SRAM

LOGIC

FLASHFLASH

RF

Analog Analog

Logic

LOGICLOGIC

ANALOGANALOG

DRAMDRAM

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High Complexity: Mixed Systems

How to test the mixed chip?

With external test only - need multiple ATE for a single chip: Logic ATE, Memory ATE, Analog ATE (Double/Triple Insertion)

Need special ATE with combined capabilities

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High Complexity: External Test

External Test Data Volume can be extremely high (function of chip complexity)

Requires deep tester memory for scan I/O pins

Slow test with long scan chains

ExternalTest

Super ATE

Pattern GenerationPrecision Timing

DiagnosticsPower Management

Test Control

Very high pin countDeep memory

Slow serial SCAN

Logic

Mixed-Signal

Memory

I/Os & Interconnects

Source: LogicVision

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High Complexity: On-chip Test

Solution: Dedicated Built-In Test for embedded blocks

Tasks repartitioned into Tasks repartitioned into embedded test and embedded test and external test functionsexternal test functions

External Test

Standard Digital Tester

Limited Speed/

Accuracy

On-chipTest

Pattern GenerationResult Compression

Precision TimingDiagnostics

Power ManagementTest Control

Support forBoard-level Test

System-Level Test

Logic

Mixed-Signal

Memory

I/Os & Interconnects

Chip, Board or System

Source: LogicVision

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Technology motivation many CMOS defects escaping logic testing physical imperfections causing delay faults unmodeled faults (weak-1, weak-0)

Quality & Reliability of IC affected !

Conventional test methods not effective

New on-chip test methods have to be applied

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Supply Current Testing

IDD

t

faulty

IDDQ

IDDT

fault-freeNMOS

defect

PMOS

VDD

IDD

outin

Figure 1 Principle of the supply current testing

PASS/FAILreference

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IDDQ/T testing - realization Off-chip measurement by external equipment On-chip monitoring using Built-In Current (BIC)

monitors

Off-chip monitors:+ no additional chip area needed- slow measurement (decoupling capacitor)- small current masked by noise

BIC Monitors:+ sensitive, very fast and accurate+ applicable in on-chip methods- chip area overhead- CUT perturbation

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IDDQ testing crucial issues Pass/Fail limit setting

represents fault-free value of IDDQ current depends on number of factors: technology, type of

circuits,... if too high - defective circuits pass if too low - undesired yield decrease (false fault

detections)

Test vectors Measurement Hardware

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On-chip IDDQ Monitoring Principle

DUT

IDD

GND

VDD

GND’

Pass/Fail

+

-

Vref BICMSensing element

Figure 2 On-chip supply current testing

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Main requirements for on-chip current monitors

ability to sense high currents testing of low-voltage circuits a minimal number of extra pins design simplicity applicable for recent VLSI circuits

Monitor development focused on: effect on performance of the CUT area overhead testing speed accuracy and sensitivity

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Example of a quiescenton-chip monitor

based on CCII+ current conveyor IDD current measurement current comparison IDDQ sampling

Figure 3 Current conveyor based quiescent BIC monitor

CC

CUT

CCII+ D

CLK

VDD

VDD’ iref

iDD

Test

Pass/Fail

BIC Monitor

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BIC monitor layout

Figure 4 The core of the monitor layout

size of 1 bypass switch is

650m x 210m (80%)

total area of 0.22 mm2

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Evaluation results

resolution of 10nA Pass/Fail limit of 50nA (sensitivity) 1 MHz testing speed VDD degradation max.100mV area overhead of 0.22 mm2

ability to handle large CMOS IC

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Useful for Differential Analog Test

SENSOR

(Pass/Fail)

ANALOGOUTPUT

IDDVDD

VSS

Win Comp

Pass

IDDSENSOR

IDDSENSOR

References

ANALOGTEST

PATTERN

DynamicIDD Monitor

RIGHT SIGNAL CHANNEL

LEFT SIGNAL CHANNEL

Fully Differential Analog Block

Figure 5 Experimental BIC monitor usage in a new ABIST approach

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Current mirror IDD principle

I II

IMIR offsetDD

MP

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Figure 6 Current mirror principle of IDD monitoring

MN2MN1 PB

NB

IMIR

IDD

R MET

MP1 MP2IMP1

VDD VDD ’

IMP2

CUT

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Example of a transienton-chip monitor

Figure 7 Transient BIC monitor

CUTIMIRIDD

MS

C

D

Vref

Vmon

Test

Voffset

VDD

VDD’

CurrentMirror

BIC monitor

A

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Experimental digital chip

both BIC monitors integrated in BIC-MU BIC-MU implemented into a digital circuit a digital multiplier used as a CUT fabricated in 0.7m CMOS multiplier size 850m 850m area of BIC-MU is 0.24mm2 around 24% of the total chip area

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Figure 8 Layout of the experimental chip

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Versatility Problem of IDD Testing IDD testing proven very successful for digital circuits Dedicated fault class only Use in submicron technologies limited IDD testing for analog IC not straightforward

Large variety of analog IC Specifications and behavior unique Difficult to generalize analog tests Validation up to now done using functional criteria

Current consumption analysis using Neural Networks

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Artificial Neural Networks Approach

Current signature analysis for presence of abnormal (faulty) behavior

Massively parallel and distributed structures capable of adaptation

No explicit Pass/Fail limit formulation required Excellent versatility Accuracy and sensitivity Reduced number of TP (time to test)

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IDD analysis using ANN

IDD

time o

r freq

1, 0

0, 1(GO

OD

)(B

AD

)

Figure 9 ANN-based analysis of IDD

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Mathematical model

xP

bk

x1wk1

wkP

(uk)uk

yk

k

P

jjkjk bxwy

1

Figure 10 Mathematical model of an artificial neuron

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Activation function

0

0,2

0,4

0,6

0,8

1

1,2

-5,00 -2,50 0,00 2,50 5,00

u

(u)

Figure 11 Activation function with top and bottom decision levels

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ANN Classification of tested ICs

ANN with two outputs: n1, n2 Classification within top/bottom decision levels

n1 TDL & n2 BDL PASS

n1 BDL & n2 TDL FAIL

Otherwise Non Classified

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Analog DUT Example

Two-stage CMOS operational amplifier

A pulse used as input stimuli

Good patterns: technology parameters and temperature variations

Faulty behavior: basic defects injected

(GOS, DOP, SOP, DSS, GSS, GDS)

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Effect of the GOS Fault

Figure 12 Effect of the GOS faults on IDD signal in time and frequency domain

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Effect of the DSS Fault

Figure 13 Effect of the DSS fault on IDD signal in different domains

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ANN setup 660 tested power supply current waveforms 200 faulty patterns 460 fault-free patterns 32 input nodes various training set: 200, 100, 76, 50 and 26 various number of hidden units: 2, 6, 10, 14, 18, 22 top decision level: 0.9 bottom decision level: 0.1 10 independent measurements

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Classification results

6065707580859095

100

26 50 76 100 200

Size of Training Set

PC

C[%

]

2 HUs

10 HUs

22 HUs

Figure 14 Percent Correct Classification (PCC) for time domain

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Classification results(2)

Figure 15 Percent Correct Classification for frequency domain

75

80

85

90

95

100

26 50 76 100 200

Size of Training Set

PC

C[%

]

2 HUs

10 Hus

22 HUs

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Conclusions To ensure quality of SoC Technologies:

On-chip Test is added into the designs of embedded cores

New adaptive on-chip approaches needed for different test functions

On-chip current monitoring effective but not versatile and limited to CMOS digital circuit

ANN classification of defective IC ability of testing mixed-signal circuits ability of sensing negligible differences possibility to analyse other circuit’s parameters

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Thank YOU for your attention!