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MICROPROCESSOR PROGRAMMING

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UNIT 4: MICROPROCESSOR ROGRAMMING

INTRODUCTION:

This topics describe about

Data transfer instructions, Arithmetic instructions, Logic instructions, Shift and Rotate

instructions, Compare instructions, Jump instructions, Subroutines and subroutines handling

instructions, The Loop and loop handling instructions, Strings and strings handling

instructions.

The following topics are covered here :

4.1 Data transfer instructions.4.2 Arithmetic instructions

4.4 Shift Instructions

4.5 Rotate instructions

LEARNING OBJECTIVES:

The objectives of this topic are to:

1. Explain the operation of each instruction set with any applicable addressing mode.

LEARNING OUTCOMES:

After completed this module trainees should be able to :

1. Determine the use of different instruction

2. write a simple program using 8088/8086 instruction set

3. Explain the operation of the instruction set mnemonic.

4. Understand how programs function using this instruction set.

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IP

CSDSSSES

AXBXCX

DX

SPBPSIDI

Address Memory Instruction

01000 8C MOV DX,CS01001 CA01002 XX next instruction

01000200

XXXX

4.1 DATA TRANSFER INSTRUCTION

It provided to move data either between its internal register or between an internal registerand a storage location in memory. This group included :

1) Move byte / word ( MOV)

Eg : MOV DX , CS move the contents of CS into DX

2) Exchange byte / word ( XCHG )Eg : XCHG AX , DX exchange the contents of the AX and DX

3) Translate byte ( XLAT )

4) Load effective address ( LEA )Eg: LEA SI , EA load SI register with an offset address value

5) Load data segment ( LDS )Eg: LDS SI , [200H]

6) Load extra segment ( LES)

An example : MOV DX , CS - the effect of executing the register addressing mode MOVinstruction.

a) Before

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b) after

In this instruction, the code segment register is the source operand, and the data

register is the destination. It stands for move the contents of CS into DX That is,

(CS) (DX)

IP

CSDSSSES

AXBXCXDX

SPBPSIDI

Address Memory Instruction

01000 8C MOV DX,CS01001 CA01002 XX next instruction

01000200

0100

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4.2 ARITHMETIC INSTRUCTIONS

4.2.1 Addition

Addition takes many forms in the 8086/8088. In this section, we detail the use of ADD

for both 8- and 16-bit binary addition and the increment instruction, which adds I to the

contents of a register or a memory location.

Table 4.1 Addition instruction

Instruction Comment

ADD AL,BL AL becomes the sum of AL + BL

ADD CX, DI CX becomes the sum of CX + DI

ADD BL,44H BL becomes the sum of BL + 44H

ADD BX,35AFH BX becomes the sum of BX + 35AFH

ADD [BX],AL The data segment memory byte

addressed by BX becomes the sum

of the data segment memory byte

addressed by BX + AL

ADD CL,[BP] CL becomes the sum of the stack segment memorybyte addressed by BP + CL

ADD BX,[SI + 2] BX becomes the sum of the datasegment word addressed by SI + 2,plus the contents of BX

ADD CL, TEMP CL becomes the sum of CL plus the

data segment byte TEMP ADD BX,

TEMP[DI] BX becomes the sum of BX plus the

contents of the data segment array

TEMP plus offset DI

ADD [BX + DI],DL The data segment memory byte

addressed by BX + DI becomes the

sum of that byte plus DL

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4.2.1.1 Register Addition.

Example 4-1 provides a simple program illustrating the use of some of the register

addition instructions. Notice in this example that the 16-bit contents of registers BX, CX, and

DX are added to the contents of the AX register. Also note that after each addition, the

microprocessor modifies the contents of the flag register. It is very important to remember

that arithmetic and logic instructions always modify the contents of the flag register. An ADD

of any type affects the sign, zero, carry, auxiliary carry, parity, and overflow flags.

EXAMPLE 4-1

0000 03 C3 ADD AX,BX

0002 03 C1 ADD AX,CX

0004 03 C2 ADD AX,DX

4.2.1.2 Immediate Addition.

In Example 4-2, which illustrates an 8-bit immediate addition, the flag bits are depicted

along with their results. Here a 12H is first moved into register DL with an immediate

move: then a 33H is added to it with an immediate addition. After the addition, the sum

(45H) is placed in the DL register. As in all additions, the flags change, and in this

example they change as follows:

Z = 0 result not 0

C = 0 no carryA = 0 no half-carry

S = 0 result positive

P = 0 odd parity

0 = 0 no overflow

EXAMPLE 4-2

0006B2 12 MOV DL,12H

0008 80C2 33 ADD DL,33H

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4.2.1.3 Addition with Carry

An addition-with-carry instruction adds the bit in the carry flag (C) along with the operand

data. It is useful in the addition of numbers wider than 16 bits.

Table 4-5 illustrates a number of add-with-carry (ADC) instructions along with a

comment explaining the operation of each instruction. Like ADD, ADC also affects all the

flags.

Suppose that the 32-bit number held in the AX and BX registers is added to the 32-bit

number held in the CX and DX registers. This cannot be accomplished without adding a

carry, and it is here that an ADC instruction becomes useful. In Example 4-8, notice that the

least significant numbers in BX and DX are added with a normal ADD command. Of course,

the ADD command affects the carry flag, which holds the carry if it occurs. Next, the most

significant words are added, along with the carry produced from the prior addition. This

leaves 32-bit sum in registers AX and BX.

EXAMPLE 4-8

0039 03 DA ADD BX,DX

003B 13 C1 ADC AX,CX

TABLE 4-2 Add-with-carry instructions

Instruction Comment

ADC AL,AH AL becomes the sum of AL + AH + carry

ADC CX,BX CX becomes the sum of CX + BX + carry

ADC [BX],AL The data segment byte addressed by BX becomes the sum of thatbyte plus AL + carry

ADC BX,[BP + 2] BX becomes. the sum of the stack segment word addressed by BP+ 2 and the contents of both the BX register and carry

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4.2.2 Subtraction

In this section we detail the many forms of subtraction (SUB) available for both 8- and l6-bitbinary subtraction. We also include the decrement instruction, which is used to subtract a 1

from a register or memory location.

TABLE 4-3 Subtraction instructions

Table 4-3 provides a list of the addressing modes allowed for the SUB instruction.

These modes include all those mentioned in Chapter 2. In addition, there are well over

1,000 possible instructions. About the only things that cannot be subtracted are the

contents of any segment register or the contents of one memory location from another. Like

addition, subtraction also affects all the flag bits, and recall that the contents of the segment

registers may only be moved, pushed, or popped.

Instruction Comment

SUB CL,BL CL becomes the difference of CL -BL . SUB AX,SP

AX becomes the difference of AX SP

SUB DH,6FH DH becomes the difference of DH -6FH

SUB AX,OCCCCH AX becomes the difference of AX CCCCH

SUB [DI],CH The data segment memory byte addressed by DI

becomes the difference of the data segment byteaddressed by DI CH

SUB CH..[BP] CH becomes the difference of the stack segment

memory byte addressed by BP CH

SUB AH, TEMP AH becomes the difference of AH minus thecontents of memory byte TEMP located in the datasegment

SUB DI, TEMP[BX] DI becomes the difference of DI minus the contents

of data segment array TEMP plus offset BX.

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4.2.2.1 Register Subtraction.

Example 4-6 provides a simple program illustrating the use of some of the register

subtraction instructions. Note in this example that the 16-bit contents of registers CX and

DX are subtracted from the contents of the BX register. Also note that, after each

subtraction the microprocessor modifies the contents of the flag register, as does every

arithmetic and logic instruction.

EXAMPLE 4-6

0030 2B D9 SUB BX,CX

0032 2B DA SUB BX,DX

4.2.2.2 Immediate Subtraction.

In Example 4- 7, which illustrates an 8-bit immediate subtrac tion, the flag bits are depicted

along with their results. Here a 22H is first moved into register CH with an immediate move;

then a 44H is subtracted from it with an immediate ;, subtraction. After the subtraction, the

difference (DEH) is placed in the CH register, As with all subtractions, the flags change, and

in this example they change as follows:

Z = result not 0

C = I borrow

A = I half-borrow

S = 1 result negative

P = 1 even parity

0 = 0 no overflow

EXAMPLE 4-7

0034 BS 22 MOV CH,22H

0036 80 ED 44 SUB CH,44H

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Notice how the carry flags (C and A) both hold borrows rather than carries, as after an

addition. Also notice that there is no overflow condition. In this example, a 44H was

subtracted from a 22H with a result of DEH or a -34. Because the quantity -34 fits into an

8-bit number, there is no overflow in this example. An 8-bit overflow will occur only if theresult is outside the range + 127 to -128.

4.2.2.3 Subtraction with Borrow

A subtraction-with-borrow instruction allows the bit in the carry flag (C), which holds a borrow

for subtraction, to be subtracted along with the operand data. This type of instruction is

useful in subtracting numbers wider than 16 bits.

Table 4-6 illustrates a number of subtract-with-borrow (SBB) instructions along with a

comment explaining the operation of each instruction. Like SUB, SBB also affects all the

flags.

If the 32-bit number held in the AX and BX registers is subtracted from the 32-bit

number held in ill and SI, there must be some method of subtracting a borrow. This is where

the SBB instruction enters in. In Example 4-9, notice that the contents of BX are subtracted

from the least significant number in SI by the SUB instruction. This subtraction naturally

affects the carry flag, which holds a borrow if it occurs in the SUB instruction. Next, the most

significant words are subtracted, along with the borrow (SBB) produced from the prior

subtraction. This leaves a 32-bit difference in registers AX and BX.

TABLE 4-4 Subtract-with-borrow instructions.

Instruction Comment

SBB AH,AL AH becomes the difference of AH -AL carry

SBB AX,BX AX becomes the difference of AX -BX carry

SBB CL,3 CL becomes the difference of CL -3 -carry

SBB[DI],AL The data segment byte addressed by DI becomes the difference ofthat byte minus AL -carry

SBB DI,[BP + 2] DI becomes the difference of the stack segment word addressed byBP + 2 and the contents of both the DI register and carry

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EXAMPLE 4-9

003D 2B DE SUB BX,SI

003F IB C7 SBB AX, BX

4.2.3 Multiplication

The 8088 is capable of performing both 8 and 16 bit multiplication on either signed or

unsigned numbers.

4.2.3.1 8 bit multiplication

In 8 bit multiplication , whether signed or unsigned , the multiplicand is always in the AL

register. Table below for 8 bit multiplication instruction

TABLE 4-5 8-bit multiplication instructions

Instruction Comment

MUL CL The unsigned number in AL is multiplied by CL; the productis found in AX

IMUL DH The signed number in AL is multiplied by DH; the product isfound in AX

IMUL BYTE PTR[BX] The signed number in AL is multiplied by the byte stored inthe data segment at the address indexed by BX; the productis found in AX

MUL TEMP The unsigned number in AL is multiplied by the 8-bit numberat memory location TEMP; the product is found in AX. (Notethat here the memory location TEMP is defined as an 8-bitlocation.)

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EXAMPLE 4-10MOV BL , 5

MOV CL , 10

MOV AL , CL

MUL BL

The contents of DX is 50

MOV DX , AX

4.2.3.2 16 Bit multiplication

Word multiplication is very similar to byte multiplication. The AX register always contains

the 16-bit multiplicand, and the DX and AX registers contain the 32-bit product. DX will

always contain the most significant 16 bits ofthe product, and AX the least significant 16

bits. As in 8-bit multiplication, the location and choice of the operand is left to the

programmer. Table 4-9 depicts some 16-bit multiplication instructions.

TABLE 4-6 16 bit multiplication instruction

Instruction Comment

MUL CX The unsigned number in AX is multiplied by CX; the product

is found in DX and AX

IMUL DI The signed number in AX is multiplied by DI; the product isfound in DX and AX

MUL WORD PTR[SI] The unsigned number in AX is multiplied by the 16- bit

number in the data segment at the memory address pointed

to by SI; the product is found in DX and AX

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EXAMPLE 4-11

MOV BX , 0805H

MOV AX , BX

MOV CX , 0604H

MUL CX

4.2.4 Division

Like multiplication, division in the 8086/8088 can also occur on 8-bit or 16-bit numbers that

are either signed or unsigned .

4.2.4.1 8-Bit Division

The dividend for an 8 bit division is located in the AX register and the divisor is the

operand selected for the instruction. The result of an 8 bit division are two 8 bit number ,

the quotient ( AL ) and the remainder ( AH ).

DIV BL = ( AX )BL

= ( AH ) ( AL )

Remainder Quotient

Table 4-7 below for 8 bit division instruction

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TABLE 4-7 8 bit division instruction

EXAMPLE 4-12

0050 BO 12 MOV AL,12H

0052 B1 03 MOV CL,3

0054 B4 00 MOV AH,O

0056 F6 F1 DIV CL

Instruction Comment

DIV CL The unsigned number in AX is devided by CL; the

Quotient is in AL and the remainder is in AH.

IDIV BL The signed number in AX is devided by BL; the quotient is inAL and the remainder is in AH.

DIV BYTE PTR [ BP] The unsigned number in AX is devided by the byte in thestack segment stored at the address located by BP; thequotient is in AL, and the remainder is in AH.

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4.2.4.2 16 bit division

The DX register contains the most significant part of the dividend and the AX

register the least significant part . After the division the quotient is found in AXand the remainder in DX.

DIV BX = ( DX , AX )BX

= ( DX ) ( AX )

Remainder Quotient

Table 4-8 below for 16 bit division instruction

TABLE 4-8 16 bit division instruction

Instruction Comment

DIV CX The unsigned number in DX and AX is divided by CX; thequotient is in AX and the remainder is in DX.

IDIV SI The signed number in DX and AX is divided by SI; thequotient is in AX and the remainder is in DX

DIV DATA The unsigned number in DX and AX is divided by the wordstored in the data segment at memory location DATA ( aword of information )

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EXAMPLE 4-12

MOV AX , 3E14H

MOV DX , 0030H

MOV BX , 0805H

DIV BX

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4.3 LOGIC INSTRUCTIONS

The 8088 has instructions for performing the logic operations AND, OR, exclusive-OR

and NOT.

A common use of logic instruction is to mask a group of bits of a byte or word of data..

Mask means to clear the bit or bits to 0.

When a bit is Anded with another bit that is at logic 0, the result is always be 0.

If a bit is ANDed with a bit that is logic 1, its value remain unchanged.

The AND,OR, and XOR instructions perform their respective logic operations bit by bit

on the specified source and destination operands,the result being represented by the

final contents of the destination operand as shown in fig. 4.3(a)

Mnemonic Meaning Format Operation Flag affectedAND

OR

XOR

NOT

Logical AND

Logical Inclusive-OR

Logical Exclusive -OR

Logical NOT

AND D,S

OR D,S

XOR D,S

NOT D

(S). (D)(D)

(S)+(D) (D)

(S) + (D) (D)

(D) (D)

OF,SF,ZF,PF,CF,AFundefined



None

Figure 4.3(a) Logic instruction

Figure 4.3(b) shows the allowed operand combinations for the AND,OR, and XOR

instructions.

Figure 4.3(b)

Destination SourceRegisterRegisterMemoryRegisterMemoryAccumulator

RegisterMemoryRegisterImmediateImmediateImmediate

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For example, the instruction

AND AX,BX

Causes the contents of BX to be ANDed with the contents of AX. The result is reflected by

the new contents of AX. For instance, if AX contain 1234H and BX contains 000FH, the

result produced by the instruction is

1234H . 00FFH = 00010010001101002 . 00000000000011112

= 00000000000001002

= 000416

This result is stored in the destination operand and gives

(AX) = 0004H

Note that the 12 most significant bits are all zero. In this way we see how the AND

instruction is used to mask the 12 most significant bits of the destination operand.

The NOT logic instruction differs from those for AND,OR and exclusive OR in that it

operates on a single operand.

Figure 4.3 ( c) shows the allowed operands for the NOT instruction

DestinationRegisterMemory

Figure 4.3(c)

This operand can be the contents of an internal register or a location in memory.

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EXAMPLE 4.15

Describe the results of executing the following sequence of instructions:

MOV AL, 01010101BAND AL, 00011111BOR AL, 11000000BXOR AL, 00001111BNOT AL

Here B is used to specify a binary number.

SOLUTION:

The first instruction moves the immediate operand 010101012 into the AL register.

This loads the data that are to be manipulates with the logic instructions. The next

instruction performs a bit-by-bit AND operation of the contents of AL with immediate

operand 000111112. This gives

010101012 . 000111112 = 000101012

This result is placed in destination register AL:

(AL) = 000101012 = 1516

Note that this operation has masked off the three most significant bits of AL.

The Third instruction performs a bit-by bit logical OR of the present contents of Al

with immediate operand CO16. This gives

000101012 + 110000002 = 110101012

(AL) = 110101012 = D516

This operation is equavalent to setting the two most significant bits of AL.

The fourth instruction is an exclusive OR operation of the contents of AL with

immediate operand 000011112. We get

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110101012 000011112 = 110110102

(AL) = 110110102 = DA16

Note that this operation complements the logic state of those bit in Al that are 1s in the

immediate operand.

The last instruction, NOT AL, inverts each bit of AL. Therefore, the final contents of

Al become

(AL) = 110110102 = 001001012 = 2516

These result are summarized in fig. 4.3 (d)

Instruction (AL)MOV AL, 01010101BAND AL, 00011111BOR AL, 11000000BXOR AL, 00001111BNOT AL

0101010100010101110101011101101000100101

+

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4.4 SHIFT INSTRUCTION

There are four type of shift instruction in 8088, they are:

1) Shift Logical left (SHL)

2) Shift arithmetic left (SAL)

3) Shift logical right (SHR)

4) Shift arithmetic right (SAR)

The logical shift instructions, SHL and SHR are describe in fig. 4.4(a)

Mnemonic Meaning Format Operation Flag affectedSAL/SHL

SHR

SAR

Shiftarithmeticleft/shiftlogical left

Shift logicalright.

Shift

arithmeticright

SAL/SHLD,Count

SHR D,Count

SAR D,Count

Shift the (D) left bythe number of bitpositions equal tocount and fill thevacated bits

positions on the rightwith zeros.

Shift the (D) right bythe number of bitpositions equal tocount and fill thevacated bit positionson the left with zeros.

Shift the (D) right by

the number of bitpositions equal toCount and fill thevacated bit positionson the left with theoriginal mostsignificant bit.

CF,PF,SF,ZFAF undefinedOF undefined ifcount 1

CF,PF,SF,ZFAF undefinedOF undefined ifcount 1

SF,ZF,PF,CF

AF undefinedOF undefined ifcount 1

Figure 4.4(a) Shift instructions

The destination operand, the data whose bit are to be shifted, can be either the contents of an

internal register or a storage location in memory.

Destination CountRegisterRegisterMemoryMemory

1CL1

CL

Figure 4.4(b) Allowed operand

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The source operand can be specified in two ways. if it is assigned the value of 1, a 1-bit shift will take place.

Executing

SHL AX,1

Causes the 16-bit contents of the AX register to be shifted 1-bit position to the left.

Here we see that the vacated LSB location is filled with zero and the bit shifted out of the

MSB is saved in CF as illustrated in fig. 4.4 (c)

Before

AX Bit 15 Bit 00 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

After

AX0

CF Bit 15 Bit 0

Figure 4.4 (c) Results of executing SHL AX,1

If the source operand is specified as CL instead of 1, the count in this register

represents the number of bit positions the contents of the operand are to be shifted.

This will permits the count to be defined under software control and allows a range of

shifted from 1 to 255 bits.

An example of an instruction specified in this way is

SHR AX, CL

Assuming that CL contains the value 02H, the logical shift right that occurs is shown in figure4.4(d).

0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 00

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Before

AX Bit 15 Bit 0

0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

After

AX

Bit 15 Bit 0 CF

Figure 4.4 (d) Results of executing SHR AX, CL

Note that the two MSB have been filled with zeros and the last bit shifted out at the

LSB, which is zero, is placed in the carry flag.

In an arithmetic shift to the left, SAL operation, the vacated bits at the right of the

operand are filled with the value of the original MSB of the operand.

In an arithmetic shift to the right, the original sign of the number is maintained.

This operation is equivalent to division by power of 2 as long as the bits shifted out of

the LSB are zeros.

EXAMPLE 4.16

Assume that CL contains 02H and AX contains 091AH. Determine the new contents of AX

and the carry flag after the instruction.

SAR AX, CL is executed.

SOLUTION:

Since CL contains 02H, a shifted right by two bits locations take place, and the original sign

bit, which is logic 0, is extended to the vacated bit positions. The last bit shifted out from the

LSB location is placed in CF. This makes CF equal to 1. Therefore, the results produced by

execution of the instruction are

0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0

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(AX) = 0246H and CF = 12

Before

AX Bit 15 Bit 00 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0

After

AX

Bit 15 Bit 0 CF

Figure 4.4( e) Results of executing SAR AX, CL

0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1

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4.5 ROTATE INSTRUCTIONS

Similar to the shift instruction

There are four types of rotate instructions:

1) Rotate left (ROL)

2) Rotate right (ROR)

3) Rotate left through carry (RCL)

4) Rotate right through carry (RCR)

Mnemonic Meaning Format Operation Flags affected

ROL

ROR

RCL

RCR

Rotate left

Rotate right

Rotate left

through carry

Rotate rightthrough carry

ROL D,Count

ROR D,Count

RCR D, Count

RCR D,Count

Rotate the (D) left by thenumber of bit positionsequal to count. Each bitshifted out from theleftmost bit goes back intothe rightmost bit position.

Rotate the (D) right by thenumber of bit positionsequal to count. Each bitshifted out from therightmost bit goes into theleftmost bit position.

Same as ROL except carryis attached to (D) forrotation

Same as ROR except carryis attached to the (D) forrotation

CFOF undefined ifcount 1


CF

OF undefined ifcount 1


Figure 4.5 (a) Rotate instructions

This instruction have the ability to rotate the contents of either an internal register or

storage location in memory.

Destination CountRegisterRegisterMemoryMemory

1CL1

CLFigure 4.5 (b) Allowed operands.

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The rotation that take place can be from 1 to 255 bit positions to the left or to the

right.

In the case of multibit rotate, the number of bit positions to be rotated is specified by

the value in CL.

Their difference from the shift instruction is that the bits moved out at either the MSB

or LSB end are not lost;instead, they are reloaded at the other end.

Example :

The operation of ROL instruction. Execution of ROL causes the contents of the

selected operand to be rotated left the specified number of bit positions. Each bit shifted out

at the MSB end is reloaded at the LSB end. The content of CF reflects the state of the last

bit that was shifted out.

The instruction

ROL AX,1

causes a 1-bit rotate to the left. The original value of bit 15 is 0.This value has been rotated

into CF and bit 0 of AX. All other bits have been rotated 1 bit position to the left, as shown in

figure 4.5(c)

BeforeAX Bit 15 Bit 0 CF

0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

After

AX CF

BIT 15BIT 0

Figure 4.5 (c) Results of executing ROL AX,1

0

0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0

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The RORinstruction operates the same way as ROL except that it causes data to be

rortated to the right instead of to the left.

Example:

The instruction of

ROR AX,CL

causes the contents of AX to be rotated right by the number of bit positions specified in CL.

The result for CL equal to four is shown in fig. 4.5 (d)

Before AXBit 15 Bit 0

0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0CF

After

Bit 15 Bit 0

CFAX

Figure 4.5 (d) Results of executing ROR AX,CL

The other two rotate instructions, RCL and RCR differ from ROL and ROR because

the bits are rotated through the carry flag.

Figure 4.5 (e) illustrates the rotation that takes place due to execution of the RCL

instruction.Note that the value returned to bit 0 is the prior content of CF and not bit

15. The value shifted out of bit 15 goes into the carry flag. Thus the bits rotate

through carry.

Bit 15 Bit 0

Figure 4.5 (e) Rotation caused by execution of the RCL instruction

0

0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1

0

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EXAMPLE 4.5

What is the result in BX and CF after execution of the following instruction?

RCR BX, CL

Assume that, prior to execution of the instruction, (CL) = 04H, (BX) = 1234H, and (CF) =0.

SOLUTION:

The original contents of BX are

(BX) = 00010010001101002 = 1234H

Execution of the RCR instruction causes a 4- bit rotate right through carry to take place on

the data in BX. The resulting contents of BX and CF are

(BX) = 10000001001000112 =8123H

(CF) = 02

In this way, the original content of bit 3, which was 0, resides in carry flag and 10002 has

been reloaded from the bit-15 end of BX.

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Exercise For Topic 4

1. If a MOV CX , [ 1234 H ] instruction appears in an assembly language program, what

is its machine language equivalent?2. Is a MOV CS,DS instruction a valid 8086/8088 instruction? Explain your answer.

3. 'What is wrong with instruction MOV BL,BX ?.

4. Write an instruction sequence that will initialized the ES register with the immediate

value 1010.

5. Write a single instruction that loads AX from address 0200 H and DS from address

0202 .

6. Describe the function / meaning of each of the following instructions:

a. LEA

b. LDS

c. ADC

d. SBB

e. LES

7. Write an instruction that will add the immediate value 111F H and the carry flag to the

contents of the data register DX.

8. Assuming that AX =0123 H, and BL = 10 H ,what will be the new contents of AX after

executing the instruction DIV BL ?.

9. What instruction is used to adjust the result of an addition that processed packed

BCD numbers ?.

10. Perform the logical AND operation for the binary number that follow:

a) 00010101 . 00011000 = ? b) 01001111 . 11011100 = ?

11. Perform the logical OR operation for the binary number that follow:

a) 00011000 . 00010101 = ? b) 11011100 . 01001111 = ?

12. Perform the logical NOT operation on the bits of the hexadecimal number AAAA H.

Express the answer in both binary and hexadecimal notation.

13. Combine the binary numbers 11000000 and 11011000 with a exclusive OR

operation . Convert the binary answer to hexadecimal form.

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14. Write an instruction that shifts the contents of the count register left by one bit position.

15. Write an instruction sequence that , when executed , shift left by eight bit positions the

contents of the word-wide memory location pointed to by the address in the

destination index register.

16. If the original contents of AX , CL , and CF are 800F H , 04 H and 1 , respectively ,

what is the content of AX an CF after executing the instruction SAR AX , CL ?.

17. Describe the operation that is performed by the following instruction sequence.

ROR DX, CL

18. Describe the operation that is performed by the following instruction sequence.

ROL DX,CL

19. Describe the operation performed by the instruction sequence that follows.

Assume AX=0002H

SHL AX,1MOV BX,AX

What is the result in AX, after the shift is complete?

20. Assume that CL contains 02 H and AX contains 091A H . Determine the new contents

of AX and carry flag after the instruction SAR AX , CL .

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SUMMARY

In this unit we have studied :

1 Data transfer instructionprovided to move data either between its internal register or

between an internal register and a storage location in memory. This group included :

Move byte / word ( MOV) ,Exchange byte / word ( XCHG ) ,Translate byte (XLAT)

Load effective address ( LEA ) ,Load data segment ( LDS ), Load extra segment

( LES)

2 Arithmetic instructioninclude addition , subtraction , multiplication and division is valid

for 8 and 16 bit ( sign and unsign number).

3. The 8088 has instructions for performing the logic operations AND, OR, exclusive-OR

and NOT.

4. There are four type of shift instruction in 8088, they are Shift Logical left (SHL) , Shift

arithmetic left (SAL) , Shift logical right (SHR) and Shift arithmetic right (SAR).

5. There are four types of rotate instructions , that is Rotate left (ROL) , Rotate right

(ROR) , Rotate left through carry (RCL) and Rotate right through carry (RCR).

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ANSWERS

Exercise For Topic 4

1. 8BOE3412

2. Invalid because the operation is segment to segment (not allow )

3. Mix size

4. MOV AX , 1010 H

5. LDS AX, [ 0200 H ]

6. a) LEA load effective address

b) LDS load register and DS

c) ADC adds bytes or words plus carry flag

d) SBB subtracts bytes or word minus carry flag

e) LES load register and ES

7. ADC DX , 111F H

8. AX = 0012 H

9. DAA

10. a) 00010000 b) 01001100

11. a) 00101101 b) 00101011

12. Binary = 0101010101010101

Hexadecimal = 5555 H

13. Binary = 00011000

Hexadecimal = 18 H

14. SHL AX , 1

15. MOV CL , 08 H

SHL WORD PTR [ DI] , CL

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16. ( AX ) = F800 H ; CF = 1

17. ROR DX , CL Rotate the DX right by the number of bit position equal to CL. Eachbit shifted out from the right most bit goes into the leftmost bit position.

18. ROL DX , CL - Rotate the DX left by the number of bit position equal to CL. Each bitshifted out from the right most bit goes into the leftmost bit position.

19. Shift the AX to the left 1 bit position , then move the new content in AX to the BXregister.

AX = 0004 H

20. ( AX ) = 0246 H ; (CF ) = 1

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07 Unit 4