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Comparison of Various Voltage Source Inverterbased UPQC Topologies

Srinivas Bhaskar Karanki, Mahesh K. Mishra, Senior Member, IEEE, B. Kalyan Kumar, Member, IEEE

Department of Electrical Engineering,

Indian Institute of Technology Madras, Chennai, India.Corresponding author: Tel.:+91 44 22575459; Fax:+91 44 22574402; E-mail: balu.karanki@gmail.com

AbstractThe Unified Power Quality Conditioner (UPQC) isa custom power device, which mitigates voltage and currentrelated power quality issues in the power distribution systems. Inthis paper, two new Voltage Source Inverter (VSI) topologies forUPQC application are proposed. The proposed topologies enablesUPQC to have a reduced DC link voltage without compromisingthe compensation capability. These proposed topologies also helpto match the DC link voltage requirement of the shunt andseries active filters in the UPQC. In this paper the proposed

UPQC topologies are compared with the existing topologies inthe literature. A simulation study of the proposed topologies hasbeen carried out and the results are presented.

Index TermsUPQC topologies, DC link Voltage, UPQC, Non-

stiff source.

I. INTRODUCTION

With the proliferation of the power electronics devices, non-

linear loads and unbalanced loads, the power quality (PQ)

in the power distribution network has degraded significantly[1]. To improve the quality of power, custom power devices

are used in the distribution system. UPQC is one of the

custom power device, which is a combination of back-to-backconnected shunt active filter and series active filter with a

common DC link. Unified Power Quality Conditioner (UPQC)

is used to provide balanced and sinusoidal source currents

and load voltages under unbalanced and distorted three-phase

supply voltages and load currents in a power distributionnetwork.

In case of the three phase four wire system, neutral clamped

topology is used for UPQC [2][4]. This topology enables the

independent control of each leg of both the shunt and series

inverters, but it requires capacitor voltage balancing [5]. In [6],four leg VSI topology for shunt active filter has been proposed

for three phase four wire system. This topology avoids thevoltage balancing of the capacitor, but the independent control

of the inverter legs is not possible. To overcome this problem

in [7], [8], the authors have proposed a T-connected trans-

former and three phase VSC based DSTATCOM. However

this topology increases the cost and bulkiness of the UPQC

because of the presences of extra transformer. In [9], H-bridge

based VSI topology is used for UPQC operation. Although it

has independent control of each legs of the inverter with single

DC capacitor, the number of switches required for each leg is

double when compared to other topologies. The compensation

978-1-4577-1510-5/11/$ 26.00 @ 2011 IEEE

performance of any active filter depends on the voltage ratingof DC link capacitor [10]. In general the DC link voltage for

the shunt active filter has much higher value than the peakvalue of the line to neutral voltages [11][14]. This is done

in order to ensure a proper compensation at the peak of the

source voltage. Similarly for series active filter the DC link

voltage is maintained at a value equal to the peak of the line

to line voltage of the system for proper compensation [15][17].In case of the UPQC, the DC link voltage requirement for

the shunt and series active filters is not the same, the shuntactive filter requires higher DC link voltage when compared

to the series active filter for proper compensation. The shunt

active filter provides a path for real power flow to aid the

operation of the series compensator and to maintain constant

average voltage across the DC storage capacitor [18]. In order

to have a proper compensation for both series and shunt activefilter, common DC link voltage based on shunt active filter

requirement have to be selected. This will result in over ratingthe series active filter as it requires lesser DC link voltage

for proper compensation when compared to shunt active filter.Due to this criterion in literature, a higher DC link voltagebased on the UPQC topology have been chosen [6], [19],

[20]. With the high value of DC link capacitor, the Voltage

Source Inverters (VSI) becomes bulky and the switches used

in the VSI also need to be rated for higher value of voltage

and current. This in turn increases the entire cost and size of

the VSI. To reduce the DC link voltage storage capacity afew attempts were made in literature. In [21], a hybrid filter

has been discussed for motor drive applications. The filteris connected in parallel with diode rectifier and tuned at 7th

harmonic frequency. Although an elegant work, the design is

specific to the motor drive application and the reactive power

compensation is not considered, which is an important aspectin shunt active filter applications.

In this paper, two UPQC topologies with reduced DC linkvoltage are proposed. The first topology is a combination of

the conventional neutral clamped topology and a capacitor inseries with the interfacing inductor of the shunt active filter.

The series capacitor enables reduction in DC link voltage

requirement of the shunt active filter and simultaneously

compensating the reactive power required by the load, so as to

maintain unity power factor, without any compromise on the

performance of the UPQC. This allows us to match the DC link

voltage requirements of the series and shunt active filter with

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vsa

vsbN

PCC

Linear load

Non-linear loadRf

Lf

Rf

Lf

Rf

Lf

Sc

S'c

Sa

S'a

Sb

S'b

Vdc

Rs Ls

Rs Ls

Rs Ls

Rla Llailaisa

Rlb Llbilbisb

Rlc Llcilcisc

Rnl

Lnl

vsc

ifbifa ifc

Vdc

'n

n

dcC

dcC

lav

lbv

lcv

Scc

S'cc

Saa

S'aa

Sbb

S'bb

lni

fni

sni

Cse Cse Cse

tv

dvrav

dvrbv

dvrcv

Lse Lse LseThree Phase

Supply

Series Injection

Transformers Unbalanced

Distorted Load

Series Active Filter Shunt Active Filter

Fig. 1. Equivalent circuit of neutral clamped VSI topology based UPQC.

a common DC link capacitor. In second topology, the system

neutral is connected to the negative terminal of the DC bus.

This will avoid the requirement of the fourth leg in VSI of

the shunt active filter and enables the independent control ofeach leg of the VSI with single DC capacitor. In this paper

various topologies are compared and the simulation studiesfor the conventional neutral clamped topology and the two

proposed topologies are carried out using PSCAD simulator

and detailed results are presented.

I I . CONVENTIONAL AND PROPOSED TOPOLOGIES OFUPQC

In this section, the conventional and proposed topologies

of the UPQC are discussed. Figure 1 shows the power circuitof the neutral clamped VSI topology based UPQC which isconsidered as the conventional topology in this study. Even

though this topology requires two DC storage devices, each

leg of the VSI can be controlled independently and tracking is

smooth with less number of switches when compared to other

VSI topologies [5]. In this figure, vsa, vsb and vsc are source

voltages of phases a, b and c respectively. Similarly, vta, vtband vtc are the terminal voltages. vdvra, vdvrb and vdvrc are

the injected voltages of the series active filter. The sourcecurrents in three phase are represented by isa, isb and isc, load

currents are represented by ila, ilb and ilc. The shunt active

filter currents are denoted by ifa , ifb, ifc and iln represents

the current in the neutral leg. Ls and Rs represent the feederinductance and resistance, respectively. The interfacing induc-

tance and resistance of the shunt active filter are representedby Lf and Rf respectively. The interfacing inductance and

filter capacitor of the series active filter are represented by Lseand Cse respectively. The load constituted of both linear and

nonlinear loads as shown in this figure. The DC link capacitors

and voltages across them are represented by Cdc1 = Cdc2 =Cdc and Vdc1 = Vdc2 = Vdc, respectively. Vbus is the total DC

link voltage. In this conventional topology, the voltage across

each common DC link capacitance is chosen as 1.6 times the

peak value of the source voltage as given in [5].

Vdc

Vdc

n

dcC

dcC

fni

PCC

Rf

Lf

Rf

Lf

Rf

Lf

Sc

S'c

Sa

S'a

Sb

S'b

lav

lbv

lcv

Scc

S'cc

Saa

S'aa

Sbb

S'bb

Three

Phase

Supply

Series

Injection

Transformer

Unbalanced

Distorted

Load

sai

sbi

sci

lai

lbi

lci

sni

tv

lni

nN

fai fbi fci

Cf Cf Cf

Fig. 2. Equivalent circuit of neutral clamped VSI topology based UPQCwith series capacitor.

Figure 2 shows the equivalent circuit of neutral clamped VSI

topology based UPQC with series capacitor Cf. This topology

is a combination of the conventional UPQC topology with a

capacitor, Cf in series with the interfacing shunt branch ofthe shunt active filter. This topology is referred as proposed

topology-I in this work. The passive capacitor Cf has thecapability to supply a part of the reactive power required

by the load and the active filter will compensate the balance

reactive power requirement and the harmonics present in the

load. The addition of capacitor in series with the interfacinginductor of the shunt active filter will significantly reduce the

DC link voltage requirement and consequently reduces theaverage switching frequency of the switches. This concept

will be illustrated with analytic description in the followingsection. The reduction in the DC link voltage requirement of

the shunt active filter enables us to match the DC link voltage

requirement of the series active filter. This topology avoids theover rating of the series active filter in the UPQC compensation

system. The design of the series capacitor Cf and the other

VSI parameters have significant effect on the performance of

the compensator. These are given in the next section.

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Cf

PCC

Rf

Lf

Rf

Lf

Rf

Lf

Sc

S'c

Sa

S'a

Sb

S'bVbus

dcC

lav

lbv

lcv

Scc

S'cc

Saa

S'aa

Sbb

S'bb

fni

Three

Phase

Supply

Series

Injection

Transformer

Unbalanced

Distorted

Load

sai

sbi

sci

lai

lbi

lci

sni

tv

lni

nN

fai fbi fci

Cf Cf

Fig. 3. Equivalent circuit of proposed VSI topology for UPQC compensatedsystem.

Figure 3 represents the equivalent circuit of the proposed

VSI topology for UPQC compensated system. In this topology

the system neutral has been connected to the negative terminal

of the DC bus along with the capacitor Cf in series with theinterfacing inductance of the shunt active filter. This topology

is referred as proposed topology-II. This topology uses a

single DC capacitor unlike the neutral clamped topology and

consequently avoids the need of balancing the DC link volt-

ages. Each leg of the inverter can be controlled independently

both in shunt and series active filters. Unlike the topologies

mentioned in the literature [2][4], [6], this topology does notrequire the fourth leg in the shunt active filter for three phase

four wire system. The performance of this topology will beexplained in detailed in the following section.

III. OPERATION OF THE PROPOSED TOPOLOGIES

In this section the operation of the two proposed topologies

are discussed. In case of the neutral clamped VSI topology

with series capacitor, the fundamental voltage across the

capacitor (vcf1) adds to the inverter terminal voltage (uVdc)

when the load is inductive in nature. This is because, whenthe load is inductive in nature, the fundamental of the filter

current lags the voltage at the PCC by 90o for reactive powercompensation and thus the fundamental voltage across the

capacitor again lags the fundamental filter current by 90o.Finally the fundamental voltage across the capacitor will be

in phase opposition to the voltage at the PCC. Thus, the

fundamental voltage across the capacitor adds to the inverter

terminal voltage. This allows us to rate the DC link voltage atlower value than conventional design [22].

In the proposed topology-II, along with the series capacitorin the shunt active filter, the system neutral is connected to the

negative terminal of the DC bus capacitor. This will introducea positive DC voltage component in the inverter output voltage,

because when the top switch is ON +Vbus(= 2Vdc) appearsat the inverter output and 0 Vappears when the bottom switchis ON. Thus the inverter output voltage will have DC voltage

component along with the AC voltage. The DC voltage is

blocked by the series capacitor and thus the voltage across

the series capacitor will be having two components, one is

TABLE ISYSTEM PARAMETERS

System Quantities Values

System voltages 230 V (line to neutral), 50 Hz

Feeder impedance Zs = 1 + j3.141

Linear Load Zla = 34 + j47.5 , Zlb = 81 + j39.6 ,

Zlc = 31.5 + j70.9

Non-Linear Load Three phase full bridge rectifier load

feeding a R-L load of 150 -300 mHShunt VSI parameters Cdc = 1100 F,Vbus = 1040 V,

Lf = 26 mH, Rf = 1

Series VSI parameters Cse=80 F, Lse= 5 mH

Rsw = 1.5

Series interfacing 1:1, 100 V and 700 V A

transformer

PI controller gains Kp = 6, Ki = 5.5

Hysteresis band h1 = 0.5 A, h2= 6.9 V

the AC component, which will be in phase opposition to the

PCC voltage and the other is the DC component. Whereas, incase of the conventional topology the inverter output voltage

varies between +Vdc when top switch is ONand Vdc whenthe bottom switch ON. Similarly, when a four leg topology

is used for shunt active filter with a single DC capacitor, the

inverter output voltage varies between +Vbus and Vbus. So,these topologies does not contain any DC component in the

inverter output voltage. This topology contains only one DC

capacitor as the neutral is directly connected to the negative

terminal of the DC bus, this avoids the need of balancing

of capacitor voltages, which is a major setback of the neutralclamped topology. Since the neutral wire is directly connected

to the negative terminal of the DC bus, the necessity of fourth

leg in the inverter is avoided. In case of the four leg basedVSI topology, independent control is not possible. In the

modified topology, the three legs of the shunt active filter are

independently controlled and which results in the automatic

tracking of the neutral current. Thus the modified topology

has the advantage of both the neutral clamped topology and

four leg inverter topology.

The parameters of the VSI need to be designed carefully

for better tracking performance. The important parameters thatneed to be taken into consideration while designing conven-

tional VSI are Vdc, Cdc, Lf , Lse, Cse and switching frequency

(fsw). A detailed design procedure of VSI parameters for the

shunt and series active filter are given in [23], [24], basedon the the equations in the [23], [24] the parameters of the

conventional VSI topology are chosen and given in Table I.The series capacitor design is given in [22] and the value

of the Cf is chosen to be 65 F for a reduced DC linkvoltage of 280 V across each DC link capacitor. In this

work, the reference currents for the active filters are generated

using Instantaneous symmetrical component theory [25] Toovercome the limitation of the algorithm, fundamental positive

sequence voltages v+la1(t), v+

lb1(t) and v+

lc1(t) of the PCCvoltages are extracted and are used in the shunt algorithm

[26].

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1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-10.0

-5.0

0.0

5.0

10.0

Current(A)

Time (s)

lai lbi lci

lni

(a)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-400

-300

-200

-100

0

100

200

300

400

Voltage(V)

Time (s)

tav tbv tcv

(b)

Fig. 4. Simulation results (a) Load currents before compensation (b) Terminalvoltages before compensation.

IV. SIMULATION RESULTS

In order to validate the proposed topologies, simulations

are carried out using PSCAD software. The same system

parameters which are given Table I with Cf = 65 F are

used in PSCAD simulation. The simulation results for both

the conventional topology and the proposed topologies I and

II are presented in this section for better understanding and

comparison between the topologies.

The load currents and terminal (PCC) voltages before com-

pensation are shown in Fig. 4. The load currents are unbal-

anced and distorted, the terminal voltages are also unbalanced

and distorted because these load currents flow through thefeeder impedance in the system. Figure 5 gives the simulation

results of the UPQC using conventional VSI topology. The

DC link voltages across the top and bottom DC link capacitors

are shown in Fig. 5(a), using PI controller the voltage across

each capacitor is maintained constant to the reference value

of 520 V as shown in the figure. The source currents after

compensation are balanced and sinusoidal as shown in Fig.

5(b). Figure 5(c) represents the compensation performance ofthe series active filter. A sag of 50 % is considered in allphases of the terminal voltages for 5 cycles, which start from

1.9 seconds and ends at 2.0 seconds. The compensated DVR

voltages and load voltages after compensation are shown in the

same figure. The load voltages are maintained to the desiredvoltage using series active filter. In this topology the peak to

peak voltage across the inductor is 1040 V.

The simulation results for the topology shown in Fig. 2

and (i.e., the neutral clamped VSI topology based UPQC withcapacitor in series with the interfacing inductor of the shunt

active filter) are shown in Figs. 6(a) and 7. In this topology

The value of the capacitor (Cf) in the shunt active filter branchis chosen to be 65 F and the reference DC link voltage

is 280 V for each capacitor. The voltage across the series

capacitor in phase-a (vcfa) is shown in Fig. 6(a). This figure

also shows the phase-a load voltage (vla). From the figure

0.0 0 0 .5 0 1. 00 1. 50 2 .0 0 2 .5 0 3 .0 0 3. 50 4.0 0 4 .5 0 5 .0 0

0

200

400

600

0

200

400

600

Voltage(V)

Time (s)

1dcV

2dcV

(a)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-10.0

-5.0

0.0

5.0

10.0

Current(A)

Time (s)

sai sbi sci

sni

(b)

1.860 1 .880 1 .900 1 .920 1 .940 1 .960 1 .980 2 .000 2 .020 2 .040

-500

-250

0

250

500

-300

-150

0

150

300

-500

-250

0

250

500

Voltage(V)

Time (s)

tav tbv tcv

dvrav dvrbv dvrcv

lav lbv lcv

(c)

Fig. 5. Simulation results using conventional topology (a) DC capacitorvoltages (top and bottom) (b) Source currents after compensation (c) Terminalvoltages with sag, DVR injected voltages and Load voltages after compensa-tion

it is clear that the voltage across the capacitor is in phase

opposition to the terminal voltage. The voltage across thecapacitor eventually adds to the DC link voltage and injects

the required compensation currents into the PCC. The reasonbeyond showing phase-a capacitor voltage is that the design of

the reference DC link voltage is based on phase-a filter current,

which has the maximum filter current among the three phases.

Figure 7 gives the simulation results of the UPQC usingproposed VSI topology-I. The DC link voltages across the top

and bottom DC link capacitors are shown in Fig. 7(a), using

PI controller the voltage across each capacitor is maintained

constant to the reference value of 280 V as shown in thefigure. The source currents after compensation are balanced

and sinusoidal as shown in Fig. 7(b). It can be observed fromthe Fig. 7(b), the band violation of the sources currents are

less when compared to the conventional topology. Figure 7(c)represents the compensation performance of the series active

filter. A sag of 50 % is considered in all phases of the theterminal voltages for 5 cycles, which start from 1.9 secondsand ends at 2.0 seconds. The compensated DVR voltages and

load voltages after compensation are shown in the same figure.

The load voltages are maintained to the desired voltage using

series active filter. In this topology the peak to peak voltage

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1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-400

-300

-200

-100

0

100

200

300

400

Time (s)

Voltage(V)

cfavlav

(a)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-400

-300

-200

-100

0

100

200

300

400

500

Voltage(V)

Time (s)

cfavlav

(b)

Fig. 6. Voltage across series capacitor and load voltage in phase - a (a)Proposed topology-I (b) Proposed topology-II.

across the inductor is 560 V.

The simulation results with the proposed topology-II are

shown in Figs. 6(b) and 8. In this topology the total DC bus

voltage is maintained at 560 V. The voltage across the series

capacitor in phase-a (vcfa) and the phase-a load voltage (vla)

are shown in Fig. 6(b). Both are in phase opposition and

eventually the series capacitor voltage supports in injecting

the compensation currents into the PCC. The inverter output

voltage varies between 0 and +Vbus, which will introduce a

dc component along with the AC components. The same dccomponent will be reflected across the series capacitor voltage

(vcfa).The DC bus voltage (Vbus) is shown in figure Fig. 8(a). The

source currents after compensation using proposed topology-II

are shown in Fig. 8(b). Figure 8(c) represents the compensa-

tion performance of the series active filter. A sag of 50 %is considered in all phases of the the terminal voltages for 5

cycles, which start from 1.9 seconds and ends at 2.0 seconds.

The compensated DVR voltages and load voltages are shown

in the same figure. The load voltages are maintained to the

desired voltage using series active filter. The peak to peak

voltage across the inductor is 560 V, which is far lower thanthe voltage across the inductor using conventional topology.

As the voltage across inductor is high in case of conventional

topology, the rate of rise of filter currentdifdt will be higher

than that of proposed topologies. Thus the slope of the actual

filter currents in case of the conventional topology will be

high and this will allow the filter currents to hit the hysteresisboundaries at a faster rate and increases the switching fre-

quency when compared to the proposed topologies. Thus, the

average switching frequency of the switches in the proposed

topology will be less as compared to conventional topology.

Since the average switching is less, the switching loss will

also decrease in proposed topologies.

One more advantage of having less voltage across the

inductor is that the hysteresis band violation will be less.

0. 00 0. 50 1 .0 0 1 .5 0 2 .0 0 2 .5 0 3 .0 0 3 .5 0 4 .0 0 4. 50 5 .0 0

0

100

200

300

0

100

200

300

Voltage(V)

Time (s)

(a)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-10.0

-5.0

0.0

5.0

10.0

Current(A)

Time (s)

sai sbi sci

sni

(b)

1.860 1.880 1.900 1.920 1.940 1.960 1.980 2.000 2.020 2.040

-500

-250

0

250

500

-300-200-100

0100200300

-500

-250

0

250

500

Voltage(V)

Time (s)

tav tbv tcv

dvrav dvrbv dvrcv

lav lbv lcv

(c)

Fig. 7. Simulation results using proposed topology-I (a) DC capacitorvoltages (top and bottom) (b) Source currents after compensation (c) Terminalvoltages with sag, DVR injected voltages and Load voltages after compensa-tion.

This will improve the quality of compensation and Total

Harmonic Distortion (THD) will be less in the proposed

topology. Similarly the switching in the series active filter

also reduces marginally as the DC link voltage is reduced.

The THD of the source currents and load voltages before and

after compensation in all the three phases are given in Table

II. Table II also gives the average switching frequency in each

leg of the inverter. This clearly shows the proposed topologiesperformance is better than the conventional topology with a

less DC link voltage, reduction in switching operation andregular tracking of reference compensator currents.

Table III gives the comparison of various topologies in

the literature with the proposed topologies. From this tableit is clear that the proposed topologies required reduced

DC link voltage and subsequently the rating of the switches

also reduces. Proposed topology-II has advantages of all the

other topologies with a extra requirement of three AC series

capacitors. Both the proposed topologies enables the matching

of the DC link voltage requirement of the shunt and series

active filters.

V. CONCLUSIONS

Two UPQC topologies for three phase four wire system

has been proposed in this paper, which has the capability of

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TABLE IICOMPARISON OF PROPOSED TOPOLOGIES WIT H CONVENTIONAL TOPOLOGY

Type of Topology THD (%) Average Switching Frequency (kHz)

Source Currents Load Voltages Shunt Active Filter Series Active Filter

isa isb isc vla vlb vlc Leg- a Leg- b Leg- c Leg- a Leg- b Leg- c

Without Compensation 9.2 11.7 12.75 5.99 5.86 6.17 - - - - - -

Conventional Topology 2.96 3.20 2.55 1.48 1.59 2.10 3.96 4.12 3.95 8.10 8.30 8.40Proposed topology-I 1.91 2.56 2.43 1.27 1.32 1.48 2.90 2.40 2.75 6.50 7.00 7.10

Proposed topology-II 1.59 2.19 1.31 1.12 1.24 1.58 3.10 2.44 2.98 6.80 7.20 7.40

TABLE IIICOMPARISON OF VARIOUS TOPOLOGIES

Parameter Conventional Four leg H-Bridge Proposed Proposed

Topology [5] Topology [6] Topology [9] Topology-I Topology-II

DC link voltage (Vbus) 2 1.6 Vm1 2.2 Vm 2.45 Vm 2 0.86 Vm 1.72 Vm

(In this paper Vm = 325V ) 1040 V 715 V 800 V 560 V 560 V

Number of Switches 6+6 = 12 6+8 =14 12+12 = 24 6+6 = 12 6+6 = 12

(Series+Shunt = Total)

Voltage Rating of Switch Vbus Vbus Vbus Vbus Vbus

Number of DC Capacitors 2 1 1 2 1

DC Capacitor Balancing R 2 NR 3 NR R NR

Series AC Capacitors - - - 3 3

Control of Shunt Inverter Legs I 4 D 5 I I I

1 Vm is the peak of the source voltage;2R = Required; 3 NR = Not Required; 4I = Independent; 5D = Dependent

compensating the load at a lower DC link voltage under non

stiff source. The proposed method is validated through simu-

lation studies in a three-phase four wire distribution system.

The proposed topology-II has the advantages of both the con-ventional neutral clamped topology and the four leg topology.

Detailed comparative studies are made for the conventionaland proposed topologies. From the study, it is found that the

proposed topologies have less average switching frequency,less THDs in the source currents and terminal voltages with

reduced DC link voltage as compared to the conventional

UPQC topology.

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7/30/2019 06156683

7/7

7

0 .0 0 0. 50 1 .0 0 1 .5 0 2 .0 0 2 .5 0 3 .0 0 3 .50 4 .00 4. 50 5. 00

0

100

200

300

400

500

600

Voltage(V)

Time (s)

dcV

(a)

1.9600 1.9650 1.9700 1.9750 1.9800 1.9850 1.9900 1.9950 2.0000

-10.0

-5.0

0.0

5.0

10.0

Time (s)

Voltage(V)

sai sbi sci

sni

(b)

1.860 1 .880 1 .900 1 .920 1 .940 1 .960 1 .980 2 .000 2 .020 2 .040

-500

-250

0

250

500

-300

-150

0

150300

-500

-250

0

250

500

Voltage(V)

Time (s)

tav tbv tcv

dvrav dvrbv dvrcv

lav lbv lcv

(c)

Fig. 8. Simulation results using modified topology (a) DC link voltage(b) Source currents after compensation (c) Terminal voltages with sag, DVRinjected voltages and Load voltages after compensation.

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