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Mathematical Analysis of Digital MASH Delta-Sigma Modulators for Fractional-N Frequency Synthesizers Kaveh Hosseini Department of Microelectronic Engineering Butler Building, North Mall, University College Cork Cork, Ireland Tel:+(353)-21-4904582, Email: [email protected] Abstract- A mathematical analysis is performed to investigate the periodic behavior of digital MASH Delta-Sigma modulators (DSM). The analysis is performed on first, second and third order MASH digital DSMs with odd initial conditions on the first stage. We prove that the maximum sequence length for the first order modulator is 2N and for the second order modulator is 2N+1, where N is the word length of the state. In the case of first and second order modulators, the maximum sequence length can be achieved when odd digital inputs are applied. In the case of the third order modulator, the sequence length is equal to 2N+1 for all digital inputs. I. INTRODUCTION Delta-Sigma modulators were introduced in [1] and [2] to shape the quantization noise power of fractional-N frequency synthesizers. Linear noise shaping can be achieved if the highly nonlinear block model of the delta sigma modulator, the quantizer, can be modelled by an additive white noise source. It has been proven [3] that, even with a continuous-amplitude discrete-time model, inherited from oversamped delta sigma analog to digital converters, the modulator behavior can be periodic when certain dc inputs are applied and thus, spurious tones appear in the modulator's output noise power spectrum. Gray showed mathematically [3] that for a first order modulator with dc inputs, the output spectrum consists of discrete spurs whose locations and amplitudes depend on the input value. This analysis was extended to higher order multistage noise shaping modulators in [4] and [5]. The results in [4] and [5] have proven mathematically that, in a higher order MASH modulator, the additive white noise source assumption for the quantizer error from the last stage is correct, when irrational dc inputs are employed. These mathematical analyses of modulators were performed with the assumption of zero initial condition on the accumu- lators. For the case of irrational dc inputs, the asymptotic behavior of the quantizer error is not affected by the initial conditions [3], [4], [5] and [6]. Kozak and Kale [6] provide an exact analysis for higher order MASH AZ, modulators with rational dc inputs and non-zero initial conditions. Their approach effectively shows that an irrational initial condition imposed on the first accumulator guarantees a tone- free output Michael Peter Kennedy Department of Microelectronic Engineering Butler Building, North Mall, University College Cork Cork, Ireland Email: [email protected] spectrum for third and higher order MASH modulators when driven by rational dc inputs. In attempting to extend their theoretical results to the case of rational initial conditions (digital DSMs), Kozak and Kale suggest that if the internal digital word length of a fixed-point digital DSM is relatively high, irrational initial conditions can be implemented using odd numbers, although, their mathematical analysis does not predict the periodicity of digital DSMs. Borkowski et al. [7] have used the results of [6], but have considered digital AE modulators as finite state machines (FSM). They performed extensive simulations on the various orders of MASH and error feedback modulators in order to extract an empirical design methodology for digital DSMs. Their empirical results for second and third order MASH digital DSMs are summarized in Table I, where I1 is the initial condition of the first stage. TABLE I SEQUENCE LENGTHS FOR SECOND AND THIRD ORDER MASH DSMs WITH WORD LENGTH N [7] Modulator Order m 2 3 Guaranteed Sequence Length 2N-1 2N+l Maximum Sequence Length 2N+1 2N+1 Initial Condition I1 odd I1 odd In this paper, we prove these results. We calculate rigorously the sequence length of digital MASH DSMs. The analysis is performed on first, second and third order MASH DSMs with odd initial conditions in the first stage and verifies the empirical observations of [7]. II. FIRST ORDER MODULATORS In this study, we derive a closed form expression for the binary quantizer error of a first order digital modulator and we calculate its sequence length (period). The accumulator shown in Fig. 1 (a) is used in the implementation of high order MASH 1-4244-0157-7/06/$20.00 C2006 IEEE 309

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Page 1: 01689958

Mathematical Analysis of Digital MASHDelta-Sigma Modulators for Fractional-N Frequency

SynthesizersKaveh Hosseini

Department of Microelectronic EngineeringButler Building, North Mall, University College Cork

Cork, IrelandTel:+(353)-21-4904582, Email: [email protected]

Abstract- A mathematical analysis is performed to investigatethe periodic behavior of digital MASH Delta-Sigma modulators(DSM). The analysis is performed on first, second and third orderMASH digital DSMs with odd initial conditions on the first stage.We prove that the maximum sequence length for the first ordermodulator is 2N and for the second order modulator is 2N+1,where N is the word length of the state. In the case of first andsecond order modulators, the maximum sequence length can beachieved when odd digital inputs are applied. In the case of thethird order modulator, the sequence length is equal to 2N+1 forall digital inputs.

I. INTRODUCTIONDelta-Sigma modulators were introduced in [1] and [2] to

shape the quantization noise power of fractional-N frequencysynthesizers. Linear noise shaping can be achieved if thehighly nonlinear block model of the delta sigma modulator, thequantizer, can be modelled by an additive white noise source.It has been proven [3] that, even with a continuous-amplitudediscrete-time model, inherited from oversamped delta sigmaanalog to digital converters, the modulator behavior can beperiodic when certain dc inputs are applied and thus, spurioustones appear in the modulator's output noise power spectrum.

Gray showed mathematically [3] that for a first ordermodulator with dc inputs, the output spectrum consists ofdiscrete spurs whose locations and amplitudes depend onthe input value. This analysis was extended to higher ordermultistage noise shaping modulators in [4] and [5]. Theresults in [4] and [5] have proven mathematically that, ina higher order MASH modulator, the additive white noisesource assumption for the quantizer error from the last stageis correct, when irrational dc inputs are employed.

These mathematical analyses of modulators were performedwith the assumption of zero initial condition on the accumu-lators. For the case of irrational dc inputs, the asymptoticbehavior of the quantizer error is not affected by the initialconditions [3], [4], [5] and [6]. Kozak and Kale [6] providean exact analysis for higher order MASH AZ, modulatorswith rational dc inputs and non-zero initial conditions. Theirapproach effectively shows that an irrational initial conditionimposed on the first accumulator guarantees a tone- free output

Michael Peter KennedyDepartment of Microelectronic Engineering

Butler Building, North Mall, University College CorkCork, Ireland

Email: [email protected]

spectrum for third and higher order MASH modulators whendriven by rational dc inputs.

In attempting to extend their theoretical results to thecase of rational initial conditions (digital DSMs), Kozak andKale suggest that if the internal digital word length of afixed-point digital DSM is relatively high, irrational initialconditions can be implemented using odd numbers, although,their mathematical analysis does not predict the periodicity ofdigital DSMs.

Borkowski et al. [7] have used the results of [6], but haveconsidered digital AE modulators as finite state machines(FSM). They performed extensive simulations on the variousorders of MASH and error feedback modulators in order toextract an empirical design methodology for digital DSMs.Their empirical results for second and third order MASHdigital DSMs are summarized in Table I, where I1 is the initialcondition of the first stage.

TABLE ISEQUENCE LENGTHS FOR SECOND AND THIRD ORDER MASH DSMs

WITH WORD LENGTH N [7]

ModulatorOrder m

23

GuaranteedSequence Length

2N-1

2N+l

MaximumSequence Length

2N+1

2N+1

InitialConditionI1 oddI1 odd

In this paper, we prove these results. We calculate rigorouslythe sequence length of digital MASH DSMs. The analysisis performed on first, second and third order MASH DSMswith odd initial conditions in the first stage and verifies theempirical observations of [7].

II. FIRST ORDER MODULATORS

In this study, we derive a closed form expression for thebinary quantizer error of a first order digital modulator and wecalculate its sequence length (period). The accumulator shownin Fig. 1(a) is used in the implementation of high order MASH

1-4244-0157-7/06/$20.00 C2006 IEEE 309

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DSMs and the model in Fig. 1(b), which is called the errorfeedback modulator, is used for calculations. The carry bit (thequantizer output in Fig. 1(b)) is determined by the followingrelationship:

(a) Digital Accumulator

£n v

(b) The Accumulator Model

Fig. 1. The digital accumulator used in MASH DSMs (a) and its model (b)

O xn + Un < 2NCn l 1: Xn + Un > 2N

where N is the accumulator word length. If the digital wis normalized to unity, the quantizer input-output relationsis described by (2) and is shown in Fig. 2

With this definition for en, and considering (4) and (6), itsvalues are in the range of:

Cn C {°' 2, ..., (1 (9 ))

In (7), u0 is the initial condition of the registers in Fig. 1. Usingthe above equations we find an expression for en versus xnand u0. Starting with (8), we consider two cases:Case 1: If vn > 1, using (2) we can write:

en = vn - 1 Vn > O, (10)

and considering (4) and (9) we can write:

en = (Vn)

where (x) is the fractional part of x.Case 2: If vn < 1, using (2) we can write:

en = vn -O Vn >O

(1) and considering (4) and (9), we can write:

,CrA eCn = (Vn)

(1 1)

(12)

(13)

Therefore (13) stands for all vn, in its range. Using (5), wehave:

Yn =vn < 1Vn > 1

The ranges of the signals are:

Xw, Un C {o,2N\ ... (1

Vn C 1o:1 ... 1 ... (22N '''(

1

2N1 )}

2N-1 )

The nonlinear difference equations governingshown in Fig. l(b) can be summarized as:

Vn Xn + un Vn > O,

(2)en = (Xn + Un) Vn >O.

Rewriting the above equation and using (7), we have:

en = (Xn + Cn-1) Vn >O.

(14)

(15)

Expanding the above equation with its indices, we have:(3)

(4)

the structure

(16)eo =(0o + uo),

el= (xi+eo),and for index n we have:

en = (Xn + Cn-1)-

(5)

(17)

(18)

If we replace the value of e from its values in previousequations, we can write en as

Yn Q(Vn) { 0 v, < 1

{ en-1Un =U

(6) en = (X. + (Xn-1 + (XI-2 + (XO + UO))))Using the property of fractional operators [6] that

Vn > 1n =O, (7)

and the binary quantizer error is defined as:

en = Vn -Yn (8)

'Yn

[email protected]

Fig. 2. Input-output relationship of the quantizer shown in Fig. l(b)

((a) + (b)) = ((a) + b) = (a + (b)) = (a + b)we can rewrite (19) as:

en = (Xn + Xn-1 + Xn-2 + xo +Uo)n

= (U0 +Ex)k.k=0

In the special case of a constant dc input X, we have:

en = (uo + (n + 1)X) Vn >0.

(19)

(20)

(21)

(22)

(23)

If there is a period of N1 for en, then we should have:

en = en+Nl = (uo+(n+Nl+l)X) = (uo+(n+l)X+NiX)(24)

310

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and therefore the term N1X should be an integer. From (24) itis obvious that the sequence length of the first order modulatordoes not depend on initial state uo. We know that X is anormalized rational dc input and we can write it as:

X = dj/2N = dijM. (25)

The solutions for N1 so that N1X is an integer are summarizedin Table II.

TABLE IITHE SEQUENCE LENGTH OF THE FIRST ORDER ERROR FEEDBACK

MODULATOR RELATED TO ITS INPUT DIGITAL WORD

Digital Input, di k12k, where k1 is odd and 0 < k < NSequence Length M/2k

The maximum sequence length (M) is only achieved whenthe input is an odd number.

III. HIGHER ORDER MODULATORSHigher order MASH DSMs are composed of the simple

structure investigated in the previous section (EFM blocksin Fig. 3). The general structure of an 1th order MASH DSMis shown in Fig. 3. The structure consists of several cascadedfirst order error feedback modulators (EFM). The input to eachstage is the quantizer error of the previous stage. The noisecancellation network is used to eliminate the quantizer errorsof the stages. The quantizer error of the last stage appearsdirectly in the output spectrum and therefore we find a closedform expression for the binary quantizer error of the last stageusing the method presented in the previous section.We use (23) and (22) for the first stage and the other stagesrespectively.

el, = (ui + (n + 1)X) Vn > 0,

n

e2n = (U2 +E e2k),k=O

and for the last stage we have:n

Cln= (Ul+ (I-1)k)kz=O

(26)

(27)

Fig. 3. Block diagram of the digital MASH DSM. EFM1 Blocks are thestructure shown in Fig l(b).

A. Second Order Modulators (I = 2)

We find the sequence length of the second order modulatorusing (30). After expanding (30), we have:

n

e2n = (u2 + E U + (k + 1)X).k=O

If there is a period of N2, we should have:

n+N2

e2n e2n+N2 = (U2 + E ul + (k + 1)X)k=O

(31)

(32)

n+N2

ul + (k + 1)X = an integer Vn >Ok=n+l

Examining (34) at n = 0 reduces it to:

N2

u1 + (k + 1)X.k=l

(34)

(35)

Further expansion of this expression, yields the condition

N2U1 + N2(N2 + 3)X an integer,2

(28)

Using the expression of e(l- 1) k from the previous indices,

we can write:n ki-I

Cln Ul+ (ui + 1 (Ul-2 +*kl10=° k1-2=0

k2+ E (ul + (ki + 1)X)))) (29)

k1 =0

and using (20) we can write:

n k1

eln = (u1+ u1i1+ u1-

k1-10 k1-2=0

k2

-2+---+I+ul+(kl+l)X)k1 =0

(30)

(36)

where u1 is the initial condition on the first stage and X is thenormalized digital dc input. We replace ul and X with theircorresponding rational representations:

d2 N2(N2 + 3) di an integer

M 2 M(37)

which d2 is the digital initial condition on the first accumu-

lator, d, is the digital input word and M is equal to 2N. Weexamine the periodicity of (37) with an odd initial condition.In case of odd digital inputs, considering (37) the sequence

length, N2, is 2M. In case of even digital inputs we considertwo cases:

Case 1: If the input is in the form of, 2k; when k is odd; we

can write (37) as:

M (d2 + (N2 + 3)k) (38)

311

n n+N2= ( U2 + (u + (k + 1)X) + S (ui+ (k + 1)X)) (33)

k=O k=n+l

The last term should be an integer; thus, we have:

Page 4: 01689958

The expression (d2 + (N2 + 3)k) is even (k and d2 are odd)therefore, the solution for N2 so that (38) is an integer, is M2Case 2: If the input is in the form of 4k, we can write 37 as:

N2 (d2 + (N2 + 3)2k), (39)

Since the term (d2 + (N2 + 3)2k) is odd, the solution forN2 so that (39) is an integer, is M. Table III summarizes theresulting sequence lengths of the second order modulator.

TABLE IIITHE SEQUENCE LENGTHS OF THE SECOND ORDER MASH DSM RELATED

TO ITS DIGITAL INPUT WORDS AND INITIAL CONDITION ON THE FIRST

STAGE

d2 di N2odd odd 2Modd 4k, k is integer Modd 2k, k is odd 2

The maximmum sequence length 2M is achieved when theinput and the initial condition of the first stage are odd.

B. Third Order Modulators (I = 3)We expand (30) for the third order modulator as follows:

n 2

e3n = (u3 + Z (u2 + Z (u + (ki + 1)X))). (40)k2 =0 k1 =0

If there is period of N3, then the following condition shouldhold:

e30 = e3N3 (41)

After expanding (40), applying the following mathematicalidentities

n

i=l

n(n + 1)2

(43)n

n(n + 1)(2n + 1)i=l6iil

and following the same procedure used for the second ordercase, we find (44) that the sum (44) should be an integer.

N3U2 + N3(N3 + 3) XY+ X N3 (N3 + 3) (N3 + 5) 2N32 2 3+N3

(44)where u1 and u2 are the normalized initial conditions onthe first and the second stages. Equation (44) shows that thesequence length does not depend on the initial condition onthe last stage. We use normalized rational representation foru1 and X and assume that u2 is zero.

d2 N3(N3 + 3) + d N3 + di N3(N3 + 3)(N3 + 5)M 2 M 2M V 3

(45)=a+b+c, (46)

where d1 and d2 are the digital input and odd initial conditionon the first stage, respectively. To find N3 so that (45) is aninteger, we define three terms as a,b and c, respectively. Sinced2 is odd, the minimum value for N3 so that a is an integer is2M. The minimum value of N3 so that b is an integer whend1 is even is equal to M and, when it is odd, is equal to M.2In case of M, the first term a is not integer; therefore the2'minimum value for N3 in order for b to be an integer is M .

Next we want to prove that for the third term c, the minimumvalue of N3 is M when d1 is even, and when it is odd, isequal to 2M. We can write c as

N3(N3 + 1)(N3 + 5) di6 M

Equivalently,

an integer (47)

N3(N3 + 1)(N3 + 5)dl = 3k2N+l = 3k(2M). (48)

If d1 is odd, then di(N3 + 1)(N3 + 5) is odd (N3 is evenrequired by the second term b) and we can write:

N3 k2ff+. (49)

Thus the minimum value of N3 is 2N+1 (k = 1) and when d1is even, N3 is half of this value and is equal to 2N+1 (= M).Therefore, the smallest common multiplier among 2M for a,M for b and M or 2M for c is 2M for all inputs, dl.

IV. CONCLUSIONIn this paper we demonestrated mathematically that, for an

odd initial condition on the first accumulator of the second andthird order modulators described in [7], the sequence length isdetermined from Table I and also for the first order modulatorthe sequence length is correctly determined from Table II,where M = 2N. We found that the initial condition on thelast stage has no effect on the periodicity of the modulator.

V. ACKNOWLEDGEMENT

This work is supported in part by Science FoundationIreland under Grant 02/IN.1/145.

REFERENCES

[1] B. Miller, R. J. Conley,"A Multiple Modulator Fractional Divider", IEEETransactions on Instrumentation and Measurement, Vol. 40, No. 3, pp578-583, June 1991.

[2] T. A. D. Riley, M. A. Copland, "Delta-Sigma Modulation in Fractional-NFrequency Synthesis", IEEE Journal of Solid-State Circuits, Vol.28, No. 5pp553-559, May 1993.

[3] R.M. Gray, "Spectral analysis of quantization noise in a single-loopsigma-delta modulator with dc input", IEEE Trans. Commun., Vol.37,pp588-599,, June, 1989.

[4] P.W.M. Wong, R.M. Gray, "Two-stage sigma-delta modulation", IEEETrans. Acoust., Speech, Signal Processing, Vol.38, pp]937-1952, Nov.,1990.

[5] W. Chua, P.W.M. Wong, R.M. Gray, "Multi-stage sigma-delta modula-tion", IEEE Trans. Inform. Theory, Vol.35, pp784-796, , July, 1989.

[6] M. Kozak and I. Kale, "Oversampled Delta-Sigma Modulators, Analy-sis, Applications and Novel Topologies", Kluwer Academic Publishers,Boston, July, 1989.

[7] M.J. Borkowski, T.A.D. Riley, J. Hakkinen, J. Kostamovaara, "A PracticalDelta Sigma Modulator Design Method Based on Periodical BehaviorAnalysis", IEEE Transactions on Circuits and Systems-II,Vol.52, pp626-630, October, 2005.

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