Embed Size (px)
Citation preview
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-1
NMOS Field Effect Transistor
Gate (G)Source (S)
Body (B)
Drain (D)
n+
L
Channel region
p-type substrate (Body)
MetalOxide (SiO2)
n+
MOSFET = Metal Oxide Semiconductor Field Effect Transistor Four terminal device (gate, source, drain, substrate) Unipolar transistor – one type of charge carrier
FET is a current control mechanism based on an electric field established by the voltage applied to the control terminal
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-2
NMOS Cross-section
GS
D
B
Metal
Metal or Polysilicon
Oxide (SiO2)
SourceRegion
DrainRegion
ChannelRegion
P-type substrate(body)
L
W
n+
n+
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-3
Creating a Channel for Current Flow
A positive voltage is applied to the gate which forms an inversion layer, or an n-type channel
G
S
B
D
n+
L
p-type substrate (Body)
Induced n-typechannel
n+
+vGS
-
Depletion region
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-4
Operation with Small vDS
G
S
B
D
n+
p-type substrate (Body)
Induced n-type channel
n+
+vGS
-
+vDS (small)-
iDiG=0
iS=iD
vDS(mV)
iD(mA)
50 100 150 200
0.4
0.3
0.2
0.1
vGS Vt
vGS=Vt+1V
vGS=Vt+2V
vGS=Vt+3V
vGS=Vt+4ViD
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-5
Exercise 5.1
Note that in the small signal linear range, iD is proportional to (vGS-Vt)vDS Find the constant of proportionality for the device below and the range of drain-to-source resistance for vGS=2V to 5V
2502440 : point1 mA/V.V)V(.mA. 2502110 : point2 mA/V.V)V(.mA.
vDS(mV)
iD(mA)
50 100 150 200
0.4
0.3
0.2
0.1
vGS Vt
vGS=Vt+1V
vGS=Vt+2V
vGS=Vt+3V
vGS=Vt+4V
Vt=1V
point 1
point 1
KmA
mVR 2
1.
200
i
v : 4VVv
D
DSDStGS
5004.
200
i
v : 4VVv
D
DSDStGS mA
mVR
Constant of proportionality
Drain-to-source resistance
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-6
Uniform Channel Approximation
Assumptions Uniform behavior in the z (channel width)
direction The mobility is a constant The x directed electric field is
approximately a constant within the channel thickness (ych) at a given x. This is known as the gradual channel approximation.
At a given x, The current is constant, independent the
location of the chosen cross-section (i.e. independent of x)
n+x = 0
y
x = Lx
VS VD > VS
p-type depletion region edge
n+ inversion channel
J x y z q n E x y zn n x, , , , x, y, z
dydzxEzyxqnxI xn
yy
y
Wz
zn
ch
0 0,,
VG>>VD and VS
Channel charge
xE
yE
yE
Area
WW=width
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-7
Charge per unit length in the channel (VGS >> VDS)
dxVxvvWCxdq tGSox
oxox
rSiO
ox
oxox t
cmFx
ttC
14
01085.89.3
2
channelsource drain
dx
Charge dq
dt
dxvelocity
dx
xdvEx
v(x) = the voltage at point x
dv(x)=the incremental voltage about point x
Gate Oxide
Gate Electrode (metal)
The voltage drop between thegate and the channel, in excessof the threshold voltage Vt
determines the amount of charge
VGS
v(x)
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-8
Derivation of the MOSFET current equation in the Linear Region of Operation
I dz qn x y dy E x
Q x
n nw
W
y
y
x
inversion
ch
0 0
,
'
W
dx
xdvxE
dt
dxnn
dx
xdvxE
dt
dxnn
tGSox
n
VxvvWCdx
xdqdx
xdvvelocity
dt
dx
dt
dx
dx
xdq
dt
dqi
xdvVxvvWCdxi tGSoxnD
DSv
tGSoxn
L
D xdvVxvvWCdxi00
2
2DS
DStGSoxnD
vvVv
L
WCi
200mVvDS
vGS=Vt + 1V
vGS=Vt + 2V
vGS=Vt + 3V
tGS Vv
iDS
Terminal potentials
Layout GeometriesProcessTechnology
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-9
Exercise 5.2
Find the expression for rDS=vDS/iD when vDS is small. Find the value of rDS for an NMOS transistor having k’n=20mA/V2,Vt=1V, and W/L=100m/10m when operated at vGS=5V
tGSnD
DSDS
DStGSnDDS
DSDStGSnD
VvLW
ki
vr
vVvL
Wkiv
vvVv
L
Wki
'1
': smallfor
2'
2
kr
VVmm
VAi
vr
DS
D
DSDS
25.1108001
1510100
201
6
2
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-10
Operation as vDS is Increased
G
S
B
D
n+
p-type substrate
n+
+vGS
-
+vDS
-
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-11
Channel pinch off
Increasing vDS causes the channel to acquire a tapered shape
Eventually, as vDS reaches vGS-Vt, the channel is pinched off at the drain end
Increasing vDS above vGS-Vt has little effect (theoretically no effect) on the channel’s shape
Source Channel DrainvDS
vDS vGS-Vt
vDS 0
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-12
Operation as vDS is Increased (cont.)
vDS
iD
vDS vGSVtvDS vGSVt
vDSsat vGSVt
vGSVt
Triode Saturation
Curve bends because the channel resistance increases with vDS
Almost a straight line with slope proportional to (vGS-Vt)
Current saturates because the channel is pinched off at the drain end, and vDS no longer affects the channel
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-13
Higher Drain Voltages (pinch-off)
n+x = 0
y
x = Lx
VS=0VD > VS
p-type depletion region edge
n+ inversion channel
yE
yE
xE
VDS=VGS-Vt=2V
For Example VG=3V Vt=1VVGD=VG-VD=1V just Vt
VGS=VG-VS
VGS=3V
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-14
The Saturation Region of Operation
2
2
2
'2
1
2'
in substitute and 2
'
tGSnoxD
tGStGStGSnoxD
tGSDSDS
DStGSnoxD
VVCL
WI
VVVVVVC
L
WI
VVVV
VVVCL
WI
Square Law - i.e The current is proportional to the voltage in excess of the threshold squared
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-15
MOSFET Transistor Operating Regions Summary
Figure taken from Semiconductor Devices, Physics and Technology, S. M. Sze,1985, John Wiley & Sons
Linear (triode)Region
Pinchoff - onset ofSaturation Region
Saturation Region
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-16
MOSFET Operation Summary
oxnn Ck 'Let:
Triode Region: vGS >Vt, vDS < vGS-Vt
DSλVtGSnD VVL
Wki 1
2'2
1
Saturation Region: vGS >Vt, vDS vGS-Vt
2'
2DS
DStGSnD
vvVv
L
Wki
Electron mobility: n 580 cm2/Vs
Oxide permittivity: ox =3.97o
= 3.97 X 8.85 X 10-14 =3.5 X 10-13 F/cm
Oxide Capacitance: Cox =ox/tox
= 1.75 fF/m2 for tox=0.02m = 0.35 fF/m2 for tox=0.1mProcess transconductanceparameter: k’n= nCox =ox/tox
= 100V2 for tox=0.02m = 20V2 for tox=0.1m
Typical Process-TechnologyParameter Values
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-17
PMOS Field Effect Transistors
Gate (G)Drain (D)
Body (B)
Source (S)
p+
L
Channel region
n-type substrate (Body)
MetalOxide (SiO2)
p+
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-18
Sub-threshold Region
I eD
V
nGB
t constant 0 In the sub-threshold regime
3t
weak inversion
junction leakage
VDS
ID
VGS sub-threshold
Moderate inversion
Bipolar-like behavior
MOS behavior
Small current level < ~1A
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-19
CMOS technology
Figure taken from supplemental material for Digital Integrated Circuits, A Design Perspective, Jan M. Rabaey,1996, Prentice Hall
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-20
MOSFET Circuit symbols
D
S
G
D
S
GB
S
D
G
S
D
G B
NMOS PMOS
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-21
The iD-vDS Characteristics (NMOS)
Figure taken from supplemental material for Digital Integrated Circuits, A Design Perspective, Jan M. Rabaey,1996, Prentice Hall
0.0 1.0 2.0 3.0 4.0 5.0
v DS (V)
1
2
i D (
mA
)
Triode
V GS = 5V
VGS = 3V
VGS = 4V
V GS = 2V
V GS = 1V
i D as a function of vDS
Squ
are
Dep
ende
nce
V DS = V GS -V t
Saturation
vDS
vGS
+
-
+
-
iG=0
iD
iS=iD
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-22
iD vs. vGS Characteristic for an NMOS transistor in saturation
iDS
vGS (V)
vDS vGS-Vt
Vt
2'2
1tGSnD VV
L
Wki
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-23
Large Signal Model of a MOSFET in Saturation
2'2
1tGSnD VV
L
Wki
G
S
D
iG=0 iD
+
-
+
-
vGS vDS
vDS vGS-Vt
vGS Vt
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-24
Finite Output Resistance in Saturation
Source Channel Drain
vDSsat vGS-Vt +- +- vDS-vDSsat
L
L
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-25
Channel Length (Drain Current) Modulation due to changes in VDS
saturationtGSDS VVV
triode
VA = -(1/)
DStGSnDS vVVL
Wki 1
2
1 2'
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-26
Large Signal Model of the MOSFET Incorporating the Output Resistance
2'2
1tGSnD VV
L
Wki
G
S
D
iG=0 iD
+
-
+
-
vGS vDS
vDS vGS-Vt
vGS Vt
rO
1 DD
AO I
I
Vr
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-27
Exercises
5.3 An enhancement mode transistor with Vt=2V has its source terminal grounded and a 3V DC source connected to the gate. In which region of operation does the device operate for:
a) VD=0.5V VDS = 0.5V < VGS-Vt, in triode region
b) VD=1V VDS = 1V = VGS-Vt, in saturation region (pinch-off)
c) VD=5V VDS = 5V > VGS-Vt, in saturation region
5.4 If the transistor above has k’n=20A/V2, W=100m and L=10m, find the value of iD in the above cases - ignore the dependence of iD on vDS in saturation.
vD
+
-
+
-
3V
μAv
vVvL
Wki DS
DStGSnD 752
5.05.023
10
1001020
2' a)
26
2
AVvL
Wki tGSnD 10023
10
100
2
1020'
2
1 b) 2
62
AiD 100 c)
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-28
Exercises
5.6 An enhancement MOSFET with k’n(W/L)=0.2mA/V2, Vt=1.5V, and l=0.02V-1 is operated with vGS=3.5V. Find iD at vDS=2V and vDS=10V. Determine rO at this value of vGS.
mAvVVL
Wki DStGSnDS 416.0202.015.15.3
2
102.01
2
1 23
2'
mAvVVL
Wki DStGSnDS 480.01002.015.15.3
2
102.01
2
1 23
2'
kmAmA
VV
i
vr
D
DSO 125
416.0480.0
210
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-29
The iD-vDS Characteristics (PMOS)
Figure taken from supplemental material for Digital Integrated Circuits, A Design Perspective, Jan M. Rabaey,1996, Prentice Hall
0.0-1.0 -2.0 -3.0 -4.0 -5.0v DS (V)
-1
-2
i D (
mA
)
Triode
V GS = -5V
VGS = -3V
VGS = -4V
V GS = -2V
V GS = -1V
V DS = V GS -V t
Saturation
vDS
vGS
+
-
+
-
iG=0
iD
iS=iD
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-30
n-channel Enhancement Mode MOS Transistors
Enhancement Mode Transistors. A normally open switch. At zero volts on the gate no current flows ( a positive Voltage must be applied to the gate to enhance a channel of electrons)
n n
p substrate
Drain
Source
Gate Substrate
Gate DrainSource
n-channel
IDS
+VGS-VGS0
Source - where electrons come from (-)Drain - where electrons flow to (+)
Channel is enhanced (resistive)
Channel is off
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-31
n-channel Depletion Mode MOS Transistors
Depletion Mode Transistors. A normally closed switch. At zero volts on the gate a current flows ( a negative Voltage must be applied to the gate to deplete the channel of electrons)
n n
p substrate
Drain
Source
Gate Substrate
Gate DrainSource
n-channel
IDS
+VGS-VGS0
Source - where electrons come from (-)Drain - where electrons flow to (+)
Channel is depleted (Off)
Channel is made stronger
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-32
p-channel Enhancement Mode MOS Transistors
Enhancement Mode Transistors. A normally open switch. At zero volts on the gate no current flows ( a negative Voltage must be applied to the gate to enhance a channel of holes)
p p
n substrate
Drain
Source
Gate Substrate
Gate DrainSource
p-channel
IDS
+VGS-VGS
0
Source - where holes come from (+)Drain - where holes flow to (-)
Channel is enhanced
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-33
p-channel Depletion Mode MOS Transistors
Depletion Mode Transistors. A normally closed switch. At zero volts on the gate a current flows ( a positive Voltage must be applied to the gate to deplete the channel of electrons)
p p
n substrate
Drain
Source
Gate Substrate
Gate DrainSource
p-channel
IDS
+VGS-VGS
0
Source - where holes come from (+)Drain - where holes flow to (-)
Channel is depleted
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-34
The Body or Back Gating Effect on Threshold Voltage
Gate (G)Source (S)
Body (B)
Drain (D)
n+ Channel region
p-type substrate (Body)
n+
Vbody-Source=0
Vt0
ox
SiA
fSBftt
C
qN
VVV
2
220
Gate (G)Source (S)
Drain (D)
n+ Channel region
p-type substrate (Body)
n+
Vbody-Source Slightly(<0.4V)ForwardBiased
Gate (G)Source (S)
Drain (D)
n+ Channel region
p-type substrate (Body)
n+
Vbody-Source ReverseBiased
A slightslight body to source forward bias raises the potential of the electrons in the substrate reducing the gate voltage necessary to invertthe surface
Vt
A reverse body to source bias lowers the potential of the electrons in the substrate increasing the gate voltage necessary to invertthe surface
Gamma -Body EffectParameter
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-35
Example 5.1
Design the circuit shown below so that the transistor operates at ID = 0.4 mA and VD= 1V. The NMOS transistor has Vt = 2 V, nCox = 20 A/V2, L = 10m, and W = 400 m. Assume = 0.
VV DD5
VV SS5
RD
RS
I D
I D
Since VD = 1V, we are operating in the saturation region.
1or 3
130
3420
210
4001020
2
14.0
2
1
22
23
2
GSGS
GSGS
GSGSGS
GS
tGSoxnD
VV
VV
VVV
V
VVL
WCI
kI
VVR
D
SSSS 5
4.0
)5(3
Choose VGS = 3V. Since gate is grounded, potential at the source must be -3V.
To establish +1V at the drain,
kI
VVR
D
DDDD 10
4.0
15
V D
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-36
Example 5.2
Design the circuit shown below to obtain a current ID = 0.4 mA. Find the value required for R and find the dc voltage VD. Let the NMOS transistor have Vt = 2 V, nCox = 20 A/V2, L = 10m, and W = 100 m. Assume = 0.
VV DD10
RV D
I D
Since VDG = 0V, we are operating in the saturation region.
0or 4
040
424
210
1001020
2
14.0
2
1
22
23
2
GSGS
GSGS
GSGSGS
GS
tGSoxnD
VV
VV
VVV
V
VVL
WCI
Choose VGS = 4V since 0V < Vt and VD = 4V.
Thus,
kI
VVR
D
DDD 154.0
410
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-37
Example 5.3
Design the circuit shown below to establish a drain voltage of 0.1V. What is the effective resistance between drain and source at this operating point? Let V t = 1 V, and kn’(W/L) = 1 mA/V2.
The MOSFET is operating in the triode region, since the drain voltage is lower than the gate voltage, and Vt is 1V.
mA 395.001.02
11.0151
I D
VV DD5
RD
VV D1.0
I D
253395.0
1.0
D
DSDS I
Vr
Effective drain-to-source resistance,
k 4.12395.0
1.05
D
DDDD I
VVR
The required resistor value,
tGSDS VVV Triode, if
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-38
Example 5.4 NMOS
Analyze the following circuit to determine all the node voltages and branch currents, given that Vt=1V and k’n(W/L) is 1mA/V2. Neglect the channel length modulation effect (i.e. assume =0)
D
SG
+vS
-
RG1 = 10 M
RG2 = 10 M
RD = 6 k
RS = 6 k
VDD = +10 V
assumed
Since the gate current is zero (why?), the voltage at the gate is simply determined by voltage division between RG1 And RG2, and since they are equal VG is VDD/2 or 5 Volts.
Since the gate voltage is significantly higher than ground it is likely that the transistor is on, but we don not know if it is in the triode region of operation or in saturation.
We will assume that it is saturated and solve the problem and then check the validity of our assumptions (often the hard part for beginners). The saturation equations are easier to work with and that makes a good choice for starting out. If our assumptions do not check out we have to go back and use the triode region equations
The drain current has to be equal to the source current since IG is zero
VGS = 5 - 6,000(ID) And in saturation
+5 V
ID =IS
IS =ID
2'2
1tGSnD VV
L
WkI
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-39
Example 5.4 continued
Again, in saturation
Which is a quadratic Eq. in ID
D
SG
+vS
-
RG1 = 10 M
RG2 = 10 M
RD = 6 k
RS = 6 k
VDD = +10 V
assumed
2'2
1tGSnD VV
L
WkI
22
1000,65001.02
1
DD I
V
AI +5 V
082518 2 DD II This yields two values for ID, 0.89 mA
and 0.5 mA Which is valid for our assumption of
saturation? For ID of 0.89 mA the source voltage
would be 6,000(0.00089) or 5.34 Volts which is higher than the gate voltage and since the gate to source voltage to turn the device on (i.e. threshold voltage) is +1 Volt the device would be off not saturated this answer is not valid.
For ID of 0.5 mA the source voltage would be 6,000(0.0005) or 3 Volts which means the gate to source voltage is 5-3 or 2 Volts which is greater than the threshold voltage (+1 Volt) and the device is on. But is it saturated?
The drain is at 10-(6,000)(0.0005) or 7 Volts VDS=7-3 or 4 Volts
Since VDS (4V) is greater than VGS-Vt (2V-1V) the device is by definition in saturation so our initial assumption was correct
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-40
Example 5.5 (PMOS)
Design the following circuit so that the transistor operates in saturation with ID=0.5mA and VD=+3V. Let the enhancement type PMOS transistor have Vt=-1V and k’p=1mA/V2. Assume = 0. What is the largest value that RD can have while still maintaining saturation-region operation?
We were given the conditions to be met so lets start there, ID=0.5mA
VG to ground is VDD -VSG = 5-(2)=+3V The gate voltage can be set by picking appropriate
values of RG1 and RG2 in a voltage divider, for example, RG1 = 2M and RG2 = 3M
The drain resistor value can be found from
S
DG
+vD = 3 V-
RG1
RG2 RD
VDD = +5 V
assumed
22
1001.02
10005.0
GSVV
A
VVV
V
GSGS
GS
2,0 11
1001.0
0005.02
negative is For PMOS GStGS VVV
kI
VR
D
DD 6
0005.0
3
The border for saturation to linear occurs at VDS=VGS-Vt so VDSmax=-2-(-1) = -1V, thereforeVD to ground max is VDD-VSD=5-(1)=4V
At VD=4V and ID=0.5mA, RD=8k
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-41
Example 5.6 (depletion NMOS)
The depletion MOSFET in the circuit is required to supply the variable resistor RD with a constant current of 100A. If k’n = 20 A/V2 and Vt = -1 V, find the W/L ratio required. Also find the range that RD can have while the current through it remains constant at 100A. Assume l = 0.
The MOSFET in this circuit is conducting (VGS = 0). It must be operated in the saturation mode in order to conduct a constant current ID while RD (and VD) is varying.
The saturated mode of operation will be maintained for
D
SG
+
vD
-
RD
VDD = +5 V
assumed
10
10202
1100
2
1
2
2
L
WL
W
VVL
WkI tGSnD
V1
,110
D
tGSDS
V
VVV
k401.0
15minmax
D
DDDD
DDDDD
I
VVR
IRVV
Thus, RD can vary in range from 0 to 40 k
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-42
Example 5.7 (depletion mode FETs)
Design the circuit shown below to establish a dc voltage of +9.9V at the source. At this operating point, what is the effective resistance between the source and the drain of the transistor? Let Vt = -1V and K’n(W/L) be 1 mA/V2.
In this case the gate and the source are just slightly below the drain (0.1V) and VGS=0. VDS is not greater than VGS-Vt (0.1 is not greater than 0-(-1)) so the transistor is in the triode region and the current is
We can now find RS by
The effective source to drain resistance is
D
SG
+VS=9.9V-
RS
VDD = +10 V
assumed
mAI
I
D
D
1.0
1.02
11.010001.0 2
kkI
VR
D
SS 10099
0001.0
9.9
kI
Vr
D
DSDS 1
0001.0
1.0
krDS 1
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-43
Exercise 5.13
Consider the circuit below where the voltage VD1 is applied to the gate of another transistor, Q2. Assume that Q1 and Q2 are identical. Find the drain current and voltage of Q2. Assume = 0. (see example 5.3)
Since VD2 > VG2 (4V), we are indeed operating in the saturation region.
From example 5.3, VD=4V and ID1=0.4mA.
Q1 and Q2 are identical and have equal VGS.
Assuming that Q2 is also operating in the saturation mode, it’s drain current will be identical to that of Q1, 0.4mA
Thus, V 6104.0102 DV
VV DD10
kR 4.12
V D1
k 102R
Q2 Q
1
V D1
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-44
MOSFET as an Amplifier
Since changes in the drain to source voltage does not change the output much we will focus on the IDS-VGS characteristic
VDS does not change output much
VGS=> Linear Input Change
GS
LinearOutputChange
saturationtGSDS VVV IDS-VDS Characteristic
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-45
MOSFET Amplifier Configuration
We can obtain amplification of a small analog signal by use of an enhancement mode MOSFET.
A dc voltage (bias) VGS, is applied along with the input signal to be amplified, vgs superimposed on it. The output voltage is taken at the drain and consists of a dc and ac response.
A circuit for amplification is shown below This circuit is not practical because
The dc voltage source at the input is difficult to implement Integrated circuit resistors take up too much room MOSFETs are used for loads
+
vDS(t) -
vgs(t)
iDS(t)
VGS +DC
ac(DC+ac)
(DC+ac)
D
SG
VDD
RD
To be used as an amplifier the MOSFET must be biased in the saturation region
To find the dc bias we set the ac component of the input to zero and determine the dc drain current in saturation (we will neglect channel length modulation in this case, that is we will assume =0)
2'2
1tGSnD VV
L
WkI
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-46
The Signal Current at the Drain
The dc voltage at the drain, VD will be equal to VDD - RDID
To ensure saturation we must have
Now we go back to the situation where we have both the dc bias and the ac signal
The resulting total instantaneous drain current to be
We can focus on the ac response if we keep the input signal small, such that
tGSDS VVV
gsGSGS vVv
2''2'
2'
2
1
2
12
1
gsngstGSntGSnDS
tgsGSnDS
vL
WkvVV
L
WkVV
L
Wki
VvVL
Wki
dc bias ac response non-linear ac response
tGSgsgstGSngsn VVvvVVL
Wkv
L
Wk 2or
2
1 '2'
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-47
Transconductance
If the small-signal condition specified on the previous page is satisfied we can neglect the last non-linear term in the current equation and express iD as
Where
And we know that the ratio of id to vgs is the transconductance gm
In general
dsDSDS iIi
gstGSnd vVVL
Wki '
tGSngs
dm VV
L
Wk
v
ig '
GSGS VvGS
Dm v
ig
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-48
Voltage Gain
The total instantaneous drain voltage is
Using the small signal condition
The small-signal component of the drain voltage is
The voltage gain is then given by
DDDDD iRVv
dDDDdDDDDD iRVviIRVv or
gsDmDdd vRgRiv
Dmgs
d
in
out Rgv
v
v
v
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-49
DC Bias with an ac small signal
The DC bias level determines the ac parameters
By restricting the input signal swing to small values we can “linearize” the characteristic like we did for amplifier transfer characterisitcs
+
vDS(t) -
vgs(t)
iDS(t)
VGS +DC
ac(DC+ac)
(DC+ac)
VGS
vgs (t)
iDS
vGS (V)
tIDS
Bias Point - Q
tangent at Q
mgslope
ids (t)
Vt
0 0
D
SG
VDD
RD
tinput
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-50
The Input and Output Signals
When the gate to source signal is at its maximum the drain current is at its maximum. Maximum drain current means that the drop across the drain resistor is at its maximum or that the drain to source voltage of the MOSFET is at its minimum
The output is therefore 180 degrees out of phase from the input. We have an inverting small signal amplifier in this configuration
In order for the transistor to operate in the saturation region at all times there is a minimum drain voltage that must be maintained.
The input signal must be small enough to keep the output above the minimum
0
gmRD
VD
vD
vGS
VGSvGS tGS
gs VVv
22
vgs
t
t
tGD Vvv maxmin
Dmgs
d
in
out Rgv
v
v
v
cutoffprevent to
max DDD Vv
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-51
Small-Signal Saturation Equivalent Circuit Models
From a small-signal point of view the FET behaves like a voltage controlled current source as shown on the top figure to the left.
Th input resistance is high (ideally infinite) After the DC analysis is done to determine
the ac parameters and then the ac equivalent circuit is drawn.
A DC voltage source is ideally immune to changes in current so small ac voltage changes do not cause change in current (dI/dV is zero or R is zero) it is replaced by a SHORT circuit.
Current source are replaced by OPEN circuits
In the first model is was assumed that the drain current did not change with increasing VDS in saturation but we know that it does. The dependence can be modeled by a finite resistance ro, between source and drain, whose value is approximated by the equation shown at the left.
+vgs
- D
gmvgs
S
G
+vgs
-
D
gmvgs
S
G
ro
D
Ao I
Vr
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-52
Applying the small-signal model
On the previous page VA = 1/ . Which we can determine from the Id-Vd characteristic, typically in the 10k to 1,000k range
Remember, the ac parameters, gm and ro depend on the DC bias point
The gain for the following circuit is given below (note that ro reduces the gain)
oDmgs
d rRgv
v||
+
vDS(t) -
vgs(t)
iDS(t)
VGS +DC
ac(DC+ac)
(DC+ac)
D
SG
VDD
RD
+vgs(t) -
D
gmvgs
G
rovgs RD
ac small-signal circuit
+vds -
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-53
The transconductance of a bipolar transistor is proportional to the bias current (not the square root of it) and does not depend on the physical size or geometry
We can write gm in another useful way, as shown
Vt is ~25mV but
MOSFETs are smaller and use less power
The Transconductance - gm
The transconductance as we have seen already is the incremental change in drain current due to an incremental change in gate voltage or
If we solve the saturation current equation for VGS-Vt we get
and by substitution
So gm is proportional to the square root of the dc bias current
At any bias current gm is proportional to the square root of W/L
tGSnm VVL
Wkg
'
LW
k
IVV
n
DtGS
'
2
Dnm IL
Wkg '2
tGS
D
tGS
Dm
tGS
Dn
VV
I
VV
Ig
VV
I
L
Wk
21
2
22
'
rs transistoBJTfor
tocomparecan we which2
1
for
T
Cm
eff
Dm
tGSeff
VIg
V
Ig
VVV
mVVV tGS 100~2
1
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-54
Example 5.8 - Complete Amplifier Analysis
In the following circuit, a discrete MOSFET amplifier is shown in which the input signal vi is coupled to the gate via a large capacitor, and the output signal at the drain is coupled to the load resistance RL via another large capacitor. We will assume that the coupling capacitors are large enough so that they act as short circuits for the ac signal frequencies of interest. We wish to analyze the amplifier circuit to determine its small-signal voltage gain and its input resistance. The transistor has Vt=1.5V, kn
’(W/L) = 0.25mA/V2, and VA = 50V.
+
vDS(t) -
+vi
-
ac
D
SG
VDD=15VRD=10k
Rin
RG=10M
RL=10k
Start by doing the dc analysis
25.100025.02
1 GSD VI
2
2
5.1000125.0
5.100025.02
1
0 since
DD
GSD
GDGS
VI
VI
IVV
DDDD IIRV 000,101515 mAIVV DD 06.1 4.4
The other solution is not valid (contradictory)
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-55
ac equivalent circuit for Example 5.8
+
vDS(t) -
+vi
-
ac
D
SG
VDD=15VRD=10k
Rin
RG=10M
RL=10k
+vgs
-
D
gmvgs
G
ro+vgs
-RD
+vo -
RL
Rin
vi
RG
ac small-signal equivalent circuit
VDD is shorted to ground in the ac circuit
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-56
ac analysis for Example 5.8
The value of gm is given by
The MOSFET output resistance ro is
We can now us the ac equivalent circuit to determine the expression for the output voltage in terms of the gate to source small-signal voltage
V
mAg
VVL
Wkg
m
tGSnm
725.05.14.400025.0
'
kI
Vr
D
Ao 47
00106.0
50
igs
oLDgsmo
vv
rRRvgv
||||
V
VA
A
rRRgv
vA
v
v
oLDmi
ov
3.3
47||000,10||000,10000725.0
||||
Since RG is so large
The value of the voltage gain Av is given by
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-57
Evaluation of the Input Resistance for Example 5.8
To find the input resistance we note that the input current is given by
M33.23.4
000,000,10
3.4
3.43.31 1
G
i
iin
G
i
G
i
i
o
G
i
G
oii
R
i
vR
R
v-
R
v
v
v-
R
v
R
vvi
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-58
The Source Absorption Theorem (Appendix E)Used to derive the “T” Model for a MOSFET
12 KVV
1I
Y
1V
2I Node 2Node 1
12 KVV
1I
1Y
1V
2I Node 2Node 1
2Y
KYVI
VVYVI
VVYI
1
1
11
1211
211
111 IVY
KYY 11
2122
122
1 VVYVI
VVYI
22 11 VKYI
222 IVY
KYY 112
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-59
The “T” Equivalent Circuit Model
+vgs
- D
gmvgs
S
G +vgs
- Dgmvgs
S
G Xig = 0 id
gmvgs
is
+vgs
- Dgmvgs
S
GX id
gmvgs
is
ig = 0
+vgs
-
G
ig = 0
S is
D
gmvgs
id
mg
1 or
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-60
Modeling the Body Effect
The body effect (or back gate effect) occurs when the source is NOT at the same potential as the substrate (body). The substrate acts as a second gate and therefore we include a second dependent current source in our model, as shown below
+vgs
-
D
gmvgs
S
G
ro gmbvbs Bvbs
+
constant constant,
DSGS vvBS
Dmb v
ig
SBfSB
t
mmb
VV
V
gg
22
D
SG
the dependence is linked to the threshold voltage
3.01.0
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-61
Exercise 5.17
For the following amplifier, let VDD = 5V, RD = 10k, Vt = 1 V, kn’ = 20 A/V2, W/L = 20, VGS = 2V and = 0.
Find the dc current ID and the dc voltage VD
Find gm
find the voltage gain If vgs = 0.2sint volts, find vd assuming that the small-signal approximation holds. What
are the maximum and minimum values of vD. Use the following equation to find the various components of the drain current
+
vDS(t) -
vgs(t)
iDS(t)
VGS +DC
ac(DC+ac)
(DC+ac)
D
SG
VDD
RD
2''2'
2
1
2
1gsngstGSntGSnDS v
L
WkvVV
L
WkVV
L
Wki
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-62
Exercise 5.17 continued
Using the following identity show that there is a slight shift in ID (by how much?) and that there is a second harmonic component (2nd harmonic has a frequency of 2)
Express the amplitude of the second harmonic component as a percentage of the amplitude of the fundamental (this is known as the second-harmonic distortion)
tt 2cos2
1
2
1sin 2
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-63
Biasing MOSFET Amplifier Circuits
Biasing is the establishment of an appropriate dc operating point for the transistor. An appropriate dc bias point has a stable and predictable dc drain current ID, and a dc
drain to source voltage that ensures operation in the saturation mode for all expected input signal levels.
Discrete component MOSFET circuits are not common but we will use them to introduce various biasing techniques.
VDS does not change output much
VGS=> Linear Input Change
GS
LinearOutputChange
saturationtGSDS VVV IDS-VDS Characteristic
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-64
MOSFET Biasing - Single Supply
Plus side of MOSFET bias circuit design - the gate current is zero (easier to design)
Negative side of MOSFET bias circuit design - Vt (VGS response) varies more than vBE does in BJT circuits.
The circuit shown at the right is commonly used when a single power supply is available. A voltage divider is used to establish a fixed dc voltage at the gate. Since the gate current is zero the two gate bias resistors
RG1 and RG2 can be selected to be very large (M range) This will provide a large amplifier input resistance
A resistor, called a self bias resistor is connected to the source. If the device is turned on more (more source current) the drop across source resistor will increase and reduce the current. A balance (negative feedback) situation will be created.
RD is selected to be as high as possible to obtain high gain but small enough to allow for a large enough output signal swing at the drain while still keeping the MOSFET in saturation at all times.
V DD
RG1
RS
I D
RG2
RD
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-65
MOSFET Biasing - Dual Supplies
For symmetric supplies (positive and negative of the same magnitude) a simpler bias arrangement can be used.
The resistor RG establishes a dc ground at the gate of the transistor.
Directly grounding the gate will also establish a dc bias but RG is used to increase the input resistance seen by a signal source that may be capacitively coupled to the gate
RD is selected to be as high as possible to obtain high gain but small enough to allow for a large enough output signal swing at the drain while still keeping the MOSFET in saturation at all times.
V DD
RS
I D
RG
RD
V SS
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-66
MOSFET Biasing with a Constant Current Source
Having a constant current source establishes the source and drain current level.
We will look at how to construct a constant current source shortly
As before RD is selected to be as high as possible to obtain high gain but small enough to allow for a large enough output signal swing at the drain while still keeping the MOSFET in saturation at all times.
As before, The resistor RG establishes a dc ground at the gate of the transistor.
Directly grounding the gate will also establish a dc bias but RG is used to increase the input resistance seen by a signal source that may be capacitively coupled to the gate
I D
RG
RD
V SS
I
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-67
Common-Source Circuit with Resistive Gate Feedback
The feedback resistor RG forces the dc voltage at the gate to be the same as that of the drain (since IG = 0).
The input can be capacitively coupled to the gate and the output can be taken at the drain to form a simple common-source amplifier.
The output signal swing is limited on the low side since the drain (which is tied to the gate) must be high enough to satisfy the threshold voltage gate to source. If the output goes too low the transistor slips out of saturation into the triode region of operation and the output will be distorted.
As before RD is selected to be as high as possible to obtain high gain but small enough to allow for a large enough output signal swing at the drain while still keeping the MOSFET in saturation at all times.
V DD
I D
RG
RD
0
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-68
Biasing of Discrete MOSFET Amplifiers
Four circuits for biasing the MOSFET in discrete-circuit design.
classical arrangement 2 power suppliescommon-source circuit
V DD
RG1
RS
I D
RG2
RD
V DD
RS
I D
RG
RD
V SS
I D
RG
RD
V SS
I
V DD
I D
RG
RD
0
constant current source
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-69
Biasing of Discrete MOSFET Amplifiers
Exercise 5.22 Design the circuit below for a MOSFET having k’n(W/L) = 0.5 mA/V2 and Vt = 2V, and utilizing two power supplies, ± 10V. Design for ID = 1mA and allow for a signal swing at the drain of ±2V. The amplifier is required to present a 1M input resistance to a signal source that is capacitively coupled to the gate. Assume =0. V10
RS
I D
RG
RD
V10
M1
kR
VV
V
V
IR
VL
Wk
S
SG
GS
GS
DG
tn
6001.
104
V4 ,0
V4
25.02
11
Thus,
mA1 ,M1
V2 and mA/V5.0'
2
2
V220min tGD VVV
kRV DD 10001.
010 thusV,0
To allow for a ±2V signal swing at the drain, Where we have neglected the signal component of VG
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-70
Design Philosophy
The circuits that we have just looked at are not suitable for integrated circuit design. They use too many resistors which take up room and are therefore expensive. It turns out that since we are making small MOSFETs anyways, that if we can use
transistors that act sort of like resistors we can make much smaller (more dense) circuits.
The coupling capacitors also take up way to much room so coupling and bypass capacitors are not used in the design of MOSFET amplifier circuits. You can learn more about integrated circuit fabrication in EGRE435 during the fall
of 2000. You can learn more about MOS analog circuit design in EGRE307 during the fall of
2000. You can learn more about MOS digital circuit design in VLSI Design EGRE429.
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-71
Basic MOSFET Constant Current Source
Use a reference current through one transistor (Generated through Q1) to set the voltage across the gate to source of another transistor (Q2) and hence replicate the reference current through the drain of the second transistor.
Q1 is saturated since VGS = VDS
V DD
R
V O
Q1
-
V GS
0 0
0
I REF
I D1
Q2
I O
R
VVII
VVL
WkI
GSDDREFD
tGSnD
1
2
11 '
2
1
1
2
2
22 '
2
1
LW
LW
I
I
VVL
WkII
REF
O
tGSnDO
constant current source
V DD
_
V O
Q
1
-
V GS
I REF
I D1
Q2
I O
current mirror
For Q2,
For Q1,
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-72
Effect of VO on IO
In the previous current source description we assumed that the transistor Q2 is operting in saturation
GSVtGS VV
OI
Or
1Slope
OV
tGSO VVV
O
AO
O
OO I
Vr
I
VR 2
2
REFI
Region of “constant” current operation
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-73
Example 5.9
Given VDD=5V and using IREF=100A, it is required to design the circuit shown below to obtain an output current whose nominal value is 100A. Find R if Q1 and Q2 are matched, have channel lengths of 10m and channel widths of 100m, Vt=1V and k’n=20A/V2. What is the lowest possible value of VO? Assuming the fabrication technology results in an Early voltage that can be expressed as VA=10L, where L is in microns and VA in volts, find the output resistance of the current source. Also find the change in output current resulting from a 3V change in VO.
21 1
10
10020
2
1100 GSREFD VII
V112
k30A100
25
V2
min
tGSO
GS
VVV
R
V
Since L=10m,
M1A100
V100
V1001010
O
A
r
V
The output current will be 100A at VO=VGS=2V. If VO changes by +3V, the corresponding change in IO will be 3%,
A3M1
V3
O
OO r
VI
V DD
R
V O
Q1
-
V GS
0 0
0
I REF
I D1
Q2
I O
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-74
Current-Steering Circuits
I REF
V DD
V DD
Q4
-
5V GS
R
Q1
-
1V GS
I D1
Q2
I 2
Q3
V SS
I 5I 4
I 3
Q5
1
33
1
22 and
LW
LWII
LW
LWII REFREF
where, 34
4
545 II
LW
LWII
tnGSSSDD VVVVV 132 ,
tpGSDDD VVVV 55
threshold voltage for n-channel devices
threshold voltage for p-channel devices
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-75
Basic Configurations of Single-Stage IC MOS Amplifiers
I
V DD
vOvI
I
V DD
vO
vI V SS
V DD
vO
vI
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-76
Resistive Load Common Source Amplifier
An ideal current source has an infinite resistance, the current does not depend on the voltage at the node to which it is connected, but what happens if we use a resistive load
REFI
1DiQ1 in triode
Q1 in saturation
0
IAGS VVv 11
DDV ODS vv 1
ICGS VVv 31
Load curve
A
B
1 2 3 4 5V
IBGS VVv 21
IDGS VVv 41
CD
A’
D’
R
V DD
vOvI
common-source
The resistor constrains the current flow through the transistor and vice-versa. For the solid resistor load curve plotted on the transistor characteristic shown below the resistance is less than that of the dashed curve.
On the solid curve the valid operating points (curve intersections) are labeled with a letter and on the dashed curve the letters have a prime On the next page we plot the voltage transfer characteristic of this amplifier
Vout
Vin
VVtn 8.0
VVtn 8.0
G
S
D
+VR
-
VR=VDD-VDS
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-77
Resistive Load Common Source Amplifier continued
The plot of the transfer characteristic of the common-source amplifier with a resistive load is shown below
Since the resistor is not an ideal current source the gain varies with the load resistance The higher the load resistance the higher the gain but the smaller the allowed input signal
swing (an still have the transistor saturated)
DDV
tnV
A’
B’
0 1 2 3 4 5
5
4
3
2
1
0
A
B
C D
D’C’
Vin
Vout
R1>R2
gain is proportional to the slopeGain1>Gain2
triode
saturation
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-78
The CMOS Common-Source Amplifier(PMOS current source load)
If the PMOS active load device is made with a long channel then lambda is small (the magnitude of VA is large or the transistor output resistance ro is large). In other words a long channel load acts more like an ideal current source.
vO
vI
V DD
Q3
iI REF
-
V SG
Q1
Q2
-
v
+-
i-v characteristic of the active-load Q2CMOS common-source amplifier circuit
SGV
tpSG VV
REFI2
1Slope
Or
v
iQ2 in triode
Q2 in saturation
SGSG Vv
0
one curve not a family of curves
REF
AO I
Vr 2
2
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-79
Graphical construction to determine transfer characteristic
We expect to have a transfer characteristic that has a high gain since output resistance of the load transistor can be made high (long channel) The load curve is like a high value resistor that has been translated upwards We are most interested in the area of intersection between A and B for amplification
SGDD VV
tpSGDD VVV
REFI
1DiQ1 in triode
Q1 in saturation
0
AGS Vv 11
DDVODS vv 1OBV
BGS Vv 11
Load curve
AB
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-80
Transfer Characteristic of the active load common source amplifier
When the input is low the load transistor is in the triode region, as the input voltage is increased the active load becomes saturated. The gain is relatively high and depends on the output resistance of the transistor used in the current mirror
I
II
III
IV
Q1 Cutoff
Q1 Saturation
Q2 Triode
Q1 Triode
Q2 Saturation
Q1 Saturation
Q2 Saturation
tpSGDD VVV
I II III IVDDV
OBV
BV1AV1tnV
A’
B’
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-81
Small-signal equivalent circuit of the common-source config.
REF
AnV
AA
REF
AA
n
v
REF
AoREFnm
I
V
L
WkA
VV
IVV
LW
k
A
I
VrI
L
Wkg
1
21
21
1
11
11
'2
1
that assume weIf
111
'2
becomesgain then The
'2
+-
11 gsm vg1or 2or
-
1vgs
iv
-
vo
D1,D2
S1,S2 211 oomi
oV rrg
v
vA
If we use physically based parameters for the transistorswe get a design equation in terms of the transistor’s length,width, transconductance, output resistance and referencecurrent source value
Voltage gains on the order of 20-100 are obtained usingCMOS common-source configuration
The source of each device is connected to the bodyso the body effect on the threshold voltage is not a factor
Since ro1 and ro2 are usually large the gain can be large without taking up a lot of room on the chip with anintegrated resistor.
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-82
Effect of RS on AC gain
In section 5.6 we discussed various DC biasing schemes and in those schemes we saw that the source resistor, RS (like its counterpart RE in the BJT case) provides negative feedback to the gate to source voltage and helps to stabilize the DC value of ID.
If the DC bias point of the gate is increased the source current will increase but not by as much as when there is no source resistance
This source resistance DOES affect the AC gain! Consider the case of a MOSFET biased to have a gm of 30mA/V, rO=16K, and RD=470 AC model WITHOUT RS:
DR
V DD
vOvI
common-source with a source resistance
GS
D
+VRD
-
SR
+vgs(t) -
D
gmvgs
G
rovi RD
+vo -
VVKXrRgv
vODm
i
o 7.13)16470(1030 3
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-83
Effect of RS on AC gain (cont.)
Now consider AC gain WITH RS, let RS=10:
+vgs(t) -
D
gmvgs
G
rovi RD
+vo -
VV
vv
i
o 54.10
More easily analyzed with the T model:
+vgs
-
G
S
D
gmvgs
mg
1 or DR
+
vo
-
vi
SRii
Sm
migs vv
Rg
gvv 7692.0
1033.33
33.331
1
iiODgsmO vKvXrRvgv 54.10)16470(7692.01030 3
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-84
The use of a Source By-Pass Capacitor
In the circuit shown on this page, at low frequencies, the source capacitor CS is an open circuit and the source resistance has a voltage drop across it which reduces the gate to source voltage across the transistor.
On the next page the ac equivalent circuit is shown DR
V DD
vOvI
common-source with a source resistance
G
S
D
+VRD
-
SRSC
SZ
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-85
The use of a Source By-Pass Capacitor (ac circuit)
+-
gsmvgDR
-
vgs
iv
-
vo
S1
SRSC
SZ CS open circuit (low frequencies)Note that Vgs does not equal vi now
CS short circuit (high frequencies)
0 as 1
CsCs ZCj
Z
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-86
The CMOS Common-Gate Amplifier
V DD
vOvBIAS
Q3
iI REF
-
V SG
Q1
Q2
-
vI B1+
-
11 gsm vg1or
-
1vgs
iv
-
vo
D1,D2
2or11 bsmb vg
G1
S1 vbs1+
-
iRcommon-gate amplifier
vi=VSG vo=VDGsmall-signal equivalent circuit
In this case a constant dc level is applied to the gate of the transistor and the input signal is applied to the source
The signal source at the gate will be zero (hence the name common gate) There will be a potential difference between the source and the bulk (body) so
we need to use the model which includes that effect.
Body effect
Vgs1=-vi vbs1=-vi
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-87
Simplified circuit
The body effect adds to the gain but reduces the input resistance The active load (ro2) reduces the gain but slightly increases the input resistance By comparison the Common-Gate configuration has a gain similar to that of the common-source amplifier but the input resistance is much lower The common-gate configuration is used in a combination circuit called a cascode amplifier that we will study later in EGRE307.
+-
imbm vgg 11
1or
2oriv
-
vo
D1,D2
S1
iR
1ooi rvv
2111
211
11
211
1
//
//1
oombmv
ooo
mbmi
ov
o
oimbm
o
oi
rrggA
rrr
ggv
vA
r
vvgg
r
vv
ii
2
2
11
111
11
o
o
mbmi
ii
o
oiimbmi
r
r
ggi
vR
r
vvvggi
output node equation
if 1/ro1<<gm1
Input resistance(input node equation)
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-88
The Common-Drain or Source-Follower Configuration
V DD
V DD
Q3
Q2
V SS
I REF Q5
vi
vo
B1
+-
11 gsm vg1or
-
1vgs
iv
-
vo
2or
11 bsmb vg
G1
S1 vbs1+
-
D1
common-drainor
source-followersmall-signal equivalent circuit
(again the body effect is included)
The common-drain or source follower configuration is used as buffer amplifier. Although its voltage gain is less than unity it has a low output resistance and is therefore capable of driving low impedance loads with little loss of gain.
Typically found in the output stage of a multi-stage amplifier. The fact that its impedance is buffered can be used to extend the high-frequency
response range of amplifiers and speed up digital circuits. Vdd is at signal ground hence the name commoncommon drain The input impedance is very high since it is the gate of a MOSFET (THIS IS A
VERY BIG ADVANTAGE OVER BJTs)
Signal Ground
Use the source absorption theorem to transform the dependent source into a resistance 1/gmb1
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-89
Simplified circuit
+-
11 gsm vg-
1vgs
iv
-
vo
SR
G1
S1
211
////1
oomb
S rrg
R
1
1
,
11
1
1
1111
1
2121
1
1
1
11
11111
111
v
mmbmbm
mv
oombm
mv
Sm
Sm
i
ov
gsSmi
gsSmgssgsi
gsSmso
A
gggg
gA
rrgg
gA
Rg
Rg
v
vA
vRgv
vRgvvvv
vRgvv
typically 0.1<<0.3
The body effect reduces the gain by ~10 to 30 percent
0
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-90
NMOS Load Devices - Saturated Enhancement Mode
v
i+
-v
i
V t
ttn VvVvL
Wki ,'
2
1 2
0
Saturated Enhancement Mode LoadVGS=VDS therefore always saturated
G
D
S
locus of points on many curves
VGS=VDS
2tDD VV
VGS2=VDS2
DDV
i
0
i+
VDS2
-
DDV
G2
D2
S2 +
VDS1=Vout
-
G1
S1
D1
x
xx
VGS1=Vin
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-91
NMOS Amplifier with Enhancement Load
22
1
2
1
2
1
2
1
1
1
LW
LWA
LW
LWA
vLW
LWV
LW
LWVVv
v
v
IttDDO
Q2
12 DD ii Q
2
-
vI
-
vO
V DD
2tV
1Di
0
...1 GSv
DDV 1DSv3V
VvGS 1
Load curve
A
B
11 tGS Vv
1V
I Q1 cutoff
3V
1 V
VIv
A’
B’
0
Ov
IIQ1 in
saturation
IIIQ1 in
triode region
Due to the body effect on Vt
VSB for Q2 is not equal to zero(reduces the gain)
2t DDV V
DDV
1t V
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-92
NMOS Amplifier with Enhancement Load
Positives
Uses the same type of device for the load as the driver (enhancement)
Negatives
Lower Gain than the Depletion Mode LoadSmaller output signal swing (The output does not go all the way up to VDD)
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-93
NMOS Load Devices - Saturated Depletion Mode
v
i +
-
v
i
V tD0
tDnDSS VL
WkI 2'
2
1
2
1Slope
Ortriode saturation
DepletionMode LoadVGS=0Always on
tDnDSS
ADSS
A
tDn
VL
WkI
V
vIi
V
vV
L
Wki
2
2
'2
1
1
1'2
1
D
GS
In saturationDepletionMode Load, VGS=0 Always on
VGS
IDS
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-94
NMOS Amplifier with Depletion Load
Q2
Di
Q1
-
vI
-
vO
V DD
+-
11 gsm vg1or 2or
-
1vgs
iv-
vo
D1,G2.S2
D2,B2
G1
S1,B1
22 bsmb vg
1
////1
2
1
2
1
2
1
211
1
LW
LWA
g
g
g
gA
rrg
gv
vA
v
m
m
mb
mv
oomb
mI
Ov
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-95
NMOS Amplifier with Depletion Load
tDDD VV
I II III IVDDV
OBVtEV
A’
B’
tDDD VV
1Di
0
...1 GSv
DDV Ov
...1 GSvLoad curve
A
CB
C’
Ov
Iv
Q1 OffQ2 Triode
Q1 SaturationQ2 Triode
Q1 SaturationQ2 Saturation
Q1 TriodeQ2 Saturation
I
II
III
IV
Positives
Higher Gain than the Saturated Enhancement Mode LoadLarger output signal swing (all the way up to VDD)
Negatives
Requires a different type of device (depletion) for the loadand is therefore more complicated
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-96
The CMOS Digital Logic Inverter
For any IC technology used in digital circuit design, the basic circuit element is the logic inverter.
The inverter uses two matched enhancement-type MOSFETS; an n-channel and a p-channel. The body of each device is connected to its source which eliminates any body effect.
CMOS inverter simplified inverter circuit
V DD
vOvI
QP
QN
iDNiDP
vOvI
QP
QN
V DD
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-97
Circuit Operation
We assume that the n-channel device is the driver, and the p-channel device is the load. When the input is high, vO=VOL=0 Volts, and the power dissipation in the inverter is 0.
Operation of the CMOS inverter when vI is high
DDV0OLV Ov
i DDOHGSN VVv
0
Operatingpoint
Load curve 0SGPv
V DD
0vOrDSN
tnDD
nnDS VVLW
kr '1-
DDSGNVv
V DD
vO
QP
QN
i
V DD-
0
vSGP
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-98
Circuit Operation, cont’d
We assume that the n-channel device is the driver, and the p-channel device is the load. When the input is low, vO=VDD, and the power dissipation in the inverter is 0.
Operation of the CMOS inverter when vI is low
DDV0OLV Ov
i
0 OLGSN Vv
0
Operating point
Load curve
DDOH VV
V DD
DLOVv
rDSP
tpDD
ppDSP VVLW
kr '1
V DD
-
0
vSGN
vO
QP
QN
i
-
DDSGPVv
DDGSP Vv
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-99
Circuit Operation, cont’d
The basic CMOS logic inverter behaves as an ideal inverter
The output voltage levels are 0 and VDD, and the signal swing is the maximum possible. This results in wide noise margins.
The static power dissipation in the inverter is 0 A low-resistance path exists between the output terminal and ground (in the low-
output state) or VDD (in the high-output state). The low output resistance makes the inverter less sensitive to the effects of noise and other disturbances.
The active pull-up and pull-down devices provide the inverter with high output-driving capability in both directions.
The input resistance of the inverter is infinite (because IG=0). Thus the inverter can drive an arbitrarily large number of similar inverters with no loss in signal level.
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-100
Voltage Transfer CharacteristicPMOS Load Lines
VDSp
IDp
VGSp=-5
VGSp=-2VDSp
IDnVin=0
Vin=3
Vout
IDnVin=0
Vin=3
Vin = VDD-VGSpIDn = - IDp
Vout = VDD-VDSp
Vout
IDnV in = V DD -V GSp
IDn = - I Dp
V out = V DD -V DSp
Figure taken from supplemental material for Digital Integrated Circuits, A Design Perspective, Jan M. Rabaey,1996, Prentice Hall
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-101
In,pVin = 5
Vin = 4
Vin = 3
Vin = 0
Vin = 1
Vin = 2
NMOSPMOS
Vin = 0
Vin = 1
Vin = 2Vin = 3
Vin = 4
Vin = 4
Vin = 5
Vin = 2Vin = 3
Figure taken from supplemental material for Digital Integrated Circuits, A Design Perspective, Jan M. Rabaey,1996, Prentice Hall
CMOS Inverter Load Characteristics
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-102
The Voltage Transfer Characteristic
For QN,
tnIOtnIn
nDN
tnIOOOtnIn
nDN
VvvVvL
Wki
VvvvvVvL
Wki
for '2
1
and
for 2
1'
2
2
tpIOtpIDDp
pDP
tpIOODDODDtpIDDp
pDP
VvvVvVL
Wki
VvvvVvVVvVL
Wki
for '2
1
and
for 2
1'
2
2
For QP,
p
n
n
p
W
W
p
pn
n L
Wk
L
Wk
''
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-103
The Voltage Transfer Characteristic, cont’d
DDOH VV
DDVILVtV
A
B
Ov
C
D
t
DD VV
2
t
DD VV
2
0OLVIHV
Iv tDD VV
2DD
th
VV
0
Slope = -1
Slope = -1
QN off
QP off
QN in saturationQP in triode
QN in saturationQP in saturation
QP in saturationQN in triode
OLILL
IHOHH
VVNM
VVNM
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-104
The Complementary MOS (CMOS) Inverter
Complementary means both nMOS and pMOS transistors are used
A polite “tug O’War”! Only one device pulls at a time A High Voltage on
Vin turns On the NMOS device and turns Off the PMOS device
A Low Voltage on Vin turns off the NMOS and turns On the PMOS
Power is dissipated only when the output is switching from low to high or high to low
+5 V
Vin Vout
source of electrons
drain for electrons
gaten channel (p wafer)
drain for holes
source of holesgate p channel (n well)
+5 V
Vout = + 5VVin = 0
closed
open
Vout = 0 VVin = + 5V
closed
open
+5 V
s=5
s=0g=5
g=5
Vgsp= Vgp-Vsp
= 5-5 = 0
Vgsn= Vgn-Vsn
= 5-0 = 5
Vgsp= Vgp-Vsp
= 0-5 = -5g=0
s=5
Vgsn= Vgn-Vsn
= 0-0 = 0 g=0s=0
The source is where charge carriers come from and the drain is where they flow to, holes come from the higher voltage and flow towards a more negative terminal, electrons come from the more negative terminal and flow towards the positive
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-105
How are Noise Margins Determined?
The slope of the voltage transfer characteristic of an inverter is the gain.
There are three key points on the gain plot The point at which the
magnitude of the gain is first equal to unity (45 degrees)
The point at which the magnitude is maximum
The point second point at which the gain is again equal to unity
1 2 3 4 5VIN (Volts)0
1
2
3
4
5
VOUT
(Volts)
|slope| = 1
|slope| = 1
|slope| = Maximum = 5
5
|gain|slope
VIHVIL
VOL
VOH
1 VIN (Volts)
max
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-106
What Noise Margins really mean
On the previous page VIL was equal to 1.2V and VIH was equal to 3V
VOL was equal to 0.7V and VOH was equal to 4.9V
The Noise Margins are defined as follows
NML = VIL - VOL in our case = 1.2 - 0.7 = 0.5 Volts
NMH = VOL - VIL = 4.9 - 3.0 = 1.9 Volts
What the output produces
Low VOL =(0.7- 0) V
High VOH =(5- 4.9) V
What the input accepts
VIL = 1.2V
VIH = 3V and up
Marginal LowNML = 1.2-9.7=0.5V
“solid”signals
Marginal HighNMH = (5-3)-(5-4.9) =1.9V
0V
+5V
solid low
solid high
1 2 3 4 5VIN (Volts)0
1
2
3
4
5
VOUT
(Volts)|slope| = 1
|slope| = 1
|slope| = Maximum = 5
VIHVIL
VOL
VOH
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-107
How does an Inverter (with gain) restorea “poor” signal level?
The output of the first inverter will be _____?? If we take that as the input to the second inverter the output of the second inverter will be ___ ?? Volts.
Is it a solid high? The inverter supplies (+5
and ground) and the gain drives unknown and marginal signals towards solid levels
1 2 3 4 5 VIN (Volts)0
1
2
3
4
5
VOUT
(Volts)
|slope| = 1
Input to inverter # 1 = 3.1V
VIHVIL
VOL
VOH 3.1 ??
Assume that we have two identical inverters in series and that they both have the same voltage transfer characteristic given below.
Lets say that the input to the first inverter is 3.1 Volts, which is about as marginal a high signal as will be recognized as a high by the inverter.
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-108
Solution to previous page
1 2 3 4 5 VIN (Volts)0
1
2
3
4
5
VOUT
(Volts)
|slope| = 1
Input to inverter # 1 = 3.1V
VIHVIL
VOL
VOH
Output of inverter # 1 = 0.65V
Input toINV #2
3.1 0.65 5
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-109
Propagation Delay and Rise and Fall Times of a signal
Input Signal
Output Signal
Time
Time
50% 1/2(VOL+VOH)
90% of (VOH-VOL)
10% of (VOH-VOL)
VOH
VOL
vI
vO
VOL
VOH
tr tf
tPLHtPHL
tTHLtTLH
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-110
The Analog Switch
The MOSFET is often used as a voltage-controlled switch. The voltage applied to the gate of each QN and QP turns them on and off.
In the off position, the MOSFET behaves as an open circuit between drain and source In the on position, the MOSFET presents a resistance rDS between drain and source
Analog Switch
tGSn
DS
VVLW
kr
'
1
+-Av
-
vO
LR LC
for small vDS
More stringent requirements are placed on an analog switch, relative to a digital switch. When the switch is open, we want it to operate as an open circuit--the off-resistance
switch should be very high (ideally infinite) A high on-resistance would result in signal attenuation
The switch should be bidirectional (able to conduct in both directions)
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-111
Circuit Operation
Notice that terminals are not labeled; they are interchangeable because the MOSFET is a symmetrical device.
In general, the drain is the terminal which is at the higher voltage.
vC high; vA positive
Vvc 7 vO
LR LC
+-
b
a
VvA 4
vO
LR LC
+-
b
a
VvA 4
vC high; vA negative
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-112
Equivalent Circuits for Transmission Gate
vO
LR LC
b’
a’
+-
a
b-+5V 5V
(positive) Av
vO
LR LC
a’
b’
+-
b
a-+5V 5V
(negative) Av
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-113
CMOS Transmission Gate and Circuit Symbol
Compared to the single NMOS switch, the transmission gate provides better performance at the expense of greater circuit complexity and chip area.
OutputInput
V SSC (clock)
V DDC
N
PInput Output
C
C
C Characteristics
0 Bidirectional open circuit1 Bidirectional short circuit
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-114
MOSFET Internal Capacitances and High-Frequency Model
The MOSFET has internal capacitances, however, they are neglected in the small-signal model.
The gain of every MOSFET amplifier falls off at some high frequency. The MOSFET model must be augmented by including internal capacitances. There are basically two types of internal capacitances in the MOSFET:
The gate capacitive effect: the gate electrode (polysilicon) forms a parallel-plate capacitor with the channel, with the oxide layer serving as the capacitor dielectric.
The source-body and drain-body depletion-layer capacitances: these are the capacitances of the reversed-biased pn junctions formed by the n+ source region (source diffusion) and the p-type substrate, and by the n+ drain region (drain diffusion) and the substrate.
There will be five capacitances in total: Cgs, Cgd, Cgb, Csb, and Cdb, where the substrates indicate the location of the
capacitances in the model.
gsmvgor
-
vgs
bsmbvg
gdC
gbCsbC
dbC
B
G
S
D
gsC
vbs
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-115
The Gate Capacitive Effect
The gate capacitive effect can be modeled by three capacitances Cgs, Cgd, and Cgb.
In the triode region at small vDS
In saturation
In the cutoff region
Overlap capacitance
oxgdgs WLCCC2
1
03
2
gd
oxgs
C
WLCC
oxgb
gdgs
WLCC
CC
0
oxovov CWLC
May be zero depending on the bulk potential
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-116
The Junction Capacitances
0
0
1V
V
CC
SB
sbsb
0
0
1VV
CC
DB
dbdb
For source diffusion, the source-body capacitance, Csb
For drain diffusion, the drain-body capacitance, Cdb
Csb0 is the value of Csb at zero body biasVSB is the magnitude of the reverse-bias voltageV0 is the junction built-in voltage
Cdb0 is the capacitance value at zero reverse-bias voltageVDB is the magnitude of the reverse-bias voltageV0 is the junction built-in voltage
The above formulas assume small-signal operation.
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-117
The High-Frequency MOSFET Model
gsmvg or-
vgs
gdC
dbC
G
S
D
gsC
gsmvgor
-
vgs
bsmbvg
gdC
gbCsbC
dbC
B
G
S
D
gsC
vbs
gsmvg or-
vgs
gdCG
S
D
gsC
© REP 04/19/23 ENGR224
MOSFETs
Page MOSFET 5.1-118
Unity-Gain Frequency (fT)
The unity-gain frequency (fT) is defined as the frequency at which the short-circuit current-gain of the common-source configuration becomes unity.
gsmvg or-
vgs
gdC
gsC
oI
iI
gsmo
gsgdgsmo
VgI
VsCVgI
gdgs
igs CCs
IV
gdgs
m
i
o
CCs
g
I
I
gdgs
mT CC
g
2T
Tf
gdgs
mT CC
gf
2
The magnitude of the current gain becomes unity at thefrequency
