Simulation of N-type MOSFETs and Tunneling Field-Effect Transistorsalice.ye/resources/undergradthesis… · Simulation of N-type MOSFETs and Tunneling Field-Effect Transistors by

Simulation of N-type MOSFETs and Tunneling Field-Effect Transistors

byZhixin Alice Ye

Supervisor: Sorin VoinigescuApril 2015

Abstract

Simulation of N-type MOSFETs and Tunneling Field-Effect Transistors

Zhixin Alice Ye

B.ASc. in Engineering Science, Electrical and Computer Option

Division of Engineering Science

University of Toronto

April 2015

Physical device-level simulations were conducted on next-generation n-type metal-oxide-semiconductor

field-effect transistors (MOSFET) and tunneling field-effect transistors (TFET). A 2D, double-gated

model of an n-type MOSFET was created and the DC and AC performance was investigated for channel

lengths from 28 nm to 2 nm. Scaling results demonstrated improved high frequency characteristics with

a tradeoff of increased leakage power. To address the issue of leakage power, TFETs were investigated as

an alternative electronic device structure. A 2D InGaAs-AlGaAs heterostructure TFET was developed

and characterized for DC performance. The TFET performance did not indicate improved subthreshold

slope, indicating further refinement of doping profiles and bandgap structure may be required.

ii

Acknowledgements

This work would not have be complete without the help of a number of very smart and passionate

people in the Voinigescu group. Of course, I am extremely grateful to Professor Sorin Voinigescu for his

guidance, prompt feedback, and for keeping me on track throughout this project. To James Bateman,

for his endless patience, stream of suggestions and tips, and helpful advice. Yuxi Liu, for sharing his

progress with me as we both worked on our respective thesis projects. Jaro and Tim for troubleshooting

my computer problems. The rest of the lab, for dealing with me and my silliness in good humour. And

last but not least, all my friends and family for their continued support.

Thank you.

iii

Contents

1 Introduction 1

2 Background and Theory 3

2.1 Modern Semiconductor Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2 Transistor Figures of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3 Metal-Oxide-Semiconductor Transistor Scaling . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3.1 Threshold voltage roll-off in the linear region . . . . . . . . . . . . . . . . . . . . . 5

2.3.2 Drain-induced barrier lowering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3.3 Bulk punch-through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4 Tunneling Field-Effect Transistor Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.5 Semiconducting Materials and Heterostructure Properties . . . . . . . . . . . . . . . . . . 10

2.6 Doping Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Literature Review 13

3.1 Alternative Semiconductor Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Tunneling Field Effect Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.1 Material Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.2 Device Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Band to Band Tunneling Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.1 Zener Tunneling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.2 Schenk Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.3 Hurkx Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4 Tunneling Field-Effect Transistor Design Considerations . . . . . . . . . . . . . . . . . . . 17

3.5 Summary and Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

iv

4 Methods 19

4.1 Research Objectives and Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2 Simulator Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 Determining Device Size and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4 Experimental Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5 Results and Discussion 22

5.1 Initial NMOS Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 Scaled NMOS Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2.1 N-type MOS Device Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.2.2 Effect of Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2.3 Extension to 3D-Nanowire Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3 Tunneling Field-Effect Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.1 Band Gap Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.3.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6 Conclusion 34

6.1 Summary of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Bibliography 36

Appendices 38

A NMOS Scaling: SDE Deck 39

B NMOS Scaling: Sentaurus Device Deck 43

C 3D Nanowire: SDE Deck 47

D 2D TFET: Sentaurus Device Deck 51

v

List of Tables

2.1 Common figures of merit (FOM) used in transistor design and their descriptions . . . . . 4

2.2 Material Properties of Common Semiconductor Materials from [18], [16], and [13] . . . . . 10

5.1 Dimensions and parameters of scaled n-type MOSFET devices . . . . . . . . . . . . . . . 25

vi

List of Figures

2.1 Intel’s 22nm FinFET Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2 Energy band diagrams showing the semiconductor from source to drain for the ON (solid

line) and OFF (dashed line) of A. a long-channel NMOS device, and B. a short-channel

NMOS device showing the DIBL effect [16]. . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 Punchthrough is shown when increasing the drain voltage increases the drain leakage

current for Vg = -0.6 V. The dependence of current on Vd and shift in threshold voltage

indicate short-channel effects. [16]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4 A. Zener tunneling in a p-n junction, and B. Triangular potential barrier seen by tunneling

electrons [15]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.5 Energy band diagrams for an n-type TFET for A. 0.1 Bias Zener Tunneling, B. Depletion

Mode Device in OFF State, and C. Depletion Mode Device in ON State [15]. . . . . . . . 9

2.6 Energy band diagram of A. two isolated semiconductors of different materials. B. An

ideal p-n heterojunction at thermal equilibrium [16]. . . . . . . . . . . . . . . . . . . . . . 11

3.1 Various n-type TFET structures. A. a single-gate lateral TFET; B. A double-gated ver-

tical TFET; C. A single-gate lateral TFET with a n+ pocket under the gate; D. A

double-gated lateral TFET with an n+ pocket under the gate [15]. . . . . . . . . . . . . . 15

3.2 A. Schematic of a gate-all-around architecture of an InAs-Si heterostructure nanowire

TFET. B. A scanning electron micrograph showing a cross-section of the TFET [8]. . . . 15

3.3 Band-to-band tunneling current for a reverse-biased pn junction comparing a heterojunc-

tion performance vs a homojunction. The heterojunction shows higher tunneling current. 17

3.4 Degenerately doped semiconductors may begin tunneling prematurely, thus causing cur-

rent to flow through the device before it is fully turned on. . . . . . . . . . . . . . . . . . 18

5.1 Initial 14nm device structure, axes plotted on X-axis and Y-axis, scale in micrometers . . 22

vii

5.2 Transfer Characteristics of NMOS device for Vds = 0.05 V, 0.1 V, and 1.0 V. Gate Voltage

in [V]. Drain current in [A/um]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3 Output Characteristics of NMOS device for Vgs = 0.5 V, 1 V, and 1.05 V. Drain Voltage

in [V]. Drain current in [A/um]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.4 Transconductance plot of NMOS device at varying voltages. . . . . . . . . . . . . . . . . . 24

5.5 Scaled n-type MOSFETs from 28 nm to 2 nm. The colouring represents doping profile

and concentration, with red indicating n-type doping and dark blue indicating p-type doping 26

5.6 Comparison of Transfer Characteristics: Drain Current vs Gate Voltage for NMOS Device

Scaling from 28nm to 2nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.7 Comparison of Output Characteristics: Drain Current vs Drain Voltage for NMOS Devices

Scaling from 28nm to 2nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.8 Comparison of Transconductance: gm vs Voltage and gm vs Drain Current for NMOS

Devices Scaling from 28nm to 2nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.9 Comparison of Cutoff Frequency: Ft (Unit Gain Method) vs Gate Voltage for NMOS

Devices Scaling from 28nm to 2nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.10 Comparison of Cutoff Frequency: Ft vs Drain Current for NMOS Devices Scaling from

28nm to 2nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.11 3D NMOS reference design using all-around gate silicon nanowire structure. . . . . . . . . 30

5.12 Device structure for tunneling Field-Effect Transistor. Colours represent the doping con-

centration, and contacts are from right to left: source, gate, drain . . . . . . . . . . . . . . 30

5.13 Lengthwise energy band diagrams for the initial TFET design in the OFF and ON state. 31

5.14 Transfer characteristics at two drain voltage bias points of the initial TFET structure.

The gate voltage was simulated to 0.5 V and 1 V, respectively. . . . . . . . . . . . . . . . 32

5.15 Output characteristics at two drain voltage bias points of the initial TFET structure.

The gate voltage was simulated to 0.5 V for the green curve and 1 V for the red curve,

respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

viii

Chapter 1

Introduction

Historically, growth in the semiconductor industry has been driven by Moore’s Law, which states that

the size of a transistor must shrink by approximately 50% every two years. Traditionally this has resulted

in improved device speed and reduced power; however the benefits of reducing the gate length of com-

plementary metal-oxide-semiconductor (CMOS) devices below 14 nm are hampered by increased leakage

current and reduced supply voltage scaling [8]. As meeting the predictions of Moores Law becomes more

difficult, researchers have turned to various other possible device structures that may prove to be more

power efficient and have improved I-V characteristics. One such novel device is the tunneling field effect

transistor (TFET), which promises a number of advantages for low power applications: extremely low

leakage current, and steep subthreshold slope below the 60mV/dec thermionic limit [4]. In addition,

TFETs can be fabricated using the same fabrication techniques used for state-of-the-art silicon CMOS

technology [10]. The TFETs extremely low OFF currents and low operating voltages could potentially

facilitate low-power circuit designs and chips, and provide significant benefit in the field of electronic

nanodevices.

The TFET principle of operation differs from that of traditional CMOS field effect transistors by

using the Zener tunneling mechanism as opposed to thermionic emission to transport carriers. Using

this mechanism, the on current, Ion, of the device is dependent on the transmission probability, TWKB,

which can be estimated using the Wentzel-Kramer-Brillouin (WKB) approximation as:

TWKB ≈ exp(−4λ√

2m∗√

(Eg)3

3qh(Eg + ∆φ))[8] (1.1)

The screening tunneling length, λ, thus is related to the on current, and can be controlled by varying

the gate voltage Vg of the device.

1

Chapter 1. Introduction 2

The main goal of this project is twofold: first to characterize, using device simulation, the extreme

scaling properties of an NMOS device from 28 nm to 2 nm, and simulate the DC and AC characteristics

of the device. It is expected that the device will perform with improved high frequency characteristics

at lower gate lengths, though this may come with a tradeoff of increased subthreshold slope and con-

sequently greater power consumption. To address the issue of leakage power in MOSFET devices, the

TFET explored as a potential alternative. The behaviour of a two-dimensional TFET device with gate

length comparable to that of MOSFETs in the next technology node (14 nm) will be investigated to

evaluate whether this device could prove superior to traditional CMOS technology in terms of perfor-

mance and power consumption. The hypothesis is that the tunnel FET will have significantly steeper

subthreshold slope and reduced leakage current, but with a trade-off of lower ON currents and reduced

efficiency for high speed switching applications. Heterojunction materials will be selected to optimize

the TFET structure and performance. If time allows, the TFET performance can also be optimized by

adjusting the structure, materials, doping profile, and scaling.

Though the n-type MOSFET remains an important device at small scales, TFETs prove promising

for low-power applications because they are the only ones that can have steeper subthreshold slope as

needed to reduce the supply voltage in ICs. The TFETs extremely low OFF currents and low operating

voltages could potentially facilitate low-power circuit designs and chips, and provide significant benefit

in the field of electronic nanodevices.

Chapter 2

Background and Theory

2.1 Modern Semiconductor Devices

Among the major players in the semiconductor industry such as Intel and TSMC, Moore’s Law has

continued for the past few years despite poor planar MOSFET performance. This has been achieved

through the implementation of a variety of innovations including incorporating strain into the channel,

using a high-k dielectric, and using a three-dimensional transistor structure such as a trigate or finFET

structure. These changes allow these companies to improve performance by incorporating incremental

improvements in fabrication methodology. However, the International Technology Roadmap for Semi-

conductors predicts that CMOS devices will still reach fundamental limits in scaling around 2018 that

must be overcome [2].

(a) 3D model of Intel’s 22nmtrigate technology. Conductingchannels are formed on three sidesof a vertical fin structure, provid-ing fully depleted operation.

(b) SEM of Intel’s physically im-plemented 22 nm trigate struc-tures. Finning is completed byconnecting multiple drains andsources under a single gate [9].

Figure 2.1: Intel’s 22nm FinFET Transistors

3

Chapter 2. Background and Theory 4

2.2 Transistor Figures of Merit

Table 2.1: Common figures of merit (FOM) used in transistor design and their descriptions

Figure of Merit Symbol Definition

On Current, orID,Sat

Ion The current at the drain when the device is in saturationmode.

Off Current, orID,Cutoff

Ioff The current at the drain when the device is in cutoff mode.

Threshold Volt-age

VT The minimum gate-to-source voltage needed to create con-duction between the source and drain of the device.

SubthresholdSlope

SS Specific to MOSFETs, the SS describes the slope of thelogarithmic plot of drain current vs. gate voltage in theregion below the threshold. This provides an indication ofthe power lost during device switching.

RF/High Speed Analog Design

Transconductance gm Transconductance describes how output current varies withrespect to input voltage, with gm = ∆Iout/∆Vin

Cutoff Fre-quency

FT The cutoff frequency is defined as the frequency where thecurrent gain drops to 0dB, and can be defined as: 2πFT =gm/Cgs where Cgs is the gate-to-source capacitance.

MaximumOscillationFrequency

Fmax The maximum oscillation frequency describes the frequencywhen power gain drops to 0dB.

Power Design

Figure of Merit rds(on) ×Qg A quick measure for power performance and efficiency, theFOM takes into account both conduction losses and switch-ing losses in a power MOSFET design [6]. Here, Qg is thequality factor of the system, or the ratio of power stored topower dissipated.

Digital Design

Gate Delay τgate The length of time for a signal (switch from on-off or off-on)to propagate through a device.

To provide an objective perspective and evaluation of electronic devices, Figures of Merit (FOM)

are commonly used metrics that describe device performance. Transistor performance parameters vary

depending on the purpose of the device, and other considerations such as size and cost of production

should also be included. For digital logic applications, the main considerations are a high on-off current

ratio (Ion/Ioff) and subthreshold slope to minimize switching power losses. Other metrics for RF and

Power applications are described in Table 2.1. Different transistors can be optimized for various purposes

and combined in a single circuit during the processing of a single System-on-Chip (SOC).


2.3 Metal-Oxide-Semiconductor Transistor Scaling

Scaling down the MOSFET is a continuous trend known as Moore’s Law. Smaller devices improve the

driving current, ID, therefore also improving operation performance and reducing area [16]. However,

for very small devices, the performance begins to deviate from so-called long-channel devices due to

short channel effects including [16]:

• Threshold voltage roll-off in the linear region

• Drain-induced barrier lowering (DIBL)

• Bulk punch-through

2.3.1 Threshold voltage roll-off in the linear region

When the source and drain depletion regions become a significant portion of channel length, it is possible

that the voltage applied across the drain and source of an NMOS device can modulate the threshold

voltage of the device instead of staying roughly constant. This can be modeled by the following equation:

∆VT = −qNAWmrjCoL

(

√1 +

2Wm

rj− 1) (2.1)

where Wm is the depletion width, rj is the junction depth, L is the channel length, and Co is the gate

oxide capacitance. Thus at larger drain voltages the voltage at the gate required to turn on the device

is decreased for an n-type MOSFET.

2.3.2 Drain-induced barrier lowering

Drain-induced barrier lowering occurs when the drain is located close to the source, and the drain bias

can influence the energy barrier height at the source end. This can cause an increase of current for

short-channel devices, and again the threshold voltage would be expected to decrease with increasing

drain bias [16].


Figure 2.2: Energy band diagrams showing the semiconductor from source to drain for the ON (solidline) and OFF (dashed line) of A. a long-channel NMOS device, and B. a short-channel NMOS deviceshowing the DIBL effect [16].

2.3.3 Bulk punch-through

For a sufficiently large drain voltage, significant leakage current may begin to flow from drain to source

from the bulk of the substrate, and the depletion-layer width of the drain can also increase with increased

drain voltage.

Figure 2.3: Punchthrough is shown when increasing the drain voltage increases the drain leakage currentfor Vg = -0.6 V. The dependence of current on Vd and shift in threshold voltage indicate short-channeleffects. [16].


2.4 Tunneling Field-Effect Transistor Theory

Figure 2.4: A. Zener tunneling in a p-n junction, and B. Triangular potential barrier seen by tunnelingelectrons [15].

The TFET principle of operation differs from that of traditional CMOS field effect transistors by using

the Zener (aka band-to-band) tunneling mechanism as opposed to thermionic injection as the primary

mechanism of transporting charge carriers. In the simplest case, a quantum tunneling treatment can be

used to solve for a finite well potential (picture of quantum well tunneling). For a tunneling field-effect

transistor, the potential barrier across the gate can be approximated as a triangular potential, as shown

in figure 2.4.

The expression for a particle tunneling through this potential barrier can be found by solving

Schrodingers equation for a triangular barrier, and the time-dependent Schrodingers equation is equal

to:

ihd

dt

(Ψ(r, t)

)= [−h2

2µ∇2 + V (r, t)]Ψ(r, t) (2.2)

Here is the particles reduced mass, V is the potential energy, ∇2 is the Laplacian, and Ψ is the wave-

function. Solving this expression for Ψ will provide enough information to approximate the probability

of tunneling current flowing through the device, leading to a band-to-band tunneling current that drives

the tunneling FET design. In the case of the triangular tunneling barrier shown in Figure 2, V(r,t) is


defined as:

V (r, t) =

−qxξ + Eg, if 0 < x < d

0, otherwise

(2.3)

The general solution for Schrodingers equation in one dimension is then:

Ψ(x) =

A1e

ik0x +A2e−ik0x if x ≤ 0

B1eik1x +B2e

−ik1x if 0 < x < d

C1eik2x + C2e

−ik2x if x ≥ d

(2.4)

The full solutions can be found by solving with boundary conditions. However, we realize that the

functions wave number, k, is defined as:

k(x) =

√2m∗g

h2 (Ex − V (x)) (2.5)

Using the Wentzel-Kramer-Brillouin (WKB) approximation, below, the tunneling probability can then

be approximated:

TWKB ≈ exp−2

∫ d

0

|k(x)|dx (2.6)

This transmission probability describes how likely it is for a particle to tunnel through the potential

barrier of the device, and must be between 0 and 1. The final tunneling probability can then be

calculated for the triangular potential well:

TWKB ≈ exp−4√

2m∗gE32g

3qhξexp−E⊥E

(2.7)

Here, E = qhξ

2√

2m∗gEg

is a factor that determines the impact of the transverse-energy-state carriers on

the tunneling magnitude [15]. By varying the gate voltage, VG, of the device, it is possible to tune the

tunneling probability, which contributes to the current flowing through the device. Finally, the Zener

tunneling current density is calculated by integrating charge flux tunneling probability from the p+

side to the n+ side:

J =

∫qvg(k)ρ(k)ρ⊥(k⊥)dk2π × k⊥dk⊥ × (fv − fc)TWKB (2.8)

The tunneling probability therefore depends on the size of the bandgap as well as the effective mass of

the device. The energy band diagrams for an nTFET depletion-mode device looks as follows:


Figure 2.5: Energy band diagrams for an n-type TFET for A. 0.1 Bias Zener Tunneling, B. DepletionMode Device in OFF State, and C. Depletion Mode Device in ON State [15].

The bandgap size can be modulated by applying a voltage across the gate of the TFET, and the

effective mass can be controlled using the relationship:

m∗ =1d2Edk2

(2.9)

Changing the effective mass would therefore involve making modifications in the material structure of the

TFET device (eg. doping, different substrate materials), while changing the size of the bandgap can be

tuned by biasing the gate voltage of the TFET. In contrast to MOSFETs, tunneling FETs are ambipolar

for the above device, it would show p-type behaviour for dominant hole conduction and n-type behaviour

for dominant electron conduction. To compensate for this, it is possible to design an asymmetric doping

profile (heavier hole-dominant doping) or using heterostructures to restrict the movement of one type

of charge carrier [8]. This asymmetry also produces the major advantage of TFETs: a low leakage

(off-state) current. When the TFET is in the off state, the tunneling barrier is very high, so holes and

electrons are extremely unlikely to tunnel through a barrier. However, modulating the applied gate

voltage of the device will lower the barrier of the device, forcing it into an ON state with a passable

barrier for current to flow.


2.5 Semiconducting Materials and Heterostructure Properties

Semiconductor materials are nominally small band gap insulators. Silicon is by far the most common

material still because of its maturity in the market, its well-defined manufacturing processes for large-

scale integrated circuits, as well as its abundance of supply. Other common compound semiconductors

used in electronics include GaAs and SiGe.

For device design, engineering the bandgaps between different parts of a device can often lead to

improved performance. This can be done by implementing a heterostructure junction in some devices,

where different materials are used in the different parts of the device based on the desired bandgap[16].

III-V materials, containing a compound of materials from Group III and Group V of the Periodic Table

of Elements, are very popular for this case. III-V materials allow the ability to tune the bandgap of

the material based on the proportions of the III-V materials contained in each compound. A chart

comparing a representative sample of relevant material properties is supplied below. In particular, the

AlxGa1−xAs and InxGa1−xAs families were investigated for this project.

Table 2.2: Material Properties of Common Semiconductor Materials from [18], [16], and [13]

ElectronAffinity

mlh/m0 me/m0 Lattice Con-stant

Eg (eV) Electron Mo-bility (µ)

Si 4.05 eV 0.16 0.2 5.431Angstroms

1.242 eV 1360cm2V −1s−1

Ge 4.0 eV 0.044 0.041 5.658Angstroms

0.66 eV 3900cm2V −1s−1

Al0Ga1As 1.42eV 0.082 0.067 5.6533Angstromsat 300K

N/A N/A

Al1Ga0As 2.17eV N/A N/A 5.6605Angstromsat 300K

N/A N/A

Al0.5Ga0.5

As0.3Sb0.7

3.6 eV 0.11 0.09 5.98Angstroms

1.36 N/A

In0.8Ga0.2As 4.73 eV 0.034 0.036 5.98Angstromsat 300K

0.50 N/A

In0.53Ga0.47As 0.75 eV 0.051 0.041 5.869Angstromsat 295K

0.50 10,000cm2V −1s−1

These parameters are important to the performance of the semiconductor to align the bandgap of

the respective materials at a junction. As shown in the figure below, bandgap alignment is dependent

on both the electron affinity and the size of the bandgap of the material. The material lattice constants

must also be considered to include the effects of lattice strain at a heterojunction. For the purposes of


this project, strain was not investigated, so lattice-matched materials were picked and only the bandgap

modified.

Figure 2.6: Energy band diagram of A. two isolated semiconductors of different materials. B. An idealp-n heterojunction at thermal equilibrium [16].


2.6 Doping Implantation

The defining property of a semiconductor material is that it can be doped with impurities that alter its

electronic properties in a controllable way, by shifting the location of the bandgaps with respect to the

Fermi energy levels of a device.

The Maxwell Boltzmann approximation is typically used, and is applicable for non-degenerate semi-

conductors in the limit of high temperature and low particle density, or when the following condition is

satisfied:

e(εmin−µ)/kT � 1 (2.10)

Here, εmin is the lowest (minimum) value of εi.

In this case, the approximation that is used to estimate the Fermi energy level can be approximated

as:

n = ni expEf − EikT

[16] (2.11)

p = ni expEi − EfkT

[16] (2.12)

For very highly doped semiconductors less than 3kT above Ev or less than 3kT below Ec, the

Maxwell-Boltzmann approximations no longer apply and there is no easy analytical solution for the

electron materials. Instead, the Fermi-Dirac equations must be solved analytically.

n =

∫ Etop

0

N(E)F (E)dE (2.13)

where N(E) is the density of states, and F(E) is the Fermi-Dirac equation as outlined below:

F (E) =1

1 + e(E−EF )/kT(2.14)

Chapter 3

Literature Review

3.1 Alternative Semiconductor Devices

Various structures and devices have been proposed as potential future devices beyond CMOS. The

single-electron transistor (SET) has been proposed as a potential logic element device that is small

in size and has low power consumption. This device consists of two tunnel junctions that share a

common electrode, thus the electrons may only use tunneling as a mechanism to transport electric

current [11]. Carbon nanotube field-effect transistors (CNFETs) have also been suggested as a device

that utilizes the high conductivity of 2-dimensional carbon to transmit electrons. Though graphene is

inherently conducting, modifying the chirality of carbon nanotubes can control the material to behave

like a semiconductor [19]. Junctionless nanowire field-effect transistors (JNTs) have also been considered

as an alternative that provides a nearly ideal subthreshold slope and good on-state current [6]. On a

grander scale, it is also possible to develop devices that use state variables other than solely electric charge

to transfer information, for example, electron spin, phase, and molecular states [2]. Tunneling field-effect

transistors are a promising alternative because of their ability to have a steep threshold voltage below the

fundamental limit of 60 mV/dec for MOSFETs and BJTs [15]. This reduces power consumption because

supply voltages can consequently be scaled to less than 0.5 V. Another key advantage to TFETs is their

low source-drain leakage, which poses significant advantages in reducing current when transistors are

in the off state. These potential advantages would theoretically allow TFETs to achieve lower standby

power and also allow less power to be lost during the switching of the circuit compared to traditional

MOSFET devices. In todays mobile-centric world, power represents an increasing concern in circuits

and tunneling field-effect transistors provide an opportunity to reduce power consumption by up to 100

13

Chapter 3. Literature Review 14

times on a fundamental level [8].

3.2 Tunneling Field Effect Transistors

A number of different designs for TFETs have been proposed in literature, which differ in bandgap selec-

tion, oxide/dielectric selection, device structure, and other design parameters. Below I have attempted

to overview a few possibilities to illustrate the breadth of options.

3.2.1 Material Selection

Various materials have been utilized in the gate, source, and dielectric of electronic devices. Examples of

recent improvements to devices include the use of III-V heterojunction materials such as GaAs, as well

as SiGe. High-K dielectrics with metal gates are now also often used to reduce the thickness of the gate

dielectric [19]. Asbeck et. Al describe a TFET developed using III-V based tunnel heterojunctions that

may operate as low as 0.3 V, with an Ion/Ioff ratio of 8. The proposed TFET allows for a good balance

between power consumption and performance, however, the III-V semiconductor design may prove more

difficult to fabricate compared to traditional CMOS processes due to the use of more exotic material

combinations, such as InAlAs and InGaAs [18]. 2-dimensional materials have also been suggested as

a possible method of reducing the dimensions of the device. The high conductivity of 2-dimensional

carbon has been attractive for its higher current throughput, though currently manufacturability of

graphene devices has proved challenging [5]. Lundstrom et. al discuss simulations that were undertaken

to explore how carbon nanotubes be optimized for TFET performance [12]. However, one issue with

carbon nanotubes is their fabrication difficulty, as it is difficult to accurately grow carbon nanotubes in

a regular pattern. Furthermore, simulations do not account for the real performance of the material, as

defects in the nanotube structure could dramatically decrease current throughput.

3.2.2 Device Structure

A number of different designs for tunnel FETs have been proposed in literature that range in feasibility,

change from previous designs, and performance. Traditional single-gated structures are simple to man-

ufacture, however, TFET designs using a planar TFET do not appear to have appreciable on-current

characteristics above 10-17 A/m [3]. Double-gate tunnel FETs are another possibility that provides more

current than their single-gate counterparts, with an Ion/Ioff ratio of more than 21011 and on current up

to 0.23mA [1]. The design mentioned in this paper, however, does not investigate the scaling impact of


TFETs, since the design was built at a 50nm gate length. Other structures that have been developed

incorporate modified doping profiles and vertical finFET structures, as shown in the figure below:

Figure 3.1: Various n-type TFET structures. A. a single-gate lateral TFET; B. A double-gated verticalTFET; C. A single-gate lateral TFET with a n+ pocket under the gate; D. A double-gated lateral TFETwith an n+ pocket under the gate [15].

Other novel structures that have been explored include those that further increase the gate surface

area, for example a gate-all-around architecture, which can be seen in a silicon nanowire FET [8]. These

structures have been combined with an InAs-Si heterostructure and prove promising in reducing device

area.

Figure 3.2: A. Schematic of a gate-all-around architecture of an InAs-Si heterostructure nanowire TFET.B. A scanning electron micrograph showing a cross-section of the TFET [8].


3.3 Band to Band Tunneling Model

The original Band to Band Tunneling Model discussed in use during the tunneling transistor simulations

in this thesis project make use of the Zener tunneling mechanism. The follow subsections will discuss

briefly the Zener model, as well as some of the updated models used during the course of this experiment.

3.3.1 Zener Tunneling

Zener tunneling is considered a form of dielectric breakdown, which occurs when the number of electrons

in an unfilled band suddenly increses as the field strength passses a critical value. Using the Bloch model,

it is possible to calculate the rate at which electrons escape from the lower into the upper energy bands

via Zener tunneling, with the main result for a one-potential barrier being [20]:

γ =eFa

hexp (−π

2maε2

h2|eF |) (3.1)

where γ represents the rate at which an electron can pass from one region to another side of the potential

barrier into the conduction band of a dielectric. To actually implement the Zener tunneling model in

simulation, however, requires some more modern simulation models described below.

3.3.2 Schenk Model

The Schenk Model proposes that band-to-band tunneling under conditions set by Zener do not reach the

same currents observed in experimental results. This indicates that some mechanism such as phonon-

assisted band-to-band tunneling occurs in steep p-n junctions (with doping greater than 1 × 10e19 cm19),

or in high normal electric fields. Green’s function formalism is used to analyze electron-phonon collisions

that propagate electrons that initially tunnel via band-to-band tunneling [14].

3.3.3 Hurkx Model

The Hurkx model for band-to-band tunneling is modelled by an additional generation-recombination

process, therefore including both trap-assisted tunneling as well as band-to-band tunneling [7]. Trap

assisted tunneling is an important point to consider, as impurities in semiconductor devices will allow

electrons to tunnel through a junction even if the valence band is not located below the conduction band

of the other portion of the junction. For the purposes of the simulations conducted through this project,

the Hurkx model was used due to its ability to converge on a solution as well as its increased accuracy

over simple Zener band-to-band tunneling.


3.4 Tunneling Field-Effect Transistor Design Considerations

A number of key aspects are considered when choosing the materials, structure, and doping profile of a

tunnel-FET design. Based on reference designs, III-V semiconductor systems seem to provide superior

performance [18]. In particular, the InGaAs/AlGaAsSb system appears promising because of a wide

range of band lineup configurations that can be provided, the ability to vary band lineup over a wide

energy range by tuning material composition, as well as easy lattice matching due to the tunability of

the system. By choosing different proportions of group III and group V materials, properties can be

engineered to desired bandgaps.

Another consideration is the use of a staggered heterojunction as opposed to a homojunction of

uniform material in the source, drain, and channel.

[18]

Figure 3.3: Band-to-band tunneling current for a reverse-biased pn junction comparing a heterojunctionperformance vs a homojunction. The heterojunction shows higher tunneling current.

Staggering materials in a heterojunction, though much more difficult to fabricate, offers up to a 100x

enhancement in tunneling current, as shown in figure 3.3.


[17]

Figure 3.4: Degenerately doped semiconductors may begin tunneling prematurely, thus causing currentto flow through the device before it is fully turned on.

Lastly, the doping profile to achieve a steep subthreshold slope is important. For MOSFETs, source

regions are usually heavily doped, however, for TFETs this may not be ideal due to the tail of electrons

that lie above the Fermi energy. These electrons may be able to tunnel through a TFET prior to

the device being fully switched on, resulting in a more shallow slope as shown in Figure 3.4. It is

recommended to reduce source doping somewhat to mitigate this effect.

3.5 Summary and Remarks

Overall, though numerous designs of tunneling field-effect transistors have been proposed, these devices

have not reached the same level of scaling and performance that would enable future electronic TFETs

to be fully functional and available to build on current silicon fabrication technology. Further research

can be conducted to investigate the impact of scaling to the 10 nm node. It is yet unclear whether or

not the ON current of the device will be sufficient to drive current, so enabling a high on current is

desirable.

Chapter 4

Methods

4.1 Research Objectives and Methodology

For the purpose of this project, a 2 dimensional double-gate NMOS structure was first implemented

in Sentaurus to understand the impact of structure on device physics and properties. A double-gated

structure was chosen to increase the ON current of the device compared to single-gated structures [1], and

a two-dimensional structure was chosen to reduce simulation time. The DC transfer characteristics and

output characteristics were plotted to verify functionality. A silicon wire 3D model was also developed,

demonstrating feasibility of 3D simulations for a nanowire or gate-all-around structure. For the purposes

of this thesis, the 2D structure was used to reduce simulation time.

Scaling was investigated on the device by simulating a series of similar n-type MOSFETs with gate

lengths ranging from 28nm to 2nm and scaling other parameters appropriately. Parameters including ft

vs. Id, ft. vs. Vds, gm vs Id, and gm vs. Vds were simulated to gather figures of merit for the device.

The high frequency characteristics of the devices were expected to improve as gate length scaled down,

while other aspects such as leakage current were expected to degrade depending on gate length.

Following this study on scaling, another intermediate structure using InGaAs in the channel instead

of silicon was developed so as to understand how the different material would impact the performance

of the n-type MOSFET. The simulations of this material was compared to the performance of a silicon-

based device to ensure that the impact of switching to a III-V compound would not greatly impact

device performance.

Then, the doping profile of the InGaAs device was modified to match that of a TFET, and a 2-

dimensional TFET heterostructure was developed using InGaAs and AlGaAs. III-V compounds were

19

Chapter 4. Methods 20

used for the TFET to ensure better performance through improving the bandgap structure [18]. Some

iterations and optimization were required in this process to understand the effect of varying the doping

profiles, the structure size, as well as the material composition. The bandgap structure of the device as

well as preliminary transfer characteristics that show tunneling behaviour are included to demonstrate

basic functionaly of the TFET.

4.2 Simulator Setup

In order to model the behaviour of a semiconductor device, software packages exist to conduct sim-

ulations with various levels of physics integrity, ranging from compact SPICE models for small-scale

integrated circuits to individual atomic-scale physics-driven simulators such as Atomistix. Ideally the

device simulator should capture the tunneling behaviour of TFETs as well as provide accurate simula-

tions of DC, small signal, and large-signal operation of the device. A number of simulation tools are

available at the desired level for this project, including quantum effects and band energy-diagram-driven

diagrams.

Synopsys offers a device modeling package called Sentaurus Device, which offers the ability to define

a device structure from both process simulation steps (SPROCESS) and through manually defined struc-

tures (using Sentaurus Structure Editor). These packages were readily available within the university

software and thus did not require additional funds to acquire. In addition, a number of prior TCAD

models and sample libraries are readily available on Sentaurus to provide examples on how to set up

projects, therefore it was the most accessible choice for this project. In addition, it is possible to enable

all necessary physics models in the software, from classical electronic models to Fermi-Dirac electronic

equations and quantum tunneling effects.

4.3 Determining Device Size and Parameters

A number of different approaches could be taken in defining the device structure. Either a more complex

3D model could be used, or a simpler model that would be easy to build and understand the device

physics. For simplicity’s sake, an initial 2D model was developed in silicon that consisted of a 10nm long

gate with a lateral doping profile, of 4 nm in thickness. A 10nm-long double gate was implemented to

increase the on current of the device, which has been shown to improve performance over a single-gated

device [1]. A 2nm thick high-k dielectric of HfO2 was used for the dielectric, with 20 nm spacers initially

placed on either side of the gate. No contact resistance was modelled. The doping profile for the NMOS

Chapter 4. Methods 21

device consisted of a 5 × 1020atoms/cm3 arsenic concentration. The channel region was lightly doped

with 1× 1020atoms/cm3 of boron.

When scaling the device to smaller gate lengths, the device was scaled such that the source, channel,

drain, and oxide lengths all remained proportional in length. Compared to the initial device, the doping

profile was made much more abrupt. The oxide material was varied as well: for the 28 nm device SiO2

was used, and Si3N4 was used for the 20nm and 14nm devices. Below 14nm, all devices had a high-K

dielectric, HfO2.

For the tunneling field-effect transistor a device was implemented with the original gate length set

to 20nm. The device had a channel and drain of InGaAs and a source of AlGaAs. InGaAs was selected

for the channel and drain for its high electron mobility properties greater than 10,000 cm2V −1s−1. To

ensure a proper heterojunction between the channel and source, AlGaAs was used as a material with

similar lattice parameters and a valence band level that matched the valence band edge of InGaAs.

A representative Sentaurus Device Editor (SDE) deck is provided in Appendix A. The AC/DC device

simulation deck can be found in Appendix B.

4.4 Experimental Outline

The experiments and major results obtained from each device structure included the following:

• Initial n-type MOSFET: Transfer characteristics, output characteristics, and transconductance

information was gathered at 3 bias points. It was found the initial length of the spacers was

somewhat limiting, so the size of the spacer and source/drain also impacted the results. The next

iteration of the device thus reduced the size of the spacer.

• Scaled n-type MOSFET: The devices were characterized for both their DC characteristics (transfer

characteristics and output characteristics) as well as their AC characteristics (Cutoff frequency and

transconductance), which were plotted both against Vg and Id.

• InGaAs TFET: A preliminary transfer plot and energy band diagrams were plotted to verify basic

tunneling capability.

Chapter 5

Results and Discussion

5.1 Initial NMOS Structure

The initial device structure had the following shape and doping profile.

(a) Initial NMOS Device Structure with high-K gate di-electric and long spacer.

(b) Device doping concentration, showing a gradient intransition from p-type to n-type doing region.

Figure 5.1: Initial 14nm device structure, axes plotted on X-axis and Y-axis, scale in micrometers

Initial trials were conducted to gather the DC transfer characteristics at Vds = 0.05 V, 0.1 V, and

1.0V, as well as the output characteristics at Vgs=0.5V, 1V, and 1.2 V from the NMOS reference

design, and the resulting I-V curves are shown in Fig. 9 and 10 below. DC results from the transfer

characteristics indicate a Id,lin of approximately 0.3 mA/um with SSlin of around 66 mV/dec, and Id,sat

of around 1mA/um with an SSsat of about 67 mV/dec. These are roughly in agreement with current

22

Chapter 5. Results and Discussion 23

semiconductor technology.

Figure 5.2: Transfer Characteristics of NMOS device for Vds = 0.05 V, 0.1 V, and 1.0 V. Gate Voltagein [V]. Drain current in [A/um].

Figure 5.3: Output Characteristics of NMOS device for Vgs = 0.5 V, 1 V, and 1.05 V. Drain Voltage in[V]. Drain current in [A/um].

The output characteristics indicate an increasing trend of greater drain-to-source current for pro-


gressively higher gate voltage, as expected. The body was not biased for this device, explaining the

difference in threshold voltages.

Figure 5.4: Transconductance plot of NMOS device at varying voltages.

These results show a measured gm,lin of 1.08mS/um at Vg = 0.52V and gm,sat of 1.7 mS/um at

Vg = 0.64 V. Some explanation for the gm performance could be due to the large size of the spacers

in the device, which could cause high source-to-drain resistance. The overall data gather so far verifies

the NMOS model developed, and provides a control reference to compare with the tunneling FET

performance.

5.2 Scaled NMOS Structure

5.2.1 N-type MOS Device Structure

The n-type MOSFET structure was refined with a more abrupt doping profile, and this device was then

scaled to smaller sizes from 28nm to 2nm.

The breakdown of device lengths and parameters is included in Table 5.1.


Table 5.1: Dimensions and parameters of scaled n-type MOSFET devices

StructureName

A B C D E F G

Gate Length(nm)

28 20 14 10 7 5 2

Tox (nm) 2 2 2 1.5 1.5 1 0.5Tchannel(nm)

7 6 5 4 2.5 2 1

Oxide Mate-rial

SiO2 Si3N4 Si3N4 HfO2 HfO2 HfO2 HfO2

Sourcelength (nm)

28 20 14 10 7 5 2

Source Ma-terial

Silicon Silicon Silicon Silicon Silicon Silicon Silicon

DrainLength(nm)

28 20 14 10 7 5 2

DrainMaterial Silicon Silicon Silicon Silicon Silicon Silicon SiliconSpacerLength(nm)

14 10 7 5 3.5 2.5 1

N source[cm3]-1

5.00E+20 5.00E+20 5.00E+20 5.00E+20 5.00E+20 5.00E+20 5.00E+20

N drain[cm3]-1

5.00E+20 5.00E+20 5.00E+20 5.00E+20 5.00E+20 5.00E+20 5.00E+20

N channel[cm3]-1

1.00E+15 1.00E+15 1.00E+15 1.00E+15 1.00E+15 1.00E+15 1.00E+15

GateBarrier -0.2 -0.2 -0.2 -0.2 -0.2 -0.2 -0.2

Bias Point 1 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6VVg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V

Bias Point 2 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0Vd = 0.3V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6VVg = 1.0V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V

Ft frequencyrange

1e10 - 1e12Hz

1e10 - 1e12Hz

1e10 - 1e12Hz

1e10 - 1e13Hz

1e10 - 1e13Hz

1e10 - 1e13Hz

1e10 - 1e13Hz


(a) Lg = 28nm (b) Lg = 20nm

(c) Lg = 14nm (d) Lg = 10nm (e) Lg = 7nm(f)Lg=5nm

(g)Lg=2nm

Figure 5.5: Scaled n-type MOSFETs from 28 nm to 2 nm. The colouring represents doping profile andconcentration, with red indicating n-type doping and dark blue indicating p-type doping

The resulting devices developed in Sentaurus Device Editor (SDE) are shown roughly to scale in

Figure 5.5. The colours indicate the doping type and concentration along the device. As can be seen,

the ratio between the source, channel, and drain, as well as the thickness of the channel and oxide

thickness were kept to scale during the scaling. The dielectric permittivity of the gate oxide was also

increased during the course of the scaling in order to demonstrate improved performance.

5.2.2 Effect of Scaling

The DC Characteristics of the device are plotted below, as indicated. Firstly the transfer characteristics

were plotted on a log scale with respect to gate voltage for two different drain bias points. The output

characteristics were also plotted to find the relationship between drain voltage and drain current.

(a) Transfer Characteristics, Vd biased to 0.3V (b) Transfer Characteristics, Vd biased to 0.6V

Figure 5.6: Comparison of Transfer Characteristics: Drain Current vs Gate Voltage for NMOS DeviceScaling from 28nm to 2nm


(a) Output Characteristics, Vg biased to 1V (b) Output Characteristics, Vg biased to 1.5V

Figure 5.7: Comparison of Output Characteristics: Drain Current vs Drain Voltage for NMOS DevicesScaling from 28nm to 2nm

Based on Figure 5.6 and 5.7, it can be seen that the general trend in drain current is to increase

with smaller-scaled transistors. For example, the ON current between Lg = 5nm and Lg = 2nm for

figure 5.7a is shown to improve from around 5 mA/width to 7 mA/width. This is a signficant increase

in performance by scaling to smaller gate lengths.

The subthreshold slope of the devices was found to range between 65 mV/dec for the Lg=2nm device

at Vd = 0.6V and 73 mV/dec for the Lg=28nm device at Vd = 0.3V. This indicates that subthreshold

slope does not change significantly for relatively low drain bias voltages that were used in this study.

Lastly, the off current (when Vg = 0 V) increased with smaller scales from 28nm to 20nm to 14nm,

however the off current can significantly be reduced at smaller scales by using a high-K dielectric, which

would reduce the gate-drain current significantly, as was used for small gate lengths.


(a) Transconductance, Vd biased to 0.3V (b) Tranconductance, Vd biased to 0.6V

(c) Transconductance vs Drain Current, Vd biased to0.3V

(d) Tranconductance vs Drain Current, Vd biased to0.6V

Figure 5.8: Comparison of Transconductance: gm vs Voltage and gm vs Drain Current for NMOSDevices Scaling from 28nm to 2nm

As shown in Figure 5.8, the scaling of smaller gate lengths show signficant improvements in transcon-

ductance over a relatively smaller range of gate voltage for the extremely scaled (Lg = 2nm) devices.

This is promising, though it remains to be further confirmed, since parasitics were not used in the device

simulations.


(a) Cutoff Frequency vs Vg, Vd biased to 0.3V (b) Cutoff Frequency vs Vg, Vd biased to 0.6V

Figure 5.9: Comparison of Cutoff Frequency: Ft (Unit Gain Method) vs Gate Voltage for NMOS DevicesScaling from 28nm to 2nm

(a) Cutoff Frequency vs Id, Vd biased to 0.3V (b) Cutoff Frequency vs Id, Vd biased to 0.6V

Figure 5.10: Comparison of Cutoff Frequency: Ft vs Drain Current for NMOS Devices Scaling from28nm to 2nm

Based on figure 5.10, it is seen that in addition to the improved transconductance, the cutoff frequency

of highly scaled devices is also improved. This indicates continued improvement of small devices in high

power applications, with a potential cutoff frequency of over 4000GHz for the 2nm device.


5.2.3 Extension to 3D-Nanowire Structure

To extend and further understand the performance of the device, a reference 3D model of a silicon-

nanowire device was developed in Sentaurus, with the full simulation device deck available in Appendix

C. The device was developed to match the structure of the 2D device in dimensions and doping profile,

and a mesh was defined in 3 dimensions. Simulations have not been conducted on this design yet due

to time and computing power constraints, and will become part of the future work.

(a) 3D view of silicon nanowire structure with gate oxide.(b) 3D side view of silicon nanowire without gate oxideto show doping profile

Figure 5.11: 3D NMOS reference design using all-around gate silicon nanowire structure.

5.3 Tunneling Field-Effect Transistor

Figure 5.12: Device structure for tunneling Field-Effect Transistor. Colours represent the doping con-centration, and contacts are from right to left: source, gate, drain

The design for the tunneling FET was done based off of the structure for the 2D NMOS device, with

modifications made to develop a heterojunction device and changes made to the doping profile. A

reference design for tunneling field-effect transistor based on a paper described by Wang et al [18] was


used, and a schematic of the final device is shown in the figure 5.12.

The device is slightly asymmetrical, with an abrupt doping profile between the source and the drain.

The source material was AlGaSb, and the channel and drain were made of InGaAs. The proportions

of the materials in the bandgap were tuned to have roughly aligned valence bands. The doping con-

centrations were as suggested in the reference design, with 2e19 atoms/cm3 boron doping in the source,

5e19 atoms/cm3 arsenic doping in the drain, and 5e15 atoms/cm3 arsenic doping in the channel. The

resulting device gate length was 30nm. The Hurkx model was used to model the band-to-band tunneling

through the device, with other physics defined in the TFET device deck, in Appendix D.

5.3.1 Band Gap Diagram

(a) Band diagrams while device is turned OFF (Vg =0), Vd = 0.05V

(b) Band diagrams while device is turned ON (Vg =0.5V), Vd = 0.05V. The valence band of the source isseen to be higher than the conduction band of the chan-nel, allowing for band-to-band-tunneling to occur.

Figure 5.13: Lengthwise energy band diagrams for the initial TFET design in the OFF and ON state.

The device bandgap diagram in the OFF and ON state are shown in Figure 5.13. It can be seen that

in the OFF state, the probability of band-to-band tunneling is extremely low in the device. In the ON

state, however, the conduction band of the gate lowers beneath the valence band of the source, allowing

for band-to-band tunneling to occur. This behaviour is expected and desired. However, it would be

desirable to have an even sharper tunneling barrier to allow for higher ON current.

Furthermore, the slight misalignment at the electron band gap could potentially cause a case where a

large number of electrons in the valence band of the source first tunnel through to the misaligned portion

of the band diagram, rather than tunneling into the conduction band of the channel region. This could


potentially smear the observed subthreshold slope.

5.3.2 DC Characteristics

Figure 5.14: Transfer characteristics at two drain voltage bias points of the initial TFET structure. Thegate voltage was simulated to 0.5 V and 1 V, respectively.

The transfer characteristics of the device were measured at two bias points to verify their tunneling

behaviour. These are plotted as shown in the figure 5.14. The subthreshold slope was measured to be

around 71 mV/dec for Vd = 0.1 curve between 0.45V ≤ Vg ≤ 0.55V. This is greater than the theoretical

thermionic limit of 60 mV/dec, as well as greater than the subthreshold slope of the initial n-type

MOSFET device of 67 mV/dec. The reasons for this large subthreshold slope could be due to imperfect

alignment of the bands in the heterojunction in the device, as well as non-ideal doping, which could

smear the subthreshold slope due to excess electrons above the electron Fermi level [18].

The output characteristics were also examined for 0 V ≤ Vd ≤ 0.6 V. Based on the plot, it appears

that the optimal drain voltage setting for maximized ON current would be around 30 mV. This is in line

with other papers on TFETs that indicate a low drain bias is required for the tunneling FET operation

[1].


Figure 5.15: Output characteristics at two drain voltage bias points of the initial TFET structure. Thegate voltage was simulated to 0.5 V for the green curve and 1 V for the red curve, respectively.

Chapter 6

Conclusion

6.1 Summary of Results

As the size of transistor gate lengths continues to shrink, a few major trends were demonstrated. It was

shown that as device gate length scaled, high frequency characteristics including gm and ft continued

to improve. However, at the same time the device threshold voltage and leakage current also increased,

indicating a source of increased power consumption. This may become unacceptable at the nanoscale

due to the resulting high power density of the devices that may not be sufficiently dissipated into the

surroundings.

One alternative that was explored was to investigate the behaviour of the tunneling field-effect transis-

tor. This device holds significant promise in offering a potentially reduced subthreshold slope compared

to n-type MOSFET devices. The initial tunneling field-effect transistor design had a subthreshold slope

greater than the thermionic limit of 60 mV/dec, however this may be due to imperfect bandgap alignment

at the tunneling junction. Further understanding and experimentation is required.

6.2 Future Work

The work can roughly be divided into two main areas of further exploration: Improved simulation models

and further research into tunneling field-effect transistor characteristics.

In terms of improving the Sentaurus simulation model, the model can first be extended and simulated

in a 3D structure environment. Since the current model is only developed in two dimensions, it does

not account for differences in structure that may occur in the third dimension. A few possibilities exist

of extending the model: a silicon-on-insulator structure could be implemented, as could a nanowire, or

34

Chapter 6. Conclusion 35

gate-all-around structure. Though a preliminary nanowire structure was created in Sentaurus as seen

in the Results section, this device has not yet been fully characterized. More non-idealities can also

be included in the simulation, including realistic parasitic capacitances, gate-oxide charge, and electron

trapped states.

For the tunneling field effect transistors, more experiments can be conducted to develop a useful

transistor structure, including optimizing gate and channel distances, material bandgaps, and doping

profiles. In addition, the AC characteristics of the device has yet to be simulated, including the cutoff

frequency, Ft, and the transconductance, gm.

Overall, there is significant exploration to be done in understanding small-scale and low-power elec-

tronic devices. Through the simulations in Sentaurus, the n-type MOSFET and the tunneling field-effect

transistor at nanoscale levels are shown to be viable devices, provided their manufacturability. However,

further research can be conducted to refine and improve their simulated structures.

Bibliography

[1] Adrian Mihai Boucart, Kathy; Ionescu. Double-Gate Tunnel FET With High-κ Gate Dielectric,

2007.

[2] An Chen. ITRS for Semiconductors, Emerging Research Devices Summary. In International Tech-

nology Roadmap for Semiconductors, 2013.

[3] Nguyen Dang Chien and Chun-Hsing Shih. Short-channel effect and device design of extremely

scaled tunnel field-effect transistors. Microelectronics Reliability, October 2014.

[4] G. Dewey, B. Chu-Kung, J. Boardman, J. M. Fastenau, J. Kavalieros, R. Kotlyar, W. K. Liu,

D. Lubyshev, M. Metz, N. Mukherjee, P. Oakey, R. Pillarisetty, M. Radosavljevic, H. W. Then, and

R. Chau. Fabrication, characterization, and physics of IIIV heterojunction tunneling Field Effect

Transistors (H-TFET) for steep sub-threshold swing. 2011 International Electron Devices Meeting,

3:33.6.1–33.6.4, December 2011.

[5] A.K. Geim and K.S. Novoselov. The rise of graphene. nature materials, 6:183–191, 2007.

[6] Elena Gnani, Antonio Gnudi, Susanna Reggiani, and Giorgio Baccarani. Theory of the junctionless

nanowire FET. IEEE Transactions on Electron Devices, 58(9):2903–2910, 2011.

[7] G. a M Hurkx, D. B M Klaassen, and M. P G Knuvers. A New Recombination Model for Device

Simulation Including tunneling. IEEE Transactions on Electron Devices, 39(2):331–338, 1992.

[8] Adrian M Ionescu and Heike Riel. Tunnel field-effect transistors as energy-efficient electronic

switches. Nature, 479(7373):329–37, November 2011.

[9] C. H. Jan, U. Bhattacharya, R. Brain, S. J. Choi, G. Curello, G. Gupta, W. Hafez, M. Jang,

M. Kang, K. Komeyli, T. Leo, N. Nidhi, L. Pan, J. Park, K. Phoa, a. Rahman, C. Staus, H. Tashiro,

C. Tsai, P. Vandervoorn, L. Yang, J. Y. Yeh, and P. Bai. A 22nm SoC platform technology featuring

3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high

36

Bibliography 37

density SoC applications. Technical Digest - International Electron Devices Meeting, IEDM, pages

44–47, 2012.

[10] Kanghoon Jeon. Band-to-Band Tunnel Transistor Design and Modeling for Low Power Applications.

PhD thesis, 2012.

[11] David L. Klein, Richard Roth, Andrew K. L. Lim, a. Paul Alivisatos, and Paul L. McEuen. A

single-electron transistor made from a cadmium selenide nanocrystal. Nature letters, 323(1982):3,

1997.

[12] S.O. Koswatta, D.E. Nikonov, and M.S. Lundstrom. Computational study of carbon nanotube p-

i-n tunnel FETs. In IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest.,

pages 8–11, 2005.

[13] T. Pearsall. Ga0.47In0.53As: A ternary semiconductor for photodetector applications. IEEE Jour-

nal of Quantum Electronics, 16(7):709–720, 1980.

[14] A Schenk. Rigorous Theory and Simplified Model of the Band-to-Band Tunneling in Silicon. Solid-

State Electronics, 36(1):19–34, 1993.

[15] Alan C. Seabaugh and Qin Zhang. Low-voltage tunnel transistors for beyond CMOS logic. Pro-

ceedings of the IEEE, 98(12):2095–2110, 2010.

[16] S. M. Sze and M. K. Lee. Semiconductor Devices: Physics and Technology. 2010.

[17] Lingquan Wang and Peter Asbeck. Design considerations for tunneling MOSFETs based on stag-

gered heterojunctions for ultra-low-power applications. In 2009 IEEE Nanotechnology Materials

and Devices Conference, number V, pages 196–199. Ieee, June 2009.

[18] Lingquan Wang, Student Member, Edward Yu, Senior Member, Yuan Taur, and Peter Asbeck.

Design of Tunneling Field-Effect Transistors Based on Staggered Heterojunctions for Ultralow-

Power Applications. IEEE Electron Device Letters, 31(5):431–433, 2010.

[19] S P Wong. Beyond the conventional transistor. IBM Journal of Research & Development, 46(2):133–

168, 2002.

[20] Clarence Zener. A Theory of the Electrical Breakdown of Solid Dielectrics. Proceedings of the Royal

Society of London, 145(855):523–529, 1934.

Appendices

38

Appendix A

NMOS Scaling: SDE Deck

; Sentaurus SDE Command File

; Scheme File using Sentaurus Device Editor

; Made By: Alice Ye

; Date: March 23, 2015

; Description:

;----------------------------------------------------------------------

; This script makes a 2D double-gated NMOS device. There’s a slight gaussian doping

; profile between the s/d and the substrate

; There is a gate on the top and the bottom, with options to change

; parameters listed below:

; Inputs:

;----------------------------------------------------------------------

; Lg = Gate Length, default 14 nm [um]

; Tox = Gate Oxide Thickness, default 2 nm [um]

; Tsi = Channel Thickness (height), default 5 nm [um]

; OxideMaterial = Gate Oxide Material (affects permittivity), default HfO2

; Ls = Source Length, default 14 nm [um]

; SourceMaterial = Source Material, default Silicon

; Ld = Drain Length, default 14 nm [um]

; DrainMaterial = Drain Material, default Silicon

; Lspacer = Spacer Length, default 5 nm [um]

; (equal length spacers surround channel)

; N_source = Concentration of dopants in source (n-type) default 5e20 [1/cm3]

; N_drain = Concennration of dopants in drain (n-type) default 5e20 [1/cm3]

; N_channel = Conc. of dopants in channel/substrate (p-type) default 1e15 [1/cm3]

; Code:

;----------------------------------------------------------------------

; 1. Initialize and Setup Parameters

;----------------------------------------------------------------------

39

Appendix A. NMOS Scaling: SDE Deck 40

(sde:clear)

(sdegeo:set-default-boolean "ABA") ; Overlap resolution - new replaces old

; Define Doping Concentrations

(define N_source @N_source@)

(define N_drain @N_drain@)

(define N_channel @N_channel@)

; Define Vertical Lengths

(define Tsi @Tsi@)

(define Tox @Tox@)

(define Ttot (+ Tsi Tox Tox)) ; 2*Oxide because of the top and bottom gate

; Define Lateral Lengths

; Already known: Lg, Lspacer, Ld, Ls

(define Lg @Lg@)

(define Lspacer @Lspacer@)

(define Ld @Ld@)

(define Ls @Ls@)

(define Ltot (+ Ls Lspacer Lg Lspacer Ld))

; Derived quantities

(define Xmax (/ Ltot 2.0))

(define Xg (/ Lg 2.0))

(define Xsg (+ (/ Lg 2) Lspacer))

(define Xdrain (* -1.0 (+ Xsg Ld)))

(define Xsource (+ Xsg Ls))

; 2. Create Geometry

;----------------------------------------------------------------------

; Silicon channel region

(sdegeo:create-rectangle (position (* Xsg -1.0) 0.0 0.0) (position Xsg Tsi 0.0) "Silicon" "R.Channel");

; Source region

(sdegeo:create-rectangle (position Xsource 0.0 0.0) (position Xsg Tsi 0.0) "@SourceMaterial@" "R.Source");

; Drain region

(sdegeo:create-rectangle (position Xdrain 0.0 0.0) (position (* Xsg -1.0) Tsi 0.0) "@DrainMaterial@" "R.Drain");

; Top gate oxide region

(sdegeo:create-rectangle (position (* Xsg -1.0) (* Tox -1.0) 0.0) (position Xsg 0.0 0.0) "@OxideMaterial@" "R.Gate_Oxide_Top");

; Bottom gate oxide region

(sdegeo:create-rectangle (position (* Xsg -1.0) Tsi 0.0) (position Xsg (+ Tsi Tox) 0.0) "@OxideMaterial@" "R.Gate_Oxide_Bottom");

(sde:showattribs "all");

; 3. Add Contacts

;----------------------------------------------------------------------

; Declare colour and style

(sdegeo:define-contact-set "source" 4.0 (color:rgb 1.0 0.0 0.0 ) "##" )


(sdegeo:define-contact-set "drain" 4.0 (color:rgb 0.0 1.0 0.0 ) "##" )

(sdegeo:define-contact-set "gate_bottom" 4.0 (color:rgb 0.0 0.5 0.5 ) "##" )

(sdegeo:define-contact-set "gate_top" 4.0 (color:rgb 0.0 0.5 0.5 ) "##" )

; Contact Settings:

; Source

(sdegeo:define-2d-contact (find-edge-id (position (- Xsource (/ Ls 2)) 0.0 0.0)) "source")

(sdegeo:define-2d-contact (find-edge-id (position (- Xsource (/ Ls 2)) Tsi 0.0)) "source")

; Drain

(sdegeo:define-2d-contact (find-edge-id (position (+ Xdrain (/ Ld 2)) 0.0 0.0)) "drain")

(sdegeo:define-2d-contact (find-edge-id (position (+ Xdrain (/ Ld 2)) Tsi 0.0)) "drain")

; Top gate

(sdegeo:insert-vertex (position (* -1.0 Xg) (* -1.0 Tox) 0.0))

(sdegeo:insert-vertex (position Xg (* -1.0 Tox) 0.0))

(sdegeo:define-2d-contact (find-edge-id (position 0.0 (* -1.0 Tox) 0.0)) "gate_top")

; Bottom gate

(sdegeo:insert-vertex (position (* -1.0 Xg) (+ Tox Tsi) 0.0))

(sdegeo:insert-vertex (position Xg (+ Tox Tsi) 0.0))

(sdegeo:define-2d-contact (find-edge-id (position 0.0 (+ Tox Tsi) 0.0)) "gate_bottom")

; 4. Doping Profiles

;----------------------------------------------------------------------

; Background doping level in channel (p-type)

(sdedr:define-refeval-window "BaseDop.Channel" "Rectangle"

(position (* -1.0 Xsg) 0.0 0.0) (position Xsg Tsi 0.0))

(sdedr:define-constant-profile "Const.Channel" "BoronActiveConcentration" N_channel)

(sdedr:define-constant-profile-placement "PlaceCD.Channel" "Const.Channel" "BaseDop.Channel")

; Source implant

(sdedr:define-refeval-window "BaseDop.Source" "Rectangle"

(position Xsource 0.0 0.0) (position Xsg Tsi 0.0))

; Source implant definition - gaussian profile

(sdedr:define-gaussian-profile "GaussDop.Source" "ArsenicActiveConcentration"

"PeakPos" 0 "PeakVal" N_source

"ValueAtDepth" N_channel "Depth" Lspacer "Gauss" "Factor" 1.0)

; Source implant placement

(sdedr:define-analytical-profile-placement "PlaceAP.Source"

"GaussDop.Source" "BaseDop.Source" "Positive" "NoReplace" "Eval")

; Drain implant

(sdedr:define-refeval-window "BaseDop.Drain" "Rectangle"

(position Xdrain 0.0 0.0) (position (* -1.0 Xsg) Tsi 0.0))

; Drain implant definition - gaussian profile

(sdedr:define-gaussian-profile "GaussDop.Drain" "ArsenicActiveConcentration"

"PeakPos" 0 "PeakVal" N_drain


; Drain implant placement - gaussian profile inward

(sdedr:define-analytical-profile-placement "PlaceAP.Drain"

"GaussDop.Drain" "BaseDop.Drain" "Positive" "NoReplace" "Eval")


; 5. Meshing Strategy

;----------------------------------------------------------------------

; Mesh constants

(define MinMesh 1e-3)

(define refsize_Ch_X 160 )

(define refsize_Ch_Y 16 )

(define refsize_Source_X 10 )

(define refsize_Source_Y refsize_Ch_Y)

(define refsize_Drain_X 10 )

(define refsize_Drain_Y refsize_Ch_Y)

(define refsize_Oxide_X 40 )

(define refsize_Oxide_Y 4 )

; Channel Mesh

(sdedr:define-refinement-size "Ref.Channel"

(/ (* Xsg 2) refsize_Ch_X) (/ Tsi refsize_Ch_Y) 0.0

MinMesh MinMesh 0.0)

(sdedr:define-refinement-region "RefPlace.Channel" "Ref.Channel" "R.Channel")

; Source Mesh

(sdedr:define-refinement-size "Ref.Source"

(/ Ls refsize_Source_X) (/ Tsi refsize_Source_Y) 0.0


(sdedr:define-refinement-region "RefPlace.Source" "Ref.Source" "R.Source")

; Drain Mesh

(sdedr:define-refinement-size "Ref.Drain"

(/ Ld refsize_Drain_X) (/ Tsi refsize_Drain_Y) 0.0


(sdedr:define-refinement-region "RefPlace.Drain" "Ref.Drain" "R.Drain")

; Top Gate Oxide Mesh

(sdedr:define-refinement-size "Ref.Gate_Oxide_Top"

(/ (* Xsg 2) refsize_Oxide_X) (/ Tsi refsize_Ch_Y) 0.0


(sdedr:define-refinement-region "RefPlace.Gate_Oxide_Top" "Ref.Gate_Oxide_Top" "R.Gate_Oxide_Top")

; Bottom Gate Oxide Mesh

(sdedr:define-refinement-size "Ref.Gate_Oxide_Bottom"

(/ (* Xsg 2) refsize_Oxide_X) (/ Tsi refsize_Ch_Y) 0.0


(sdedr:define-refinement-region "RefPlace.Gate_Oxide_Bottom" "Ref.Gate_Oxide_Bottom" "R.Gate_Oxide_Bottom")

; Output

;----------------------------------------------------------------------

(sdedr:write-cmd-file "n@node@_msh.cmd")

(sde:build-mesh "snmesh" " " "n@node@_msh")

Appendix B

NMOS Scaling: Sentaurus DeviceDeck

* Sentaurus Device Command File

* Scheme File using Sentaurus Device

* Author: Alice Ye

* Date: March 25, 2015

* Description:

*----------------------------------------------------------------------

* This script for a device ramps the device to a set gate voltage

* and then calculates the AC frequencies that it runs at. Data can be

* used to measure either Id-Vg or RF parameters such as Ft.

* Device Setup:

*----------------------------------------------------------------------

Device MOS

{

Electrode

{

{ Name="source" Voltage =0.0 }

{ Name="drain" Voltage =0.0 }

{ Name="gate_top" Voltage =0.0 Barrier = @GateBarrier@ }

{ Name="gate_bottom" Voltage =0.0 Barrier = @GateBarrier@ }

}

Thermode

{

{ Name = "source" Temperature = 300 }

{ Name = "drain" Temperature = 300 }

{ Name = "gate_top" Temperature = 300 }

{ Name = "gate_bottom" Temperature = 300 }

}

File

{

* input

Grid = "n@node|sde@_msh.tdr"

* output

43

Appendix B. NMOS Scaling: Sentaurus Device Deck 44

Plot = "n@node@_des.tdr"

Current = "n@node@_des.plt"

Param = "pp@node@_des.par"

* Output = "n@node@_des.log"

}

* Physics Setup:

*----------------------------------------------------------------------

*Physics

* {

* Mobility( DopingDependence HighFieldSat Enormal )

* EffectiveIntrinsicDensity( BandGapNarrowing( oldSlotboom ) )

* MLDA

* Fermi

* eQuantumPotential

** Hydrodynamic(eTemperature)

* Recombination(

* SRH( DopingDep )

** Band2Band

* )

* Noise(

* DiffusionNoise( eTemperature )

* MonopolarGRNoise

* FlickerGRNoise

* Doping(Mobility)

* )

* }

Physics

{

Mobility( DopingDependence HighFieldSat Enormal )

EffectiveIntrinsicDensity( BandGapNarrowing( oldSlotboom ) )

Noise(

DiffusionNoise( eTemperature )

MonopolarGRNoise

FlickerGRNoise

Doping(Mobility)

)

}

* Plot Information Setup

*----------------------------------------------------------------------

Plot

{

eDensity hDensity eCurrent hCurrent

ElectricField eEnormal hEnormal

eQuasiFermi hQuasiFermi

Potential Doping SpaceCharge

eMobility hMobility eVelocity hVelocity

DonorConcentration AcceptorConcentration

Doping


BandGap BandGapNarrowing ElectronAffinity

ConductionBandEnergy ValenceBandEnergy

eQuantumPotential

}

} * End of Device MOS

* File Setup:

*----------------------------------------------------------------------

File

{

* output

Output = "n@node@_ac_des.log"

ACExtract = "n@node@_ac_des.plt"

}

* Math Setup

*----------------------------------------------------------------------

Math

{

Number_of_Assembly_Threads = 4

Number_of_Solver_Threads = 4

Extrapolate

RelErrControl

Notdamped=50

Iterations=101

ExitOnFailure

}

System

{

MOS dc (source=s drain=d gate_top=g gate_bottom=g)

Vsource_pset vs (s 0) {dc=0}

Vsource_pset vd (d 0) {dc=0}

Vsource_pset vg (g 0) {dc=0}

}

* Sentaurus Device manual, p41, p129, p1265

Solve

{

#-a) zero solution

Coupled(Iterations=100) {Poisson eQuantumPotential}

Coupled(Iterations=100 LineSearchDamping= 1e-5) { Poisson eQuantumPotential Electron Hole }

#-b) ramp drain to 0.6 V

NewCurrentPrefix= "IdVd_"

Quasistationary (

InitialStep= 1e-2 Increment= 1.41

MinStep= 1e-15 MaxStep= 0.05

Goal { Parameter=vd.dc Voltage= @Vd@ }

){Coupled (Iterations = 30){ Poisson eQuantumPotential Electron Hole } }

Plot (FilePrefix= "n@node@_Vd")


#-c) ramp gate to 1.0 V

Quasistationary

(

InitialStep=1e-4 Increment=1.3

MaxStep=0.05 Minstep=1e-20

Goal { Parameter=vg.dc Voltage=@Vg@}

)

{ ACCoupled (

StartFrequency=@StartFrequency@

EndFrequency=@EndFrequency@

NumberOfPoints=@NumberOfPoints@ Decade

Node(s d g) Exclude(vs vd vg)

ObservationNode(g d s)

ACCompute (Time = (Range = (0 1) Intervals = 20))

)

{ Poisson eQuantumPotential Electron Hole }

}

}

Appendix C

3D Nanowire: SDE Deck

; Sentaurus SDE Command File

; Scheme File using Sentaurus Device Editor

; Made By: Alice Ye

; Date: April 02, 2015

; Description:

;----------------------------------------------------------------------

; This script makes a 3D gate-all-around NMOS nanowire device.

; There’s a slight gaussian doping

; profile between the s/d and the substrate

; Options to change parameters listed below:

; Inputs:

;----------------------------------------------------------------------

; Lg = Gate Length, default 14 nm [um]

; Tox = Gate Oxide Thickness, default 2 nm [um]

; Tch = Channel Thickness (Diameter), default 5 nm [um]

; OxideMaterial = Gate Oxide Material (affects permittivity), default HfO2

; Ls = Source Length, default 14 nm [um]

; SourceMaterial = Source Material, default Silicon

; Ld = Drain Length, default 14 nm [um]

; DrainMaterial = Drain Material, default Silicon

; Lspacer = Spacer Length, default 5 nm [um]

; (equal length spacers surround channel)

; N_source = Concentration of dopants in source (n-type) default 5e20 [1/cm3]

; N_drain = Concennration of dopants in drain (n-type) default 5e20 [1/cm3]

; N_channel = Conc. of dopants in channel/substrate (p-type) default 1e15 [1/cm3]

; Code:

;----------------------------------------------------------------------

; 1. Initialize and Setup Parameters

;----------------------------------------------------------------------

(sde:clear)

(sdegeo:set-default-boolean "ABA") ; Overlap resolution - new replaces old

; Define Doping Concentrations

47

Appendix C. 3D Nanowire: SDE Deck 48

(define N_source @N_source@)

(define N_drain @N_drain@)

(define N_channel @N_channel@)

; Define Vertical Lengths

(define Tch @Tch@)

(define Tox @Tox@)

(define Ttot (+ Tch Tox Tox)) ; 2*Oxide because of the top and bottom gate

(define Hg 1e-3) ; Height of gate metal

; Define Lateral Lengths

; Already known: Lg, Lspacer, Ld, Ls

(define Lg @Lg@)

(define Lspacer @Lspacer@)

(define Ld @Ld@)

(define Ls @Ls@)

(define Ltot (+ Ls Lspacer Lg Lspacer Ld))

; Derived quantities

(define Xmax (/ Ltot 2.0))

(define Xg (/ Lg 2.0))

(define Xsg (+ (/ Lg 2) Lspacer))

(define Xdrain (* -1.0 (+ Xsg Ld)))

(define Xsource (+ Xsg Ls))

; 2. Create Geometry

;----------------------------------------------------------------------

; Metal Gate region

(sdegeo:create-cylinder (position (* Xg -1.0) 0.0 0.0) (position Xg 0.0 0.0) (+ (/ Ttot 2) Hg) "Metal" "R.Gate_Metal");

; Gate Oxide region

(sdegeo:create-cylinder (position (* Xsg -1.0) 0.0 0.0) (position Xsg 0.0 0.0) (+ (/ Tch 2) Tox) "@OxideMaterial@" "R.Gate_Oxide");

; Channel region

(sdegeo:create-cylinder (position (* Xsg -1.0) 0.0 0.0) (position Xsg 0.0 0.0) (/ Tch 2) "@ChannelMaterial@" "R.Channel");

; Source region

(sdegeo:create-cylinder (position Xsource 0.0 0.0) (position Xsg 0.0 0.0) (/ Tch 2) "@SourceMaterial@" "R.Source");

; Drain region

(sdegeo:create-cylinder (position Xdrain 0.0 0.0) (position (* Xsg -1.0) 0.0 0.0) (/ Tch 2) "@DrainMaterial@" "R.Drain");

(sde:showattribs "all");

; 3. Add Contacts

;----------------------------------------------------------------------

; Declare colour and style

(sdegeo:define-contact-set "source" 4.0 (color:rgb 1.0 0.0 0.0 ) "##" )

(sdegeo:define-contact-set "drain" 4.0 (color:rgb 0.0 1.0 0.0 ) "##" )

(sdegeo:define-contact-set "gate" 4.0 (color:rgb 0.0 0.5 0.5 ) "##" )


; Contact Settings:

; Source

(sdegeo:set-current-contact-set "source")

(sdegeo:set-contact-faces (find-face-id (position (- Xsource (/ Xsg 2)) (/ Tch 2) 0.0 )))

; Drain

(sdegeo:set-current-contact-set "drain")

(sdegeo:set-contact-faces (find-face-id (position (+ Xdrain (/ Xsg 2)) (/ Tch 2) 0.0 )))

; Gate

(sdegeo:set-current-contact-set "gate")

(sdegeo:set-contact-faces (find-face-id (position 0.0 (+ (/ Ttot 2) Hg) 0.0)))

; 4. Doping Profiles

;----------------------------------------------------------------------

; Background doping level in channel (p-type)

; (sdedr:define-refeval-window "BaseDop.Channel" "Rectangle"

; (position (* -1.0 Xsg) 0.0 0.0) (position Xsg Tch 0.0))

; (sdedr:define-constant-profile "Const.Channel" "BoronActiveConcentration" N_channel)

; (sdedr:define-constant-profile-placement "PlaceCD.Channel" "Const.Channel" "BaseDop.Channel")

(sdedr:define-constant-profile "Const.Channel" "BoronActiveConcentration" N_channel)

(sdedr:define-refinement-window "BaseDop.Channel" "Cuboid"

(position (* -1.0 Xsg) (* -1.0 Ttot) (* -1.0 Ttot)) (position Xsg Ttot Ttot))

(sdedr:define-constant-profile-placement "PlaceCD.Channel" "Const.Channel" "BaseDop.Channel")

; (sdedr:define-constant-profile "SD" DopSD 2.5e20)

; (sdedr:define-refinement-window "Drain_PlBox" "Cuboid"

; (position Xcha -30 -30)

; (position (+ Xfin 30) (+ Yfin 30) (+ Zfin 30)))

; (sdedr:define-constant-profile-placement "Drain_PL" "SD" "Drain_PlBox" 8)

; Source implant

(sdedr:define-refeval-window "BaseDop.Source" "Cuboid"

(position Xsource (* -1.0 Tox) (* -1.0 Tox)) (position Xsg Tox Tox))

; Source implant definition - gaussian profile

(sdedr:define-gaussian-profile "GaussDop.Source" "ArsenicActiveConcentration"

"PeakPos" 0 "PeakVal" N_source


; Source implant placement

(sdedr:define-analytical-profile-placement "PlaceAP.Source"

"GaussDop.Source" "BaseDop.Source" "Positive" "NoReplace" "Eval")

; Drain implant

(sdedr:define-refeval-window "BaseDop.Drain" "Cuboid"

(position Xdrain (* -1.0 Tox) (* -1.0 Tox)) (position (* -1.0 Xsg) Tox Tox))

; Drain implant definition - gaussian profile

(sdedr:define-gaussian-profile "GaussDop.Drain" "ArsenicActiveConcentration"

"PeakPos" 0 "PeakVal" N_drain


; Drain implant placement - gaussian profile inward

(sdedr:define-analytical-profile-placement "PlaceAP.Drain"

"GaussDop.Drain" "BaseDop.Drain" "Positive" "NoReplace" "Eval")


; 5. Meshing Strategy

;----------------------------------------------------------------------

; Mesh constants

(define MinMesh 1e-3)

(define refsize_Ch_X 20 )

(define refsize_Ch_Y 8 )

(define refsize_Ch_Z 8 )

(define refsize_Source_X 10 )

(define refsize_Source_Y refsize_Ch_Y)

(define refsize_Source_Z refsize_Ch_Z)

(define refsize_Drain_X 10 )

(define refsize_Drain_Y refsize_Ch_Y)

(define refsize_Drain_Z refsize_Ch_Z)

(define refsize_Oxide_X 10 )

(define refsize_Oxide_Y 4 )

(define refsize_Oxide_Z 4 )

; Channel Mesh

(sdedr:define-refinement-size "Ref.Channel"

(/ (* Xsg 2) refsize_Ch_X) (/ Tch refsize_Ch_Y) (/ Tch refsize_Ch_Z)

MinMesh MinMesh MinMesh)

(sdedr:define-refinement-region "RefPlace.Channel" "Ref.Channel" "R.Channel")

; Source Mesh

(sdedr:define-refinement-size "Ref.Source"

(/ Ls refsize_Source_X) (/ Tch refsize_Source_Y) (/ Tch refsize_Source_Z)


(sdedr:define-refinement-region "RefPlace.Source" "Ref.Source" "R.Source")

; Drain Mesh

(sdedr:define-refinement-size "Ref.Drain"

(/ Ld refsize_Drain_X) (/ Tch refsize_Drain_Y) (/ Tch refsize_Drain_Z)


(sdedr:define-refinement-region "RefPlace.Drain" "Ref.Drain" "R.Drain")

; Top Gate Oxide Mesh

(sdedr:define-refinement-size "Ref.Gate_Oxide"

(/ (* Xsg 2) refsize_Oxide_X) (/ Tch refsize_Ch_Y) (/ Tch refsize_Ch_Z)


(sdedr:define-refinement-region "RefPlace.Gate_Oxide" "Ref.Gate_Oxide" "R.Gate_Oxide")

; ; Bottom Gate Oxide Mesh

; (sdedr:define-refinement-size "Ref.Gate_Oxide_Bottom"

; (/ (* Xsg 2) refsize_Oxide_X) (/ Tch refsize_Ch_Y) 0.0

; MinMesh MinMesh 0.0)

; (sdedr:define-refinement-region "RefPlace.Gate_Oxide_Bottom" "Ref.Gate_Oxide_Bottom" "R.Gate_Oxide_Bottom")

; Output

;----------------------------------------------------------------------

(sdedr:write-cmd-file "n@node@_msh.cmd")

(sde:build-mesh "snmesh" " " "n@node@_msh")

Appendix D

2D TFET: Sentaurus Device Deck

* Sentaurus Device Command File

* Scheme File using Sentaurus Device

* Author: Alice Ye

* Date: March 25, 2015

* Description:

*----------------------------------------------------------------------

* This script for a device ramps the device to a set gate voltage

* and then calculates the AC frequencies that it runs at. Data can be

* used to measure either Id-Vg or RF parameters such as Ft.

* Device Setup:

*----------------------------------------------------------------------

Device MOS

{

Electrode

{

{ Name="source" Voltage =0.0 }

{ Name="drain" Voltage =0.0 }

{ Name="gate_top" Voltage =0.0 Barrier = @GateBarrier@ }

{ Name="gate_bottom" Voltage =0.0 Barrier = @GateBarrier@ }

}

Thermode

{

{ Name = "source" Temperature = 300 }

{ Name = "drain" Temperature = 300 }

{ Name = "gate_top" Temperature = 300 }

{ Name = "gate_bottom" Temperature = 300 }

}

File

{

* input

Grid = "n@node|sde@_msh.tdr"

* output

Plot = "n@node@_des.tdr"

Current = "n@node@_des.plt"

51

Appendix D. 2D TFET: Sentaurus Device Deck 52

Param = "pp@node@_des.par"

* Output = "n@node@_des.log"

}

* Physics Setup:

*----------------------------------------------------------------------

*Physics

* {



* MLDA

* Fermi

* eQuantumPotential

** Hydrodynamic(eTemperature)

* Recombination(

* SRH( DopingDep )

** Band2Band

* )

* Noise(


* MonopolarGRNoise

* FlickerGRNoise

* Doping(Mobility)

* )

* }

Physics{

* DriftDiffusion

eQuantumPotential

* Alice removed to match quantum -- Fermi

EffectiveIntrinsicDensity( BandGapNarrowing(OldSlotboom) )

Mobility(

DopingDep

eHighFieldsaturation( GradQuasiFermi )

hHighFieldsaturation( GradQuasiFermi )

Enormal

)

* Note: Recombination wasn’t in here before and simulations were converging!

Recombination(

SRH( DopingDep TempDependence )

Band2Band (

Model = Hurkx

* DensityCorrection = Local

)

* Avalanche (vanOverstraeten)

* Auger

)

* MoleFraction( xFraction=0.15 RegionName="R.Source")

}

Physics (Region = "R.Source") {

MoleFraction(xFraction=0.1)


}

Physics (Region = "R.Channel") {


}

Physics (Region = "R.Drain") {


}

* NOte: this one was the selected physics before and failed

* Physics

* {



* Noise(


* MonopolarGRNoise

* FlickerGRNoise

* Doping(Mobility)

* )

* }

* Plot Information Setup

*----------------------------------------------------------------------

Plot

{

eDensity hDensity eCurrent hCurrent

ElectricField eEnormal hEnormal

eQuasiFermi hQuasiFermi

Potential Doping SpaceCharge

eMobility hMobility eVelocity hVelocity

DonorConcentration AcceptorConcentration

Doping

BandGap BandGapNarrowing ElectronAffinity

ConductionBandEnergy ValenceBandEnergy

eQuantumPotential

}

} * End of Device MOS

* File Setup:

*----------------------------------------------------------------------

File

{

* output

Output = "n@node@_ac_des.log"

ACExtract = "n@node@_ac_des.plt"

}

* Math Setup

*----------------------------------------------------------------------

Math

{

Number_of_Assembly_Threads = 4

Number_of_Solver_Threads = 4


Extrapolate

RelErrControl

Notdamped=50

Iterations=101

ExitOnFailure

}

System

{

MOS dc (source=s drain=d gate_top=g gate_bottom=g)

Vsource_pset vs (s 0) {dc=0}

Vsource_pset vd (d 0) {dc=0}

Vsource_pset vg (g 0) {dc=0}

}

* Sentaurus Device manual, p41, p129, p1265

Solve

{

#-a) zero solution

Coupled(Iterations=100) {Poisson eQuantumPotential}

Plot (FilePrefix = "output/n@node@_poisson")

Coupled(Iterations=100 LineSearchDamping= 1e-5) { Poisson eQuantumPotential Electron Hole }

Plot (FilePrefix="output/n@node@_electric")

#-b) ramp drain to Drain Voltage

NewCurrentPrefix= "IdVd_"

Quasistationary (

InitialStep= 1e-3 Increment=1.3

MinStep= 1e-10 MaxStep= 0.05

Goal { Parameter=vd.dc Voltage= @Vd@ }

){Coupled (Iterations = 30){ Poisson eQuantumPotential Electron Hole } }

Plot (FilePrefix= "output/n@node@_Vd")

#-c) ramp gate to 1.0 V

Quasistationary

(

InitialStep=1e-2 Increment=1.3

MaxStep=0.05 Minstep=1e-10

Goal {Parameter=vg.dc Voltage=@Vg@}

Plot {Range = (0 1) Intervals=3 }

) {Coupled (Iterations = 30){ Poisson eQuantumPotential Electron Hole } }

* { ACCoupled (

* StartFrequency=@StartFrequency@

* EndFrequency=@EndFrequency@

* NumberOfPoints=@NumberOfPoints@ Decade

* Node(s d g) Exclude(vs vd vg)

* ObservationNode(g d s)

* ACCompute (Time = (Range = (0 1) Intervals = 20))

* )

* { Poisson eQuantumPotential Electron Hole }

* }


}

Documents

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