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MIXED SIGNAL RADIATION

TOLERANT DESIGN WITH DARE KNUT

ASIC

© IMEC 2010

OVERVIEW

▸ KNUT ASIC▸ Mixed Signal Design Flow▸ Design Analog Blocks▸ Integration of Analog Blocks▸ Physical Verification▸ Conclusions

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KNUT ASIC

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MIXED SIGNAL DESIGN FLOW

▸ Digital-on-top approach, based on- Complexity of digital part- Area estimation digital/analog- Number/type of analog blocks- Experience/familiarity with digital flow for DARE

▸ Extra requirements for analog blocks- Floor planning, placement and routing

Additional layers, additional labels, port placement, ..

- Timing analysis Additional simulations

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DESIGN ANALOG BLOCKS

▸ Current-steering DAC▸ Capacitive SAR ADC▸ Analog I/O

Schematic entry + SPICE simulatorStandard available UMC Mixed-Mode PDKStandard DRC checkingCustom LVS checkingExtra RAD checking

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DAC SPECIFICATION

Specification Range

Resolution 10 bit

DNL < 1 LSB

INL < 1 LSB

Temperature Range -55 °C .. +125 °C

Analog Supply Voltage VDDA = 3.3 V +/- 10%

Temperature Drift < 10 LSB

ILSB low current range 1µA .. 6 µA

ILSB high current range 5 µA .. 30 µA

Total Dose 100 krad

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DAC DESIGN

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DAC LAYOUT IMPLEMENTATION

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10b Bin2Thermo(fully digital P&R)

Current sourcesmatrix withlocal level shifter

Bias voltagegeneration

© IMEC 2010

ADC SPECIFICATION

Specification Range

Resolution 10 bit

DNL < 1 LSB

INL < 1 LSB

Temperature Range -55 °C .. +125 °C

Analog Supply Voltage VDDA = 3.3 V +/- 10%

Temperature Drift < 1 LSB

Input Voltage Range 0 < Vin < VFS

Full Scale Voltage 1.4 < VFS < VDDA

Conversion Speed < 1 ms

Total Dose 100 krad

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ADC DESIGN

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ADC LAYOUT IMPLEMENTATION

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SAR + level shifters(full custom layout)

analog switches

MiM capacitor array

Comparator and referencevoltage generation

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ANALOG I/O

▸ Dedicated 3.3V analog power and ground▸ Analog input and output▸ Same protection device used as in digital I/O

Full chip ESD behavior initially not good enough(~ 500 V HBM) due to broken ring

ESD optimization (bulk connections, distances, marker layers) increases performance beyond2KV HBM

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INTEGRATION OF ANALOG BLOCKS

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abstract generatorLEF script

analog simulationLIB template

layout

LEF file LIB file

schematic

vhdl

model description

© IMEC 2010

PHYSICAL VERIFICATION

▸ Default checks: DRC, LVS, ANT, ERC▸ Extra ‘RAD’ check:

- Digital layout = standard cell library, well defined flow => correct-by-design/flow

- Analog layout = full custom => prone to mistakes during cell layout or integration on top level

- Checks for NMOS ELT compliance Presence of guard bands Forbidden polysilicon routing

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© IMEC 2010

CONCLUSIONS

▸ KNUT ASIC demonstrates the feasibility of a Mixed Signal design flow for Space Applications with the DARE library

▸ The digital-on-top approach needs descriptions of the analog blocks for doing P&R, STA, IR-drop and power analysis

▸ ESD performance is proven▸ RAD check gives added value in mixed-

mode designs

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© IMEC 2010

QUESTIONS ?