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CIRCUIT BOOTSTRAPPING TECHNIQUES FOR EXTENDED VOLTAGE RANGE AND IMPROVED EFFICIENCY IN LOW-VOLTAGE TRIPLE-WELL CMOS
INTEGRATED CIRCUITS WITH DRIVEN CAPACITIVE LOADS
By
CHRISTOPHER MICHAEL DOUGHERTY
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2016
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© 2016 Christopher Michael Dougherty
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This dissertation is dedicated to my grandparents (all four), my parents (both sets), my siblings, and my wife. I thank you for your never-ending encouragement.
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ACKNOWLEDGEMENTS
First, I would like to express my sincere gratitude to my advisor Prof. Rizwan
Bashirullah, for bringing me into his research group as an undergraduate student many
years ago, for uncountable hours of technical discussions, and for taking me on as a
full-time researcher and member of the Integrated Circuits Research Laboratory. I am
most grateful for the opportunity to delve deeply into topics that have fascinated me
without financial distress or major distraction. Not so many generations back, this would
have been a privilege open only to the very wealthy and one cannot overestimate the
profound positive impact it’s had on my life trajectory. This was all made possible by the
financial support of the University of Florida Alumni Association, the UF Department of
Electrical and Computer Engineering, the US Army Research Laboratory (ARL) and
Texas Instruments.
Second, I would like to thank the members of my PhD committee, Professors
Robert Fox, Scott Thompson, and Richard Lind, for their patience and willingness to
oversee my research. Dr. Fox, in particular, has greatly influenced the direction of this
work and, much earlier, my decision to make a career out of electronic circuits. I’ve
thoroughly enjoyed his approach to teaching and his open-door policy for questions.
These traits I mimicked when working as a Teacher’s Assistant for the department,
another exceptionally fruitful and joyful endeavor initiated by Dr. Fox and Dr.
Bashirullah.
Collaborating on an ARL sponsored project, especially one requiring a multi-
faceted attack combining several disciplines (IC design, MEMS fabrication techniques,
power electronics, and even flight mechanics), proved to be both exciting and
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enlightening. For this, I owe much credit to Prof. David Arnold, Christopher Meyer, Brian
Morgan, Sarah Bedair, and Jeffrey Pulskamp.
My years in the lab were greatly enriched by my colleagues, most of them senior
to myself. Chun-Ming Tang, Chung-Ching Peng, Hong Yu, Yan Hu, Quizhong Wu, and
Jikai Chen were particularly helpful in taking the mystery out of Cadence IC design
software and were great resources in general. I appreciate Pengfei Li and Zhiming Xiao
(“Xiao Lǎoshī”) for trusting my minor but potentially hazardous contributions to their
projects, providing a perfect incubator for skill development. Pawan Sabharwal and
Deepak Bhatia were not only great sources of humor but were inspirational, the
absolute examples of dedication and work-ethic (perhaps the most important
ingredients for success). Working with Lin Xue and Walker Turner significantly improved
the quality of my academic output and made lab-life even more enjoyable. My
overlapping time in the lab with E. Felipe Garay, Lawrence Fomundam, and visiting
Prof. André Aita was also appreciated, for both social and academic reasons. Overall,
my time on the 5th floor of NEB was enhanced by interactions with many great people—
too many to name— who I will never forget.
Having the opportunity to finish the degree part-time, while living out an
adventure abroad and working full-time for Texas Instruments, brought me in contact
with talented engineers who ultimately had an influential but largely indirect effect on the
quality of the work presented in this dissertation. A proper list of individuals would not fit
here but, for reasons of technical and moral support, I can’t help but thank Dr. Stephan
Endrass, Santhosh Shankar, Maciej Jankowski, Su Gin Ong, Sudarshan Udayashankar,
and Caspar van Vroonhoven.
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Finally, the years of dedication needed for completing a PhD are rarely felt by the
student alone; my case is no different. My family has been steadfast in their patience,
love, and support. In particular, my wife Erica has endured many sacrifices, giving me
the necessary time and resources to finish. In truth, I never would have succeeded
otherwise.
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TABLE OF CONTENTS page
ACKNOWLEDGEMENTS ............................................................................................... 4
LIST OF TABLES ............................................................................................................ 9
LIST OF FIGURES ........................................................................................................ 10
LIST OF ABBREVIATIONS ........................................................................................... 14
ABSTRACT ................................................................................................................... 15
CHAPTER
1 INTRODUCTION .................................................................................................... 17
1.1 Motivation ......................................................................................................... 17
1.2 Research Goals ................................................................................................ 19 1.3 Dissertation Organization .................................................................................. 27
2 LITERATURE REVIEW .......................................................................................... 28
2.1 Application Overview: PZT-Based Micro-Robotic Insects ................................. 28 2.2 Power Conversion Techniques and Choice of SC Converter ........................... 29
2.3 Fundamental Loss Mechanisms for SC Converters .......................................... 33 2.3.1 Capacitor Energy Transfer – An Overview .............................................. 33
2.3.2 Energy Transfer from Voltage Source to Capacitor (Charging) ............... 35 2.3.3 Energy Transfer from Capacitor to Capacitor .......................................... 39 2.3.4 Energy Transfer from Capacitor to Current-Source Load ........................ 48
2.3.5 Energy Transfer from Capacitor to ZL ...................................................... 50 2.3.6 Conduction Loss and Explanation of ROUT............................................... 51
2.3.7 Pedagogical Example: (Pseudo) Four-Phase Series-Parallel SC Converter ...................................................................................................... 53
2.3.8 Comments on Dynamic Models for SC Power Converters ...................... 61
2.4 Charge-Pump and SC Power Converter Architectures ..................................... 62 2.5 An Overview of Bootstrapping Techniques ....................................................... 62
2.6 Conclusions for Chapter 2 ................................................................................ 65
3 A 10V FULLY-INTEGRATED BIDIRECTIONAL SC LADDER CONVERTER IN 0.13 μm CMOS USING NESTED-BOOTSTRAPPED SWITCH CELLS (TASK 1) .. 66
3.1 Application and Design Overview ..................................................................... 66 3.1.1 Background ............................................................................................. 66 3.1.2 Integrated Power Converters with Voltage Waveform Outputs ............... 68 3.1.3 Proposed Switched-Mode Amplifier Architecture .................................... 70 3.1.4 Sizing of MIM Capacitors and MOSFET Switches .................................. 74
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3.2 Circuit Implementation ...................................................................................... 77
3.2.1 Bidirectional SC Ladder Converter in Triple-Well CMOS ......................... 77 3.2.2 Development of Voltage Compliant Nested-Bootstrapped Switch
(NBS) Cell ..................................................................................................... 81 3.2.3 Voltage-Compliant High-Voltage Signals with Multiple NBS Cells ........... 91
3.3 Experimental Results for 1:3 Step-up Driver ..................................................... 95 3.4 Conclusions for Chapter 3 .............................................................................. 104
4 POTENTIAL DESIGN IMPROVEMENTS FOR SC LADDER STEP-UP DRIVE STAGE (TASK 1) .................................................................................................. 105
4.1 Background ..................................................................................................... 105 4.2 Concept Overview........................................................................................... 106
4.3 MOS-Only NBS Cells and the Cross-Coupled NMOS Switch ......................... 109 4.4 System-Level Improvements by Exploiting Symmetry .................................... 114 4.5 Supporting Simulation Results ........................................................................ 122
4.6 Conclusions for Chapter 4 .............................................................................. 127
5 A 3.3V BOOTSTRAPPED PIEZO-ACTUATOR CAPACITIVE LOAD (PRE)-DRIVER FOR ENABLING ENERGY RECOVERY AND CLASS G TECHNIQUES (TASK 2) ....................................................................................... 129
5.1 Background ..................................................................................................... 129
5.2 Choice of Design Direction ............................................................................. 133 5.3 Bootstrapped Push-Pull Source-Follower for Rail-to-Rail Drive ...................... 136
5.4 Feedback Stability and Frequency Compensation .......................................... 149 5.5 Measurement Results ..................................................................................... 157
5.6 Conclusions for Chapter 5 .............................................................................. 163
6 SUMMARY AND FUTURE WORK ....................................................................... 164
6.1 Summary ........................................................................................................ 164
6.2 Future Work .................................................................................................... 166
LIST OF REFERENCES ............................................................................................. 171
BIOGRAPHICAL SKETCH .......................................................................................... 186
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LIST OF TABLES
Table page 1-1 Specification summary ....................................................................................... 22
3-1 Comparison table ............................................................................................. 103
5-1 Key device sizes ............................................................................................... 138
5-2 Extracted parameters for hand calculation ....................................................... 156
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LIST OF FIGURES
Figure page 1-1 ARL Micro-Flyer prototype. ................................................................................. 18
1-2 Required drive waveforms for the ARL Micro-Flyer prototype. ........................... 19
1-3 Simplified piezo-actuator load model. ................................................................. 20
1-4 Task 1 – Design of 1:3 step-up driver. ................................................................ 23
1-5 Task 2 – Efficient “pre-drive” of the step-up driver. ............................................. 24
2-1 Harvard’s Robo-Fly has ~1.5 cm wings and requires 200V ................................ 29
2-2 Hybrid-SI-SC converter from [10]. ...................................................................... 30
2-3 Two-step solution for bidirectional drive from [51]. ............................................. 32
2-4 VBAT charging a capacitor through REFF. ............................................................. 35
2-5 Capacitor-to-capacitor current transfer through REFF.. ........................................ 40
2-6 Supporting plots for Equations (2-22) through (2-35) for complete charging. ..... 46
2-7 Supporting plots for Equations (2-22) through (2-35) for partial charging. .......... 47
2-8 Initially charged capacitor transferring energy to a current-source load. ............ 48
2-9 Example 4-phase series-parallel voltage doubler. .............................................. 54
2-10 Charging event waveforms with time axis normalized to TPER.. .......................... 56
2-11 Simulation results summarized. .......................................................................... 59
2-12 Extracted quantities from simulation. .................................................................. 60
3-1 Diagram of 1:3 step-up driver. ............................................................................ 67
3-2 SC ladder converter with ideal switches. ............................................................ 71
3-3 Results of MATLAB sizing routine and embedded model. .................................. 73
3-4 Summary of SPICE transient simulations using ideal capacitors and ideal switches with on-resistance.. .............................................................................. 76
3-5 Three-stage SC ladder with proposed switch arrangement and ideal floating switch drivers (voltage source clocks, in gray).................................................... 77
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3-6 Voltage compliant gate drive signals for each voltage domain. .......................... 78
3-7 Bulk and well connections (with p-type substrate at ground potential). .............. 79
3-8 Traditional gate-drive using floating CMOS inverter drivers powered by subsequent stage voltages [23]: not directly compatible here. ........................... 80
3-9 Typical bootstrapped switch used in data-converters [96], in the “offstate”. ....... 81
3-10 Development of “Nested-Bootstrapped Switch” (NBS) cell. ................................ 83
3-11 Leakage path identification and removal.. .......................................................... 85
3-12 Nested-Bootstrapped Switch (NBS) cell. ............................................................ 86
3-13 Simulation results (BSIM3v3 models) showing Φ1M, VGS-N7 with varying VIN. ..... 87
3-14 NBS cell simplified model considering capacitive loading. ................................. 89
3-15 Simplified process cross-section showing important parasitics. ......................... 90
3-16 Cascading NBS cells to create Φ1H using several M domain clocks. .................. 92
3-17 Detailed system diagram. ................................................................................... 93
3-18 Detailed simulation results using BSIM3v3 device models. ................................ 94
3-19 Typical stroke and pitch waveforms under worst-case specified loading conditions and highest signal frequency. ............................................................ 95
3-20 Step response for various fSW. ............................................................................ 96
3-21 Efficiency vs. VOUT and POUT for various fSW and resistive loads. ........................ 97
3-22 Measured waveforms. ........................................................................................ 98
3-23 ROUT vs fSW. ........................................................................................................ 99
3-24 Measurements vs. fIN.. ...................................................................................... 100
3-25 Response to a small input signal. ..................................................................... 101
3-26 Die photo of prototype test chip. ....................................................................... 101
3-27 ARL Micro-Flyer prototype as driven by proposed SC ladder IC. ..................... 102
4-1 SC ladder converter with ideal switches. .......................................................... 106
4-2 Nested-Bootstrapped Switch (NBS) cell. .......................................................... 109
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4-3 MOS-Only Nested-Bootstrapped Switch (MO-NBS) cell. ................................. 110
4-4 Simulated complement drive signals using MO-NBS cells. .............................. 111
4-5 MO-NBS simplification steps. . ........................................................................ 112
4-6 Simulation results for CC-NM. .......................................................................... 113
4-7 Single-phase output three-stage SC ladder. ..................................................... 115
4-8 Dual-phase SC ladder. ..................................................................................... 116
4-9 Dual-phase SC ladder with combined CC-NM and MO-NBS drive. .................. 117
4-10 Simulation results for CC-NM / MO-NBS implementation of Figure 4-9. .......... 118
4-11 Cross-coupled PMOS for negative clocks. ....................................................... 119
4-12 Concept for PMOS drive with negative-going voltage signals. ......................... 120
4-13 Compact dual-phase SC ladder drive stage. .................................................... 121
4-14 Extracted RON for main SC ladder switches over corners and temperature. ..... 123
4-15 Results of transient simulations for compact dual-phase SC ladder drive stage over device corners and temperature (with nominal MIM capacitors). .... 124
4-16 Transient simulation outputs for minimum and maximum MIM capacitor densities and nominal transistors (27°C). ......................................................... 125
4-17 Extracted simulated ROUT vs. fSW. ..................................................................... 126
5-1 Task 2 – Efficient “pre-drive” of the step-up driver. ........................................... 129
5-2 SC ladder simplified models.. ........................................................................... 130
5-3 Thevenin equivalent circuit representation of pre-driver. .................................. 133
5-4 Output stages. .................................................................................................. 134
5-5 Pre-driver prototype simplified schematic. ........................................................ 137
5-6 Waveforms depicting bootstrapped supply scheme. ........................................ 139
5-7 Simulated periodic steady-state waveforms using BSIM3v3 models. ............... 140
5-8 Simulated start-up operation for pre-driver.. ..................................................... 141
5-9 CBOOT waveforms in periodic steady-state.. ...................................................... 142
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5-10 Compatible efficiency improvement schemes.. ................................................ 143
5-11 Bias distribution block with shielding devices. .................................................. 144
5-12 Implementation of integrated MOS diodes. ...................................................... 146
5-13 NMOS current-mirror operating below substrate potential. ............................... 148
5-14 PMOS current-mirror operating above supply potential. ................................... 149
5-15 Simplified view of pre-driver for stability analysis. ............................................. 150
5-16 Small-signal model for loop analysis. ............................................................... 151
5-17 Simplified schematic showing STB probe placement and four feedback loops. ................................................................................................................ 154
5-18 STB simulation results at four transient operating points. ................................. 155
5-19 Die photo of pre-driver prototype. ..................................................................... 157
5-20 Properly functioning DC bias condition. ............................................................ 158
5-21 Proper operation while emulating Micro-Flyer application. ............................... 159
5-22 Combined measurement using all three prototypes ......................................... 160
5-23 Proper operation while emulating E-field sensor application. ........................... 160
5-24 Measured driver operation. ............................................................................... 161
5-25 Measured total supply current vs. waveform frequency. ................................... 162
6-1 Diagram showing combined solution. ............................................................... 167
6-2 Preliminary simulation results for the block diagram of Figure 6-1. .................. 168
6-3 Schematic with potential system-level augmentations. ..................................... 169
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LIST OF ABBREVIATIONS
ARL Army Research Laboratory
BJT Bipolar-Junction Transistor
BTS Bootstrapped-Switch
CC-NM Cross-Coupled NMOS
CC-PM Cross-Coupled PMOS
CMOS Complimentary Metal-Oxide-Semiconductor
ESR Equivalent Series Resistance
FSL Fast-Switching Limit
MEMS Micro Electrical-Mechanical System(s)
MO-NBS MOS-Only Nested-Bootstrapped Switch
MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
NBS Nested-Bootstrapped Switch
PCB Printed Circuit Board
PZT Lead Zirconate Titanate
SBD Schottky-Barrier Diode
SC Switched-Capacitor
SL Switched-Inductor
SSL Slow-Switching Limit
THD Total Harmonic Distortion
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
CIRCUIT BOOTSTRAPPING TECHNIQUES FOR EXTENDED VOLTAGE RANGE
AND IMPROVED EFFICIENCY IN LOW-VOLTAGE TRIPLE-WELL CMOS INTEGRATED CIRCUITS WITH DRIVEN CAPACITIVE LOADS
By
Christopher Michael Dougherty
December 2016
Chair: Rizwan Bashirullah Major: Electrical and Computer Engineering
The development of many integrated systems using CMOS technology has been
hindered by the down-scaling of the device voltage rating, typically near 1V for modern
process nodes. Historically, this trend has been accompanied by many improvements
for digital blocks but has often limited the performance of associated analog and power
electronic sub-circuits or complicated their implementations. A particularly challenging
application, and the motivation for this work, is the realization of an autonomous fully-
mobile flying robotic insect where the balanced demands of integration and voltage
handling capability are both at extremes and the available battery power is strictly
limited. This dissertation explores the combination of circuit bootstrapping and switched-
capacitor techniques for efficiently driving a 5nF 10V 2-millimeter wing piezo-electric
robotic fruit-fly within a 1.2V/3.3V triple-well CMOS technology. Specifically, Nested-
Bootstrapped Switch (NBS) cells are introduced for the creation and safe-handling of
~10V DC-500 Hz arbitrary waveforms on chip without external components. A simplified
implementation using combinations of cross-coupled NMOS and PMOS switches,
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creating dual-polarity clock waveforms, is also proposed to increase efficiency and/or
offer a more compact solution. Finally, a capacitive load “pre-driver” with bootstrapped
supplies enables energy recycling for up to a ~30% reduction in battery current with
minimal impact on drive signal quality.
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CHAPTER 1 INTRODUCTION
1.1 Motivation
Progress towards the realization of an autonomous fully-mobile flying robotic
insect has been ongoing for more than a decade [1], taking inspiration from biological
flapping-wing counterparts found in nature. Advanced prototypes utilize piezo-actuators
and wing structures fabricated using MEMS techniques, resulting in impressive life-like
features and a well-defined interface for the associated electronic circuitry needed to
drive and control the synthetic organism. However, even at the centimeter scale, where
the potential flight capabilities of such a robot are maturing at an impressive rate [2],
successfully combining the available battery technologies (typically of 5V or less) with
portable and miniaturized power electronic drive circuitry has proven difficult [3],
especially due to the large actuation voltage requirements (often over 100V) for these
bee-sized prototypes. Published architectures for implementing the drive circuitry have
been almost exclusively based around off-chip inductors or transformers that are
partnered with high-voltage (HV) MOS devices, also external to the main IC [4] [5] [6] [7]
with one recent exception including on-chip HV MOS devices in a specialized power
DMOS process [8]. Considering the strict limits on allotted size and mass for this
application space, and the combined requirements of high-voltage and low-power
consumption, these magnetic components are often custom-made, in certain instances
requiring dedicated investigations of their own [9] [10], and are not directly compatible
with standard CMOS processes. At the time of writing this dissertation a complete
power solution operating in tandem with an actual cm-scale robotic insect and a battery
(or alternative independent energy source) has not yet been demonstrated in the
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literature. Liftoff of the most advanced flapping-wing examples has depended on
externally supplied power [2] [11] [12].
Figure 1-1. ARL Micro-Flyer prototype (from [13], public domain).
Recently, as part of an effort for increased integration, a millimeter-scale
flapping-wing prototype was developed by the US Army Research Laboratory, referred
to as the ARL Micro-Flyer [14] [15] , as shown in Figure 1. Similar in size to a fruit-fly, an
order of magnitude smaller than other examples in the literature, it places extreme size
limitations on the necessary drive electronics [16]. However, facilitated by use of a new
piezo-actuator technology [17] [18], the required drive waveforms are on the order of
10V, not 100V or higher, making direct drive with a single CMOS chip (without external
components) a more practical challenge. Example waveforms, sinusoidal for stroke
actuation and band-limited square-wave for pitch actuation, are presented in Figure 2.
The development of suitable drive electronics for this prototype, using low-voltage
CMOS, serves as the motivation for the circuit techniques presented in this dissertation
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[19]. A secondary but similar application will also be addressed by the same circuit
topologies – efficiently driving a piezo-based MEMS electric-field sensor [20].
Figure 1-2. Required drive waveforms for the ARL Micro-Flyer prototype.
1.2 Research Goals
The overall goal of this work is to develop novel circuit and system-level
techniques for increased voltage handling on chip (3x the device rating) and prolonged
battery life with driven capacitive loads, particularly with the ARL Micro-Flyer and similar
10V Lead Zirconate Titanate (PZT) actuators. These techniques will be demonstrated in
a 0.13μm 1.2V/3.3V CMOS process with isolated NMOS devices (triple-well), primarily
targeting fully-integrated solutions that do not require off-chip components other than a
power source. An overview of system-level specifications and the circuit design
methods investigated, for both the Micro-Flyer and the E-field sensor applications, are
provided in the following paragraphs. A simplified model of the piezo-actuator,
applicable to the Micro-Flyer and also the E-field sensor, is shown in Figure 3. In either
case, the effective load capacitance CACT is in the 1-10 nF range overall and is a non-
VDRV
0V
10V
0V
10V
IDRV0μA IDRV
1mA80μA
-80μA -1mA
VDRV
Sinusoidal
(Stroke)Square-wave
(Pitch)
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linear function of the drive voltage VDRV. The effective resistance RACT is extremely high
(GΩ), and the additional RLC legs, in gray, represent resonant modes of the piezo.
Since these resonant modes typically draw negligible peak currents compared to those
flowing in CACT (Rmode is often in the MΩ range) they have little impact on the driver
design direction and are largely ignored hereafter with the exception that the applied
drive signal is typically at the lowest fundamental resonant frequency and real power is
dissipated in the Rmode resistors (and should be considered for efficiency
measurements). As unimorph piezo-actuators (opposed to a bimorph [4]), the required
drive signal voltage must vary but remain of one polarity only, implying that a DC bias is
necessary. Both sinusoidal and band-limited (or slew-rate limited) waveforms are
needed, depending on the application and/or wing flapping mode, making the load
current quite signal dependent due its capacitive nature (I=C dv/dt). These load currents
are bidirectional, flowing in and out of CL as shown in Figure 1-2 for the Micro-Flyer,
even though the voltage polarity is always positive.
Figure 1-3. Simplified piezo-actuator load model.
In order to maintain compatibility with the Micro-Flyer several system and circuit
level specifications must be met. The electronics should be fully-integrated, output 0-
500Hz waveforms with peak voltages of ~10V and drive capacitive piezo-actuators in
VDRV
CACT RACT
Cmode1
Lmode1
Rmode1
C(VDRV)
Cmode2
Lmode2
Rmode2
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the 1-5 nF range with zero external parts other than a carefully chosen 3-4V battery [21]
[22]. Peak load currents, considering CL and 500 Hz operation, are on the order of 80
μA for sinusoidal drive but can be much higher for band-limited square waves (1mA or
more). A low-voltage CMOS process is strongly preferred since, in the final envisioned
system, a digital “brain” must be included as part of a single chip solution and an
increased density of logic gates would be very beneficial for enhancing the capability of
the robotic insect. As a balance between the competing goals of voltage handling and
logic-density, the 0.13μm 1.2V/3.3V triple-well CMOS process (featuring a ~10V N-well
to P-substrate reverse breakdown voltage) was chosen. For simplicity a 3.3V battery is
assumed for operation. Inductor based approaches are largely ruled out by the
requirements because suitable valued inductors are not typically compatible with
standard process flows [23]. Thus, a switched-capacitor (SC) approach is investigated
for the creation of the ~10V drive signals.
For the secondary application, the PZT-based E-field sensor, the required drive
voltages are lower, on the order of 3V, and are directly compatible with both the battery
and the CMOS rated voltage. However, the capacitance is at the upper end of the
specified range (8-10 nF), and the frequency of operation is approximately 10k-20k Hz,
making the peak currents nearly 25x higher than in the Micro-Flyer for sinusoidal drive.
These large currents originate from the battery when charging the load and, with
standard driver topologies, are directed to ground from the load during discharge [24]. A
comparatively large amount of energy each cycle is then ultimately expended as heat in
the power devices of the driver (1.7mW average for 8nF at 20kHz with 3.3V drive).
Recovery and reuse of this energy, even if only partial, could have significant impact on
22
battery life. Thus, enabling such energy recycling methods is an important topic
considered in this work, for both applications but especially the E-Field sensor driver.
Keeping in line with the research direction and for compatibility between both
applications, inductors are considered prohibited in all cases. While implementing such
a recycling scheme with a completely integrated solution is extremely challenging (due
to the large cost in area associated with integrated capacitors), easing the design
constraints for the sensor driver is the acceptance of external capacitors that can be
packaged with the main IC using specialized MEMS techniques [25] [26] [27]. Table 1
provides a summary of these specifications.
Table 1-1. Specification summary
Accomplishment of the overall design objectives is partitioned into two key tasks.
First is the design of a high-voltage "driver" circuit, responsible for the safe creation and
processing of a 0-9.9V waveform derived from a low-voltage 0-3.3V waveform, without
the need for external components and capable of driving the bidirectional load current.
For this task, illustrated in Figure 4, the low-voltage 0-3.3V signal is assumed to
originate from a circuit with low drive resistance to deliver input current IIN, provided
initially in the form of external lab equipment. VCLK represents the reference clock for the
ARL Micro-Flyer PZT-Based E-Field Sensor
CPZT 1 nF - 5 nF 8 nF – 10 nF
Frequency Range DC – 500 Hz 10 kHz – 20 kHz
Max. Peak Drive Current
SINUSOIDAL
SQUAREWAVE
80μA
2.1 mA
1.2 mA N/A
Voltage Range 0 – 10V 0 – 3.3V
Ext. Components? NONE Yes, capacitors only
23
internal SC blocks, which operate at a much higher frequency than the VIN drive signal.
The key challenge is enabling the necessary voltage handling capability safely on chip,
within the 1.2V/3.3V process and with symmetrical bidirectional load currents, while also
minimizing unnecessary current draw from the power source.
Figure 1-4. Task 1 – Design of 1:3 step-up driver.
The second task is that of replacing the external laboratory circuitry that provides
IIN, or at least its non-trivial features, with an on-chip implementation as shown in Figure
1-5. This circuit exhibiting the necessary low effective drive resistance will be referred to
as a "pre-driver" and must feed the subsequent step-up drive circuitry in a current-
efficient manner: static bias currents should be as small as possible and negligible when
compared to the magnitude of the bidirectional IIN. In essence, the circuit operates as an
efficient voltage buffer. VREF is a reference voltage signal, originating from low-power
circuitry, which the pre-driver output should follow, thus creating VIN for the step-up
VOUT
0V
10V
1:3
Step-up
Driver
VOUT
VIN0V
3.3V
VDD=3.3V
CLK0V
3.3V
20kHz to 10MHz
50 to 500Hz 0.13 μm CMOS
VIN
VCLK
CACT
IDRV
fOUT = fIN
fCLK:
fIN:
IIN
VDRV
24
driver. It should be emphasized that this second task represents a low voltage problem:
all signals remain at or below the supply voltage. If inductors were compatible with
system requirements, then a solution using class-D techniques [28] would be directly
applicable. Here, to remain compatible with the Micro-Flyer requirements, the use of
inductors is prohibited and alternative means are investigated to improve efficiency.
Figure 1-5. Task 2 – Efficient “pre-drive” of the step-up driver.
The high-voltage driver presents a large effective capacitive load CEFF to the pre-
driver (the ratio of VIN and IIN is strongly capacitive, a multiple of the load capacitance).
The primary challenges for this second task are ensuring system stability from a
feedback perspective, because of large CEFF, while also limiting the average current
draw from the 3.3V battery (IBAT) and providing the necessary signal swing.
The Pre-Driver block will be used directly for meeting the goals of the second
(3.3V) application, the E-Field sensor driver, where CEFF then represents the 8-10 nF
capacitive load itself. As will be shown, a large impact on limiting IBAT can be had by
recovering energy from CEFF as it discharges and recycling this energy in the next drive
1:3
Step-up
Driver
VOUT
VIN
0V
3.3V
VDD=3.3V CLK
0.13 μm CMOS
VREF
VCLK
CACT
IDRV
IIN
VDRV
Pre-Driver
VIN VOUT
CEFF
VREF
(Buffer)
IBAT
25
signal period. If enough energy can be efficiently extracted back from the load, instead
of wasting it, the drive scheme can then potentially “pay for itself” – a net improvement
occurs when the recovered energy is more than the energy used for biasing and for
extending the pre-driver to have rail-to-rail drive.
The central theme of this work, essentially, is the generous but judicious
application of circuit bootstrapping techniques to simultaneously meet voltage and
efficiency requirements at the system-level but with inherently voltage limited devices. In
the literature of circuit design “bootstrapping” is a term with multiple definitions but
typically implies either some form of positive feedback with loop-gain near unity [29] or a
feedforward biasing of specific capacitors which, using a clocked approach, are "lifted"
above or below the biasing voltage (usually the input signal) via a switching mechanism
[30]. As will be presented in the following sections of this dissertation, for the previously
described first task (creation of the high voltage piezo-actuator drive signal), a fully-
integrated switched-capacitor ladder converter (a charge-pump) is implemented. It
converts a 0-3.3V waveform at the input to a 0-9.9V waveform at the output and
employs capacitor-based bootstrapping, or what might be more accurately defined
“pseudo-bootstrapping”, successively at each ladder stage. Stacked level-shifted clock
signals that follow the varying input voltage are created during this process, splitting the
large output voltage into three voltage domains and distributing it safely over several
devices, above both the device rating and battery voltage by a factor of 3 without the
use of resistors. A key feature of this circuit is its ability to drive bidirectional load
currents over the complete voltage range.
26
Bootstrapping is also applied in the second task, that of pre-driving CEFF (~50nF),
where the challenges are the efficient creation of continuous-time waveforms that are
nearly rail-to-rail (0 to 3.3V); handling bidirectional currents over the bandwidth of
interest; minimizing static power due to the pre-driver itself; and enabling the ability to
recover energy from CEFF as it discharges, potentially without external components.
Incidentally, these are the same features needed for compatibility with the 3.3V E-field
sensor, and for this secondary application, the pre-driver can be used independently
without the step-up circuitry (with the additional exception that off-chip capacitors are
tolerable). Specifically, bootstrapping is applied to a push-pull source-follower based
output stage, resulting in near rail-to-rail drive and minimal static bias current while also
ensuring all device oxide voltages remain safely limited. Most importantly, the
architecture is amenable to class G/H efficiency improvement techniques [31] [32] as
well as energy recovery without inductors [24]. Internal node-voltages, however,
routinely operate below the substrate potential in the proposed scheme, and careful
attention to well-bias voltages is critical to avoid latch-up in the triple-well technology.
In summary, this dissertation explores system-level and circuit techniques which,
when combined, should have the capability to meet the strict requirements imposed by
the ARL Micro-Flyer, a 10V PZT-based biomimetic millimeter-scale flapping-wing
robotic insect, or at least make major progress in the right direction. A secondary
application, a piezo-based E-field sensor, is also addressed. Throughout, because of
the application, the use of inductors is considered prohibited. While the proposed circuit
techniques have been developed for the specific application of piezo-actuator drive, the
author believes that they are of a more general nature and applicable to a wide variety
27
of IC designs using low-voltage CMOS technologies, especially for capacitive loads
when drive voltages must exceed both the battery and the rated voltages of individual
CMOS devices.
1.3 Dissertation Organization
This dissertation is organized as follows: Chapter 2 provides a literature review
and an overview of the pertinent topics associated with the proposed design techniques.
Chapter 3 focuses on the custom designed fully-integrated high-voltage bidirectional SC
drive stage (task 1) and supporting measurement results. Chapter 4 presents possible
improvements to the Chapter 3 design with the potential to shrink down the
implementation by an approximate factor of two. In Chapter 5 the design of the low-
voltage rail-to-rail pre-driver circuitry is covered (task 2), including a brief description of
compatible efficiency enhancement schemes. Finally, Chapter 6 presents concluding
remarks and a discussion of future work.
28
CHAPTER 2 LITERATURE REVIEW
2.1 Application Overview: PZT-Based Micro-Robotic Insects
Development efforts for flapping-wing robotic insects have been on-going since
at least the late 1990s [1] with much interest from military organizations for surveillance
and combat applications [33]. More benign uses, such as for agriculture [34], have also
been suggested. Many exciting advancements have taken place thereafter, especially
regarding fabrication techniques, aerodynamics, modeling, and feedback control. For
the most compact examples, cm sized or smaller, piezo actuator based wing structures
have become standard [2] [35], and in 2013 the first successful controlled vertical liftoff
of a cm-scale prototype took place [11] as depicted in Figure 2-1 (from [11]), known as
the Harvard Robo-Fly. However, compared to the immense progress made in terms of
the biologically inspired areas of development (dynamics, structure, control, etc., related
to biomimicry [33] [36] [37]), implementing practical drive and power-conditioning
circuitry with compatible power sources at such small scales has proven to be extremely
difficult. A major hurdle is the high actuation voltage typical of piezo-based wings in the
literature, on the order of 100-300V [3]. Various methods have been investigated for
synthesizing the necessary waveforms by stepping-up and modulating compatible
battery voltages of 3-4V, up to a 100x step-up ratio, using specialized off-chip magnetic
components [38]. In spite of these efforts, at the time of writing this dissertation and as
far as the author is aware, even the most advanced cm-scale flapping-wing robotic
insects in the literature depend on external laboratory power supplies and are
essentially tethered by thin wires to their immediate surroundings (these wires are
visible in the top-right corner of Figure 2-1). For this reason and for increased
29
integration in general, the work presented in this dissertation is focused on creation of
drive-circuitry for millimeter-scale PZT-based prototypes requiring much smaller
actuation voltages (~10V) but allowing zero off-chip components, representing a new
challenge with similar but distinctive requirements. The subsequent sections of this
chapter will provide an overview of relevant drive circuits, potential options and
tradeoffs, and provide support for the chosen design direction.
Figure 2-1. Harvard’s Robo-Fly has ~1.5 cm wings and requires 200V [11] (used with permission).
2.2 Power Conversion Techniques and Choice of SC Converter
The goal of any power converter, regulator, or drive circuit (amplifier or buffer) is
to transfer energy from a power source to the load while also maintaining a desired
input-output relationship, usually in terms of voltage (i.e. a voltage amplifier, voltage
supply, or voltage regulator) or current [39] [40]. An increasingly important secondary
parameter—especially with battery powered and heat limited systems [39] [41] but also
with shifts towards “green” technology [42]–is the efficiency of conversion (η = POUT/PIN).
The literature describes in detail various tradeoffs with particular topologies and
30
implementations for power conversion [43], regulation [44], and amplification [45] [46].
For high power transfer levels, inductor (SI) or transformer based topologies have
historically exhibited the highest efficiencies. SI DC-DC converters [47] and class-D
amplifiers [48], for example, routinely exceed efficiencies of 90% with a wide variety of
load powers. SC step-down DC-DC converters, utilizing a total off-chip capacitance in
the 100 μF range, have recently begun competing with more traditional magnetics
oriented designs [49] demonstrating 92% peak efficiency and above 80% with a 1A
load current.
Figure 2-2. Hybrid-SI-SC converter from [10].
For voltage step-up, inductor based topologies [50] as well as hybrid SI-SC
converters [5] [10] have been successfully demonstrated in low-power architectures
largely compatible with the end application considered in this work except for difficulties
in integration. An example of such a hybrid-converter with integrated capacitors and
switches, but an off-chip MEMS inductor [10] is shown in Figure 2-2 with a max output
voltage of nearly 10V. In addition to the issue of external components, noting the use of
31
(on-chip) diodes in the signal path, the structure is optimal for DC-DC applications with
a load current in one direction only; if applied as a capacitive load driver, the falling
portion of the output waveform is not actively driven (the diodes are off) and is shaped
passively by the load’s time constant resulting in grossly distorted waveforms or
extremely limited bandwidth.
Application of a two-step solution, depicted in Figure 2-3, can circumvent this
problem. First, a unidirectional step-up converter is used, such as the one just
described, to create a static high-voltage (HV) supply rail. Next, this HV rail supplies
power to a dedicated secondary drive circuit for waveform creation and bidirectional
load currents – essentially operating as a step-down converter – as proposed in [51] in
2012. The major drawback with this solution is the difficulty in meeting efficiency
requirements, especially for light-loads. In practice, circuits operating in the HV domain
must carefully distribute the large voltage over several devices and with this distribution
comes added overhead (efficiency, area, etc.). Because both of the two steps have
circuits operating within the HV domain, this cost is incurred twice. A similar recent
example has an SC converter creating the high voltage supply and depends on a pull-
down resistor for the falling portion of the waveform [52]. The alternative two-step
solution proposed in this dissertation has only one step (task 1, as described in Chapter
1) operating in a HV domain and actively drives the load in both directions.
While fully-integrated circuits using on-chip magnetic components for conversion
exist, the corresponding efficiency results have been quite low in standard technologies,
45% for the boost converter in [53] with 1.1V output and 300 mV inputs. Step-down
examples with on-chip inductors [54], which aren’t directly applicable here, have
32
exhibited a comparably improved efficiency at 77% but with load currents nearing 1A.
Due mainly to the extremely high switching frequencies (often >10MHz) necessary for
operation with such small inductances, it is difficult to achieve high efficiency at low
powers as needed in this work. Solutions depending on bond-wire inductors, nominally
of 20 nH [55], have similar drawbacks and are also not desirable here.
Figure 2-3. Two-step solution for bidirectional drive from [51].
For on-chip power conversion the only widely available energy storage element
is the capacitor [23]. Thus, for completely integrated solutions with light loads, as
investigated in this work, a pure switched-capacitor topology is the prime (see Figure 11
in [56]) and possibly the only practical option for energy conversion. In step-up DC-DC
applications with moderate to high conversion ratios, the SC topologies (also known as
charge-pumps [57]) are well established [58] [59] [60]. However, configuring these
architectures for the high-voltage drive of waveforms (above the supply and/or device
rating) with significant AC components is a much lesser explored area in the literature,
especially for capacitive loads larger than several pF (see for example [61]) and when
waveforms must routinely operate from 0V to the maximum output voltage value and
33
back (implying bidirectional load currents over the complete voltage range). It is this
particular region of charge-pump operation that is investigated in this dissertation.
With the design and optimization of the SC implementation being so important for
the end application addressed here, the remainder of this chapter is mostly focused on
the literature concerning the topic, including an overview of the critical tradeoffs and a
summary of the key architectures. Since the proposed SC driver and associated pre-
driver are enabled by the use of custom circuit bootstrapping techniques, a brief review
of such related methods and publications is also provided.
2.3 Fundamental Loss Mechanisms for SC Converters
2.3.1 Capacitor Energy Transfer – An Overview
As a starting point, with a very fundamental view of the capacitor, the primary
tradeoffs associated with capacitor-based converters can be understood [62]. From
circuits and physics texts at the introductory level [63] [64], it is clear that a capacitor of
value C Farads with V Volts across it has a charge magnitude |q|=CV on each plate (but
of opposing polarities) and an energy of E=CV2/2 Joules stored in its electric field.
Because this energy had to come from somewhere, typically a battery or voltage
source, it is important to recall that if an initially empty capacitor then has 1 Joule (J) of
energy transferred to it directly through a wire, the source itself had to provide the 1J but
also expends an additional 1J in the process [65] [66] [67]; a 50% efficient energy
transfer has occurred. The simplest explanation of this loss, and the most practical in
the author's view, is that the energy transfer from the battery to the capacitor must
always take place as the movement of charge through a non-ideal wire with non-zero
resistance RWIRE (and/or switch with resistance RSW) to a capacitor with non-zero
equivalent series resistance (ESR) [68]. The sum of these resistances will be referred to
34
as REFF and (for finite practical values) resistive charging of the capacitor takes place.
As will be demonstrated in the next sub-section of this dissertation, a simple hand
calculation integrating the power dissipation in REFF during the charging process (as the
capacitor voltages rises from 0V to VBAT) shows that the physical value of REFF only
varies the time it takes for the charge transfer to complete, or asymptotically approach
completion based on the time constant τ, but doesn't play a role in the proportion of
overall energy loss [69]. For example, cutting REFF by a factor of 10 has no impact on
the 1:1 loss to transferred energy expenditure, assuming the capacitor is given enough
time to completely charge from 0 to VBAT.1 More academic discussions consider this
energy loss using a general electromagnetic representation instead of lumped element
circuit theory [70] [71], explaining that as REFF shrinks to zero the loss can be viewed as
radiated energy (the wire acts like an antenna), and Maxwell’s equations must be
applied. Thus, this loss isn't avoided even by using a charging path with a 0Ω effective
resistance. How then, as demonstrated in the literature [69], can SC power converters
without inductors have efficiencies well above 90%?
As will be shown, the necessary improvement during charging comes about from
a simple but fundamental observation for the charging process (from voltage source to
capacitor); the ratio of the resistive energy loss vs. the energy actually transferred to the
capacitor, the proportional cost of the transfer, greatly improves if the capacitor has an
initial voltage near that of the final value (in other words, if it experiences smaller ΔVC
[69]). This same relationship allows the efficient step-wise charging of a capacitor [72].
1 A similar calculation is used in the derivation of dynamic power loss for digital CMOS logic [155]: PDYN =
fCLKCLVDD2.
35
On the other hand, for an efficient transfer of energy during discharge from capacitor to
resistive load it is important to minimize the path resistance [62] since an effective
voltage divider circuit emerges. To illustrate the first point, the following sub-sections
analyze simple examples using the fundamentals of circuit theory.2 A more expansive
overview is then left to the literature [23] [62].
Figure 2-4. VBAT charging a capacitor through REFF.
2.3.2 Energy Transfer from Voltage Source to Capacitor (Charging)
Considering the RC circuit shown in Figure 2-4, with the capacitor having an
initial voltage VINIT and the charging event beginning at t=0, from [73]
𝑖(𝑡) =𝑉𝐵𝐴𝑇−𝑉𝐶(𝑡)
𝑅𝐸𝐹𝐹 (2-1)
2 It should be stressed that this fundamental outlook is particularly important, in the author’s opinion,
because even recent examples in the literature describing SC DC-DC converter behavior and related design tradeoffs have provided conflicting views on the topic (as discussed as recently as 2013 in [62] and [156]]). To be clear, the confusion mentioned from the DC-DC standpoint is associated with the seemingly simple capacitor-only architectures. If inductors of a satisfactory quality factor are available, resonant charging [71] of an initially empty capacitor can curtail the fifty-percent energy cost, diminishing it greatly in resonant power converters. Similar efficiency benefits can be had by resonant gate drive [151] and other inductor-capacitor (LC) techniques (such as class E converters [130]). Since inductors are precluded from this work, for application related reasons and to reasonably limit the scope of coverage, these techniques will be not considered here. Also worth mentioning are “simulated” or “active” inductors, often implemented by a gyrator circuit combining feedback amplifiers with capacitors [158], which provide an inductive reactance over a finite frequency range (with effective loop gain) and are well documented in filter designs. These emulations, however, do not possess the energy storage capability of a tangible passive component and applying them to the aforementioned LC techniques will not result in the intended efficiency improvement.
36
𝑣𝐶(𝑡) = 𝑉𝐵𝐴𝑇 − (𝑉𝐵𝐴𝑇 − 𝑉𝐼𝑁𝐼𝑇) ∙ 𝑒−𝑡 𝑅𝐸𝐹𝐹𝐶⁄ (2-2)
𝑃𝑅𝐸𝑆(𝑡) = (𝑉𝐵𝐴𝑇 − 𝑣𝑐(𝑡)) ∙ 𝑖(𝑡) (2-3)
To simplify some of the following equations and emphasize a key relationship, the initial
voltage difference between VBAT and the capacitor, just before the start of the charging
event, will be referred to as ΔVC = VBAT – VINIT. The energy dissipated in REFF during the
charging process is ELOSS, representing the effective energy cost of the transfer, and
can be found by integrating the power dissipated in the resistor over the allotted
charging time tSTOP:
𝐸𝐿𝑂𝑆𝑆 = ∫ (𝑉𝐵𝐴𝑇 − 𝑣𝑐(𝑡)) ∙ 𝑖(𝑡)𝑡𝑆𝑇𝑂𝑃
0𝑑𝑡 (2-4)
= ∫(𝑉𝐵𝐴𝑇 − 𝑉𝐶(𝑡))2
𝑅𝐸𝐹𝐹
𝑡𝑆𝑇𝑂𝑃
0𝑑𝑡
= ∫((𝑉𝐵𝐴𝑇 − 𝑉𝐼𝑁𝐼𝑇)∙𝑒−𝑡 𝑅𝐸𝐹𝐹𝐶⁄ )
2
𝑅𝐸𝐹𝐹
𝑡𝑆𝑇𝑂𝑃
0𝑑𝑡
=(𝑉𝐵𝐴𝑇 − 𝑉𝐼𝑁𝐼𝑇)2
𝑅𝐸𝐹𝐹∙ (
𝑅𝐸𝐹𝐹𝐶
2−
𝑅𝐸𝐹𝐹𝐶
2𝑒
−2∙𝑡𝑆𝑇𝑂𝑃𝑅𝐸𝐹𝐹𝐶 )
=𝐶
2∙ 𝛥𝑉𝐶
2∙ (1 − 𝑒
−2∙𝑡𝑆𝑇𝑂𝑃𝜏 )
Note that, as expected, the actual value of the resistor has largely dropped out of the
equation and doesn't play a role in the overall energy loss except for influencing the
time necessary for a complete charge, as dictated by the time constant τ = REFFC.
Minimizing ΔVC, however, greatly reduces energy loss.3 Assuming that the charging
time tSTOP is longer than several time constants (or equivalently that the capacitor has a
3Peak resistive loss (i
2R) occurs at the start of the charging transient when I(t=0) = ΔVC/REFF and then
decreases thereafter. Regardless of the value of REFF, minimizing ΔVC diminishes this loss.
37
chance to equilibrate [23]), the exponential term can be ignored and charging
considered complete. In this case,
𝐸𝐿𝑂𝑆𝑆 ≅𝐶
2∙ 𝛥𝑉𝐶
2 (2-5).
The energy transferred from the battery to the capacitor during the charging
process, referred to here as ΔEC, is simply equal to the difference of the final and initial
capacitor energies:
∆𝐸𝐶 =𝐶
2∙ (𝑉𝐹𝐼𝑁𝐴𝐿
2 − 𝑉𝐼𝑁𝐼𝑇2) (2-6),
where VFINAL is
𝑉𝐹𝐼𝑁𝐴𝐿 = 𝑉𝐵𝐴𝑇 − 𝛥𝑉𝐶 ∙ 𝑒−𝑡𝑆𝑇𝑂𝑃 𝑅𝐸𝐹𝐹𝐶⁄ (2-7)
If complete charging takes place, VFINAL = VBAT and
∆𝐸𝐶 =𝐶
2∙ (𝑉𝐵𝐴𝑇
2 − 𝑉𝐼𝑁𝐼𝑇2) (2-8)
Thus, for a complete transfer (when charging time t is longer than several time
constants), a straightforward relationship describes the tradeoff between energy lost
and the energy transferred. This energy cost ratio, which ideally would be minimized, is
𝐸𝑅𝐴𝑇𝐼𝑂 =𝐸𝐿𝑂𝑆𝑆
∆𝐸𝐶=
(𝑉𝐵𝐴𝑇 − 𝑉𝐼𝑁𝐼𝑇)
(𝑉𝐵𝐴𝑇 + 𝑉𝐼𝑁𝐼𝑇)=
∆𝑉𝐶
(𝑉𝐵𝐴𝑇 + 𝑉𝐼𝑁𝐼𝑇) (2-9).
The energy efficiency [62] of the transfer during charging ηch is then
𝜂𝑐ℎ =∆𝐸𝐶
∆𝐸𝐶+ 𝐸𝐿𝑂𝑆𝑆=
1
1 + 𝐸𝑅𝐴𝑇𝐼𝑂 =
1
2∙ (1 +
𝑉𝐼𝑁𝐼𝑇
𝑉𝐵𝐴𝑇) (2-10).
The simple relationships in Eq. (2-9) and Eq. (2-10), for the resistive charging of
a capacitor from a voltage source (for a complete charge), support the previously
mentioned assertion: the closer the capacitor's initial voltage is to the final voltage the
lower the proportional energy loss in the transfer. If VINIT is 0V, a brief inspection of Eq.
38
(2-9) supports the 50% efficient transfer (1:1 ERATIO). As an example to illustrate the
improvement, if the capacitor begins at 99% of its final charged value, transferring the
last ΔEC of energy to the capacitor costs 0.005*ΔEC of energy burned in switch or wire
resistance, thus equating to a 1:199 ERATIO instead of 1:1 and a 99.5% efficient transfer.
Efficient DC-DC SC power converters exploit the above transfer relationship by
using nearly full capacitors as energy conduits to the load and only partially discharging
and recharging during each clock cycle once the converter operates in periodic steady-
state [23]. In practice the allotted charging time for an SC converter is a direct function
of the converter’s switching frequency fsw which, for improved regulation or to minimize
dynamic power consumption, may vary greatly during operation. Furthermore, to
balance competing loss mechanisms in the converter or minimize chip area a “short”
nominal switching period may be chosen for normal operation in the periodic steady-
state. For the general DC-DC case it is thus not reasonable to assume that the charging
time is always long enough to neglect the exponential term in Eq. (2-4) or,
consequently, that the capacitor charges completely. On the contrary, many fully
integrated designs deliberately use short relative clock periods [74]. Even in the partial
charging case the energy transfer efficiency can be high as long as the capacitor initial
ΔVC remains small. A general form for the energy cost-to-transfer ratio is
𝐸𝑅𝐴𝑇𝐼𝑂,𝐺𝐸𝑁 =𝐸𝐿𝑂𝑆𝑆
∆𝐸𝐶=
1+𝑒−𝑡𝑆𝑇𝑂𝑃
𝜏
(𝑉𝐵𝐴𝑇+𝑉𝐼𝑁𝐼𝑇)
∆𝑉𝐶 − 𝑒
−𝑡𝑆𝑇𝑂𝑃𝜏
(2-11)
and the efficiency of the charging process is
𝜂𝑐ℎ,𝐺𝐸𝑁 =∆𝐸𝐶
∆𝐸𝐶+ 𝐸𝐿𝑂𝑆𝑆=
1
1 + 𝐸𝑅𝐴𝑇𝐼𝑂 =
1
2∙ [(1 +
𝑉𝐼𝑁𝐼𝑇
𝑉𝐵𝐴𝑇) −
∆𝑉𝐶
𝑉𝐵𝐴𝑇𝑒
−𝑡𝑆𝑇𝑂𝑃𝜏 ] (2-12).
39
For charging events of extremely short duration, Eq. 2-11 simplifies to
𝐸𝑅𝐴𝑇𝐼𝑂,𝑆𝐻𝑂𝑅𝑇 =𝐸𝐿𝑂𝑆𝑆
∆𝐸𝐶≈
∆𝑉𝐶
𝑉𝐼𝑁𝐼𝑇 (2-13)
and the associated energy transfer efficiency for charging is
𝜂𝑐ℎ,𝑆𝐻𝑂𝑅𝑇 =∆𝐸𝐶
∆𝐸𝐶+ 𝐸𝐿𝑂𝑆𝑆≈
1
1 + ∆𝑉𝐶
𝑉𝐼𝑁𝐼𝑇 =
𝑉𝐼𝑁𝐼𝑇
𝑉𝐼𝑁𝐼𝑇 + ∆𝑉𝐶=
𝑉𝐼𝑁𝐼𝑇
𝑉𝐵𝐴𝑇 (2-14).
A brief inspection of Eq. (2-14) reveals that, for short charging events, the efficiency of
the transfer is almost directly equal to how close the capacitor is, percentage-wise, to
being “fully charged”. More information on this topic, in general, can be found in [62] and
a discussion of related waveform shapes, partial vs. complete charging, in [75].
2.3.3 Energy Transfer from Capacitor to Capacitor
It is also prudent, for better comprehension of SC converters and as the basis for
the potential energy recycling schemes proposed for task 2 (the pre-driver), to review
the behavior of capacitor-to-capacitor energy transfer through a resistive path of REFF
Ohms. The schematic associated with such a transfer is provided in Figure 2-5A. Both
C1 and C2 are assumed to have initial voltages before the transfer begins at t=0 with
the closing of the switch. To simplify the analysis, as shown in the intermediate step of
Figure 2-5B, each capacitor can be represented as a static voltage source equal to the
initial value (VINIT1 for C1 and VINIT2 for C2) plus an initially empty capacitor of equal
value in series [76]. Only the voltage across the initially empty device varies during the
analysis and is referred to as ΔVC1 (or ΔVC2) such that the sum of VINIT and ΔVC equal
the total capacitor voltage. The capacitor voltages are a direct function of the only
current i(t) flowing in the circuit (it is a series circuit) and to further speed analysis the
device order can be rearranged as depicted in Figure 2-5C where
40
A
B
C
Figure 2-5. Capacitor-to-capacitor current transfer through REFF. A) Original circuit, B) intermediate equivalent circuit, C) final equivalent circuit.
∆𝑉𝐼𝑁𝐼𝑇 = 𝑉𝐼𝑁𝐼𝑇1 − 𝑉𝐼𝑁𝐼𝑇2 (2-15)
and
𝐶𝐸𝐹𝐹 =𝐶1∙𝐶2
𝐶1+𝐶2= 𝐶1||𝐶2 (2-16).
41
It is then easily identified as a first order circuit with time constant τ=REFFCEFF. At the
instant the switch is closed an initial current flows of value
𝐼𝐼𝑁𝐼𝑇 = ∆𝑉𝐼𝑁𝐼𝑇
𝑅𝐸𝐹𝐹 (2-17)
and the time dependent current is
𝑖(𝑡) = 𝐼𝐼𝑁𝐼𝑇 ∙ 𝑒−𝑡/𝜏 (2-18).
Going back to Figure 2-5B and integrating from t=0 to tSTOP, the assumed end of the
charging time, we find
∆𝑉𝐶1 = −1
𝐶1∙ ∫ 𝐼𝐼𝑁𝐼𝑇 ∙ 𝑒−
𝑡
𝜏𝑡𝑆𝑇𝑂𝑃
0𝑑𝑡 =
𝐼𝐼𝑁𝐼𝑇
𝐶1∙ 𝜏 ∙ (𝑒−(𝑡𝑆𝑇𝑂𝑃/𝜏) − 1) (2-19)
= −𝐼𝐼𝑁𝐼𝑇
𝐶1∙ 𝜏 ∙ (1 − 𝑒−(𝑡𝑆𝑇𝑂𝑃/𝜏))
and similarly (but noting the change in sign)
∆𝑉𝐶2 =𝐼𝐼𝑁𝐼𝑇
𝐶2∙ 𝜏 ∙ (1 − 𝑒−(𝑡𝑆𝑇𝑂𝑃/𝜏)) (2-20).
The power dissipated by the resistor is
𝑃𝑅𝐸𝑆 = 𝑖(𝑡)2 ∙ 𝑅𝐸𝐹𝐹 =∆𝑉𝐼𝑁𝐼𝑇
2
𝑅𝐸𝐹𝐹∙ 𝑒−(2∙𝑡𝑆𝑇𝑂𝑃/𝜏) (2-21)
and by integrating PRES from t=0 to tSTOP the energy lost in the transfer is
𝐸𝐿𝑂𝑆𝑆 =1
2∙ 𝐶𝐸𝐹𝐹 ∙ ∆𝑉𝐼𝑁𝐼𝑇
2 ∙ (1 − 𝑒−(2∙𝑡𝑆𝑇𝑂𝑃/𝜏)) (2-22).
If the capacitors are allowed to equilibrate, i.e. tSTOP is greater than several τ time
constants, then the equation simplifies to
𝐸𝐿𝑂𝑆𝑆 =1
2∙ 𝐶𝐸𝐹𝐹 ∙ ∆𝑉𝐼𝑁𝐼𝑇
2 (2-23).
A key observation from Equations (2-22) and (2-23) is that the loss is in
proportion to the square of the capacitors’ initial voltage difference: a smaller ΔVINIT
42
implies less loss. Similarly, like charging from a voltage source, the value of REFF has no
impact on the overall energy loss except through the charging time constant τ (also
notice the factor of 2 in Eq. (2-22) for the energy loss analysis). If the resistance had
been neglected from the analysis and energy transfer took place by ideal capacitive
charge redistribution only, the energy loss would still be observed but the loss
mechanism left unidentified; this is known as the “two capacitor problem” in the
literature [77] and has also been a source of discussion when considering SC circuit
behavior [78]. Despite the term “capacitor charge-redistribution loss”, the actual loss
mechanism in practice is exclusively the path resistance REFF.
To evaluate the efficiency of the energy transfer, C1 is considered the main
energy source and C2 the target destination. Then, recalling that ΔVC1 is negative when
C2 is charging positively,
∆𝐸𝐶1 =𝐶1
2∙ ((𝑉𝐼𝑁𝐼𝑇1 + ∆𝑉𝐶1)2 − 𝑉𝐼𝑁𝐼𝑇1
2) (2-24)
and
∆𝐸𝐶2 =𝐶2
2∙ ((𝑉𝐼𝑁𝐼𝑇1 + ∆𝑉𝐶2)2 − 𝑉𝐼𝑁𝐼𝑇2
2) (2-25).
Thus, the actual energy transferred to load capacitor C2 from source capacitor C1 is
equal to the difference of the final and initial energy values for C2, which are in turn
related to its final (VFINAL2) and initial (VINIT2) capacitor voltages. More explicitly,
𝑉𝐹𝐼𝑁𝐴𝐿2 = 𝑉𝐼𝑁𝐼𝑇2 + ∆𝑉𝐶2 (2-26).
= 𝑉𝐼𝑁𝐼𝑇2 + ∆𝑉𝐼𝑁𝐼𝑇 ∙𝐶1
𝐶1 + 𝐶2∙ (1 − 𝑒−(𝑡𝑆𝑇𝑂𝑃/𝜏))
Assuming the voltage on C2 has equilibrated, then
𝑉𝐶2,𝐹𝐼𝑁𝐴𝐿 = 𝑉𝐼𝑁𝐼𝑇2 + ∆𝑉𝐼𝑁𝐼𝑇 ∙𝐶1
𝐶1 + 𝐶2 (2-27).
43
The energy transferred to C2 is
∆𝐸𝐶2 = 1
2𝐶2 ∙ 𝑉𝐹𝐼𝑁𝐴𝐿2
2 − 1
2𝐶2 ∙ 𝑉𝐼𝑁𝐼𝑇2
2 (2-28)
= 1
2𝐶2 ∙ (𝑉𝐹𝐼𝑁𝐴𝐿2
2 − 𝑉𝐼𝑁𝐼𝑇22)
= 1
2𝐶2 ∙ (∆𝑉𝐶2
2 + 2 ∙ 𝑉𝐼𝑁𝐼𝑇2 ∙ ∆𝑉𝐶2)
= 1
2𝐶2 ∙ (𝑇𝐸𝑅𝑀1 + 𝑇𝐸𝑅𝑀2)
where,
𝑇𝐸𝑅𝑀1 = ∆𝑉𝐶22 = ∆𝑉𝐼𝑁𝐼𝑇
2 ∙ (𝐶1
𝐶1 + 𝐶2)
2
∙ (1 − 𝑒−(𝑡𝑆𝑇𝑂𝑃/𝜏))2
(2-29)
and
𝑇𝐸𝑅𝑀2 = 2𝑉𝐼𝑁𝐼𝑇2∆𝑉𝐶2 = 2 ∙ 𝑉𝐼𝑁𝐼𝑇2 ∙ ∆𝑉𝐼𝑁𝐼𝑇 ∙𝐶1
𝐶1 + 𝐶2∙ (1 − 𝑒−(𝑡𝑆𝑇𝑂𝑃/𝜏)) (2-30).
A general energy cost ratio ERATIO,GEN can now be defined, similarly to the previous
subsection, which ideally would be minimized,
𝐸𝑅𝐴𝑇𝐼𝑂,𝐺𝐸𝑁 =𝐸𝐿𝑂𝑆𝑆
∆𝐸𝐶2
=𝐶1
𝐶1 + 𝐶2∙
∆𝑉𝐼𝑁𝐼𝑇2∙(1−𝑒−(2∙𝑡𝑆𝑇𝑂𝑃/𝜏))
(𝑇𝐸𝑅𝑀1 + 𝑇𝐸𝑅𝑀2) (2-31)
=(1−𝑒−(2∙𝑡𝑆𝑇𝑂𝑃/𝜏))
(1−𝑒−𝑡𝑆𝑇𝑂𝑃/𝜏)∙
1
((𝐶1
𝐶1 + 𝐶2∙(1−𝑒−𝑡𝑆𝑇𝑂𝑃/𝜏)) +
2𝑉𝐼𝑁𝐼𝑇2
∆𝑉𝐼𝑁𝐼𝑇)
=(1+𝑒−𝑡𝑆𝑇𝑂𝑃/𝜏)
((𝐶1
𝐶1 + 𝐶2∙(1−𝑒−𝑡𝑆𝑇𝑂𝑃/𝜏)) +
2𝑉𝐼𝑁𝐼𝑇2
∆𝑉𝐼𝑁𝐼𝑇)
If tSTOP is much greater than the time constant τ, then complete charging is assumed
and Eq. (2-31) simplifies to
𝐸𝑅𝐴𝑇𝐼𝑂,𝐶𝑂𝑀𝑃𝐿𝐸𝑇𝐸 =1
(𝐶1
𝐶1 + 𝐶2) +
2𝑉𝐼𝑁𝐼𝑇2
∆𝑉𝐼𝑁𝐼𝑇 (2-32).
For very small ΔVINIT values, Eq. (2-32) further simplifies to
44
𝐸𝑅𝐴𝑇𝐼𝑂,𝐶𝑂𝑀𝑃𝐿𝐸𝑇𝐸 ≅∆𝑉𝐼𝑁𝐼𝑇
2𝑉𝐼𝑁𝐼𝑇2 (2-33).
Conversely, if tSTOP/τ is small and only a short partial charging event has taken place,
then the resulting energy cost ratio can be approximated as
𝐸𝑅𝐴𝑇𝐼𝑂,𝑆𝐻𝑂𝑅𝑇 ≈2−
𝑡𝑆𝑇𝑂𝑃
𝜏𝑡𝑆𝑇𝑂𝑃
𝜏∙(
𝐶1
𝐶1 + 𝐶2) +
2𝑉𝐼𝑁𝐼𝑇2
∆𝑉𝐼𝑁𝐼𝑇 (2-34),
using the series expansion for the exponential in Eq. (2-31) and ignoring higher order
terms.
The equations support the assertion that the energy cost ratio can be “low” in
either situation, governed either by Eq. (2-32) or Eq. (2-34), as long as ΔVINIT is small.
Consider, as an example, that C1 = C2, VINIT2 = 0.95V and ΔVINIT = 0.05V (meaning
VINIT1 = 1V). In this case, using Eq. (2-32) the energy cost to transfer ratio is ~1:40 (i.e.,
1 pJ spent for every 40 pJ transferred to the load capacitor). Next, using Eq. (2-34),
assuming the same values for capacitors and initial voltages, and letting tSTOP/τ = 0.2,
then the energy cost to transfer ratio is ~1:20 and still not a bad “deal”. However, noting
the difference in tSTOP values for the two cases and reviewing Eq. (2-28), the actual
energies transferred differ greatly (by ~5x if 1nF capacitors are used, 24 vs. 4.3 pJ).
As in the previous subsection, the energy efficiency of the transfer ηch can be
defined for a single (general) charging event (the capacitor voltages do not fully
equilibrate but tSTOP/τ is not necessary small):
𝜂𝑐ℎ,𝐺𝐸𝑁 =∆𝐸𝐶2
∆𝐸𝐶2+ 𝐸𝐿𝑂𝑆𝑆=
1
1 + 𝐸𝑅𝐴𝑇𝐼𝑂 =
1
1+(1+𝑒−𝑡𝑆𝑇𝑂𝑃/𝜏)
((𝐶1
𝐶1 + 𝐶2∙(1−𝑒−𝑡𝑆𝑇𝑂𝑃/𝜏)) +
2𝑉𝐼𝑁𝐼𝑇2∆𝑉𝐼𝑁𝐼𝑇
)
(2-35).
45
Alternatively, the energy efficiency of the transfer ηch,complete during a single and
complete charging event (the capacitor voltages fully equilibrate with tSTOP >> τ)
simplifies to
𝜂𝑐ℎ,𝑐𝑜𝑚𝑝𝑙𝑒𝑡𝑒 =∆𝐸𝐶2
∆𝐸𝐶2+ 𝐸𝐿𝑂𝑆𝑆=
1
1 + 𝐸𝑅𝐴𝑇𝐼𝑂 =
(𝐶1
𝐶1 + 𝐶2) +
2𝑉𝐼𝑁𝐼𝑇2
∆𝑉𝐼𝑁𝐼𝑇
1+ (𝐶1
𝐶1 + 𝐶2) +
2𝑉𝐼𝑁𝐼𝑇2
∆𝑉𝐼𝑁𝐼𝑇
(2-36).
As a quick sanity check, with VINIT1 = 1V, with VINIT2 = 0V and thus C2 initially empty of
charge, and with C1 = C2, after a complete charging event the capacitor voltages would
be equal at 0.5V and the energy transfer would have taken place with 33.3% efficiency.
However, with VINIT2 = 0.5V (for a ΔVINIT of 0.5V) and all other conditions the same, the
energy is transferred with 71% efficiency.
Figure 2-6A provides plots of Equations (2-22) and (2-28), for ELOSS and ΔEC2,
respectively, while Figure 2-6B contains plots for Equations (2-31) and (2-35), for ERATIO
and ηch, respectively. C1 and C2 are set to 1nF each, path resistance REFF = 1kΩ, and
VINIT1 = 1V. VINIT2 is swept from 0 to 0.99V such that ΔVINIT ranges from large values
(including starting from a completely discharged state) to very small values. With tSTOP/τ
= 20, the plot shows the result of complete charging events. To confirm the accuracy of
the derived equations, the black dots on each curve show corresponding output values
from SPICE transient simulations using ideal passives; initial conditions were applied to
set the capacitor voltages.
46
A
B
Figure 2-6. Supporting plots for Equations (2-22) through (2-35) for complete charging. A) ΔEC2 and ELOSS vs. ΔVINIT and B) ηCH,GEN and ERATIO,GEN vs. ΔVINIT.
For practical but vanishingly small ΔVINIT values, transfer efficiencies of well over
95% are possible. However, the energy transferred during each event becomes
increasingly small as well. Because switched-capacitor converters operate cycle-by-
cycle with many such events, this explains how switched capacitor DC-DC converters
can be extremely efficient but primarily with relatively light-loads (small relative load
currents). Using large capacitors improves efficiency: for the same amount of
transferred charge per cycle or event, ΔVINIT can be minimized.
47
Additionally, ignoring dynamic switching losses, it is better to transfer many small
charge packets in a given amount of time rather than large packets once in a while:
ΔVINIT for each event is minimized and efficiency is increased. This explains why
switched-capacitor converter drive strength and efficiency improve with higher clock
frequencies (in terms of conduction loss), at least until equilibrated capacitor charging
no longer takes place or further dynamic loss is prohibitive.
A
B
Figure 2-7. Supporting plots for Equations (2-22) through (2-35) for partial charging. A) ΔEC2 and ELOSS vs. ΔVINIT and B) ηCH,GEN and ERATIO,GEN vs. ΔVINIT.
48
Figure 2-7 is comparatively the same as Figure 2-6 but for a very short charging
event: tSTOP/τ = 0.2. In contrast to the complete charging situation, the “Energy” plots of
Figure 2-7A show a large decrease in energy transferred ΔEC2 for a given ΔVINIT value.
However, as shown in Figure 2-7B, even though the ERATIO is 10x higher for large ΔVINIT
values, it drops quickly as ΔVINIT decreases. Thus, energy transfer efficiency can be
high (above 95%, for example) for the short charging case but there is an increasingly
limited amount of energy transferred per charging event.
2.3.4 Energy Transfer from Capacitor to Current-Source Load
Energy transfer from a storage capacitor to an effective current-source load,
depicted in Figure 2-8, can be extremely efficient and is commonplace in integrated
circuits, especially those using RFID or similar techniques for system power [79] [80].
Figure 2-8. Initially charged capacitor transferring energy to a current-source load.
Assuming a transfer duration from t=0 to t=tSTOP and initial capacitor voltage VINIT,
the associated equations are derived as follows. The capacitor is discharged linearly
from the current source and thus the voltage drop on the capacitor over the discharge
time is
∆𝑉𝐶 =𝐼𝐿𝑂𝐴𝐷
𝐶𝐻∙ 𝑡𝑆𝑇𝑂𝑃 (2-37)
with the final capacitor voltage equal to
𝑉𝐹𝐼𝑁𝐴𝐿 = 𝑉𝐼𝑁𝐼𝑇 − ∆𝑉𝐶 = 𝑉𝐼𝑁𝐼𝑇 − 𝐼𝐿𝑂𝐴𝐷
𝐶𝐻∙ 𝑡𝑆𝑇𝑂𝑃 (2-38).
49
Accounting for the voltage drop on path resistance REFF, the initial load and final load
voltages are, respectively,
𝑉𝐿𝑂𝐴𝐷,𝐼𝑁𝐼𝑇 = 𝑉𝐼𝑁𝐼𝑇 − 𝑅𝐸𝐹𝐹 ∙ 𝐼𝐿𝑂𝐴𝐷 (2-39)
and
𝑉𝐿𝑂𝐴𝐷,𝐹𝐼𝑁𝐴𝐿 = 𝑉𝐹𝐼𝑁𝐴𝐿 − 𝑅𝐸𝐹𝐹 ∙ 𝐼𝐿𝑂𝐴𝐷 = (𝑉𝐼𝑁𝐼𝑇 − 𝐼𝐿𝑂𝐴𝐷
𝐶𝐻∙ 𝑡𝑆𝑇𝑂𝑃) − 𝑅𝐸𝐹𝐹 ∙ 𝐼𝐿𝑂𝐴𝐷 (2-40).
Average load power is the product of the average load voltage and ILOAD:
𝑃𝐿𝑂𝐴𝐷,𝐴𝑉𝐺 = (𝑉𝐿𝑂𝐴𝐷,𝐼𝑁𝐼𝑇 + 𝑉𝐿𝑂𝐴𝐷,𝐹𝐼𝑁𝐴𝐿
2) ∙ 𝐼𝐿𝑂𝐴𝐷 (2-41)
or, more specifically,
𝑃𝐿𝑂𝐴𝐷,𝐴𝑉𝐺 = (𝑉𝐼𝑁𝐼𝑇− 𝑅𝐸𝐹𝐹∙𝐼𝐿𝑂𝐴𝐷+ (𝑉𝐼𝑁𝐼𝑇−
𝐼𝐿𝑂𝐴𝐷𝐶𝐻
∙𝑡𝑆𝑇𝑂𝑃)− 𝑅𝐸𝐹𝐹∙𝐼𝐿𝑂𝐴𝐷
2) ∙ 𝐼𝐿𝑂𝐴𝐷 (2-42)
= (𝑉𝐼𝑁𝐼𝑇 − 𝑅𝐸𝐹𝐹 ∙ 𝐼𝐿𝑂𝐴𝐷 + (− 𝐼𝐿𝑂𝐴𝐷
2𝐶𝐻∙ 𝑡𝑆𝑇𝑂𝑃) ) ∙ 𝐼𝐿𝑂𝐴𝐷
= 𝑉𝐼𝑁𝐼𝑇 ∙ 𝐼𝐿𝑂𝐴𝐷 − 𝑅𝐸𝐹𝐹 ∙ 𝐼𝐿𝑂𝐴𝐷2 −
𝐼𝐿𝑂𝐴𝐷2
2𝐶𝐻∙ 𝑡𝑆𝑇𝑂𝑃
Thus, the total energy transferred to the load is
𝐸𝐿𝑂𝐴𝐷 = 𝑃𝐿𝑂𝐴𝐷,𝐴𝑉𝐺 ∙ 𝑡𝑆𝑇𝑂𝑃 (2-43)
= 𝑡𝑆𝑇𝑂𝑃 ∙ (𝑉𝐼𝑁𝐼𝑇 ∙ 𝐼𝐿𝑂𝐴𝐷 − 𝑅𝐸𝐹𝐹 ∙ 𝐼𝐿𝑂𝐴𝐷2 −
𝐼𝐿𝑂𝐴𝐷2
2𝐶𝐻∙ 𝑡𝑆𝑇𝑂𝑃)
= 𝑡𝑆𝑇𝑂𝑃 ∙ 𝐼𝐿𝑂𝐴𝐷 ∙ (𝑉𝐼𝑁𝐼𝑇 − 𝑅𝐸𝐹𝐹 ∙ 𝐼𝐿𝑂𝐴𝐷 − 𝐼𝐿𝑂𝐴𝐷
2𝐶𝐻∙ 𝑡𝑆𝑇𝑂𝑃)
The energy lost through REFF is simply
𝐸𝐿𝑂𝑆𝑆 = 𝑅𝐸𝐹𝐹 ∙ 𝐼𝐿𝑂𝐴𝐷2 ∙ 𝑡𝑆𝑇𝑂𝑃 (2-44).
During the same time duration, the total energy removed from the capacitor ΔEC is
equal to the difference between its initial and final energies, which is a function of its
initial and final voltages:
50
∆𝐸𝐶 =𝐶𝐻
2∙ (𝑉𝐼𝑁𝐼𝑇
2 − 𝑉𝐹𝐼𝑁𝐴𝐿2) (2-45)
or, more specifically,
∆𝐸𝐶 =𝐶𝐻
2∙ [(2𝑉𝐼𝑁𝐼𝑇) − (
𝐼𝐿𝑂𝐴𝐷
𝐶𝐻∙ 𝑡𝑆𝑇𝑂𝑃)] ∙ (
𝐼𝐿𝑂𝐴𝐷
𝐶𝐻∙ 𝑡𝑆𝑇𝑂𝑃) (2-46)
=1
2∙ [(2𝑉𝐼𝑁𝐼𝑇) − (
𝐼𝐿𝑂𝐴𝐷
𝐶𝐻∙ 𝑡𝑆𝑇𝑂𝑃)] ∙ (𝐼𝐿𝑂𝐴𝐷 ∙ 𝑡𝑆𝑇𝑂𝑃)
The corresponding energy cost to transfer ratio is then
𝐸𝑅𝐴𝑇𝐼𝑂 =𝐸𝐿𝑂𝑆𝑆
∆𝐸𝐶
= 2∙𝑅𝐸𝐹𝐹∙𝐼𝐿𝑂𝐴𝐷
[2∙𝑉𝐼𝑁𝐼𝑇− (𝐼𝐿𝑂𝐴𝐷
𝐶𝐻∙𝑡𝑆𝑇𝑂𝑃)]
(2-47)
and the efficiency of energy transfer is
𝜂𝑡𝑟𝑎𝑛𝑠 =∆𝐸𝐶
∆𝐸𝐶+ 𝐸𝐿𝑂𝑆𝑆=
1
1 + 𝐸𝑅𝐴𝑇𝐼𝑂 =
1
1+2∙𝑅𝐸𝐹𝐹∙𝐼𝐿𝑂𝐴𝐷
[2∙𝑉𝐼𝑁𝐼𝑇− (𝐼𝐿𝑂𝐴𝐷
𝐶𝐻∙𝑡𝑆𝑇𝑂𝑃)]
(2-48).
A key observation of Equations (2-47) and (2-48) is that, unlike for resistive
charging, if REFF is made negligibly small the capacitor’s energy can be transferred to
the current source load with an efficiency approaching 100%. Of course, for an SC
converter in periodic steady-state, any capacitor energy delivered to the ILOAD source in
one converter phase must be replenished in a subsequent recharging phase, normally
by resistive charging with the previously described tradeoffs. Current source charging of
a capacitor, and the associated benefits, is discussed in [23].
2.3.5 Energy Transfer from Capacitor to ZL
To further build understanding of SC related transfer loss mechanisms, analysis
of energy transfer taking place between an initially charged capacitor and a load
impedance is also important. To limit the scope of this overview the interested reader
should consult [62].
51
2.3.6 Conduction Loss and Explanation of ROUT
Consideration of the two situations governing the equations in Sections 2.3.1 to
2.3.3, namely complete vs. partial charging per energy transfer event (or per half-
switching cycle in an overall SC converter), helps to explain the basis for two different
asymptotic operation regimes for SC DC-DC converters in periodic steady-state [23] –
the slow-switching limit (SSL) when capacitors are allowed to fully equilibrate and the
fast-switching limit (FSL) when the switch resistances completely dominant the charge
transfer operation (basically by influencing tSTOP/τ in consequent charging events).
These regimes are characterized by differing expressions for effective converter output
resistance ROUT.
For instance, assume an SC converter reaches steady-state operation at a very
low switching frequency and with a (relatively light) current-source load. The converter
then effectively operates in the SSL: for the same load current, an increase in the
switching frequency allows more charge “packets”, of proportionally smaller size, to
move from one capacitor to another in a given amount of time. The capacitor voltage
excursions, which are in direct proportion to charge moved, are also smaller per cycle;
the decreasing ΔVINIT values result in increased efficiency for associated transfer events
(see Eq. (2-35), for example). Switch resistances have essentially no effect in this
regime. As long as complete charging can be assumed for each cycle, by definition for
the SSL equation to be valid [23]), doubling the clock frequency improves the drive
capability of the converter4 also by 2x, resulting in decreased (halved) ROUT.
4In terms of conduction loss, more total charge QTOT can be moved per second (higher current) with
converter efficiency held constant. Alternatively, efficiency can improve with current held constant.
52
This rate of improvement with increasing clock frequency cannot continue
indefinitely: eventually the assumption of complete charging events no longer holds and
switch resistances must be considered. In the extreme case, the FSL is reached.
Operation in FSL is characterized by charge transfer each clock cycle being fully limited
by the path resistance, resulting in equal but opposite partial charging events and quasi-
static capacitor voltages. While a further frequency increase implies more packets are
delivered per cycle to subsequent capacitors, each of these packets is smaller, the ΔV
for each event is no longer appreciably improving, and drive strength (characterized by
ROUT) is essentially constant. Operation much above the approximate SSL to FSL
transition frequency fZ is fruitless [56], having little impact on drive capability and a
detrimental effect on overall converter efficiency due to large dynamic switching losses
in practical MOS switches, which are proportional to switching frequency. In practice,
the operating conditions of a converter are usually set somewhere between these two
asymptotic regions, optimally at fZ, and neither of the equations governing SSL or FSL
operation perfectly describes converter behavior. For a converter that optimizes
tradeoffs to minimize a given “cost” metric (chip area, power dissipation, etc.) while
simultaneously meeting drive requirements, usually specified in terms of output
resistance ROUT, operation near or at this transition frequency is typical [81]. In [23] an
overview of the charge-multiplier vector design method for SC DC-DC converters is
presented that includes a quantitative view of the drive strength (ROUT) versus fSW
relationship for DC-DC converters. It is shown that the topological structure of the
converter, switching frequency, along with capacitor and MOS switch sizes, must all be
considered simultaneously for an optimal design. With a resistor and/or current source
53
loaded SC DC-DC converter, an output hold capacitance CHOLD has large impact on
ripple voltage and can be made arbitrarily large in theory. If large enough, ROUT perfectly
models the voltage drop due to Thevenin resistance of the ideal converter – an increase
in current implies an increased loss. Note, however, that while REFF (as defined in the
previous sub-sections) plays a role in defining ROUT these are two separate but related
quantities.
2.3.7 Pedagogical Example: (Pseudo) Four-Phase Series-Parallel SC Converter
Sub-sections 2.3.1 through 2.3.5 of this dissertation described fundamental SC
power converter behavior through the use of simplified equivalent circuits and by
deriving equations that represent energy transfer tradeoffs. Section 2.3.6 provided a
qualitative overview of ROUT and two asymptotic regions of converter operation, the SSL
and FSL, as a function of fSW and with respect to these equivalent circuits. To further
illustrate key concepts in a more specific manner, this sub-section presents a four-
phase SC Voltage Doubler example created for pedagogical purposes, a simple series-
parallel topology as shown in Figure 2-9.
Associated clock waveforms are provided in Figure 2-9A and the circuit
arrangement itself in Figure 2-9B. TPER is the overall clock period ( = fSW-1), tON is the
“on” time for each of the phases, which are labeled Φ1 - Φ4, and tNON is the non-
overlapping time. Most switches in the schematic are active for more than one phase:
switches labeled Φ14 are active for both Φ1 and Φ4, those labeled Φ23 are active for both
Φ2 and Φ3, etc. This convention is used similarly throughout.
54
A
B
C
D
Figure 2-9. Example 4-phase series-parallel voltage doubler. A) Clock waveforms, B) circuit schematic, C) equivalent circuit for Φ1, and D) equivalent circuit for Φ2.
The example is essentially a two-phase circuit in disguise, designed so that the
sub-circuit of each charging or discharging event can be described exactly by Eq. (2-12)
55
for voltage-source charging, by Eq. (2-35) for capacitor-to-capacitor charging, or by Eq.
(2-48) for current-source loading of a capacitor. Associated equivalent circuits are
provided in Figure 2-9C and 2-9D for odd and even phases, respectively. In phase Φ1,
flying capacitors CF1 and CF2 are each (re)charged to the battery voltage VBAT through
effective path resistance REFF1, hold capacitor CH1 feeds the current source load (of
value ILOAD amps) through a negligibly small resistance R, and hold capacitor CH2 is idle
(retaining its voltage from a previous phase without accounting for leakage).
Approximate steady-state voltages are noted in the schematic. In phase Φ2, the
VBAT source is left idle, CF1 and CF2 are stacked (having equivalent capacitance CSTACK)
to recharge CH1 through resistance REFF2 (to a voltage of approximately 2∙VBAT), and CH2
feeds the load. The sub-circuits of phase Φ3 are identical to those of Φ1, as are those of
phases Φ4 and Φ2, except that CH1 and CH2 exchange roles: signifying that this is
fundamentally a two phase circuit operating at 2∙fSW. Capacitor CX is a small capacitor
whose role is to hold VLOAD during the non-overlapping time; this capacitor’s impact on
behavior will be ignored in the following discussion. 5
To help clarify the nature of the example, Figure 2-10 displays the results of a
series of transient SPICE simulations using ideal capacitors and switches (with on/off
resistances) in periodic steady-state operation. VBAT = 1V, capacitor CH1 = CH2 = 100nF,
and capacitor CF1 = CF2 = 10nF. Switch resistances, which sum to form the REFF1 and
REFF2 values, are chosen so that the time-constants for each local charging/discharging
event are equal and (arbitrarily) set to τ=5ns (tNON is sufficiently short to be neglected).
5 The pedagogical nature of this example is apparent – idle components represent a sub-optimum design.
An improved implementation would remove CF1 and stack CF2 directly on VBAT in Φ2; also CH2 could remain connected to the load at all times and a direct two-phase scheme utilized.
56
Then, REFF1 is thus τ/CF1 = 0.5Ω, CSTACK = CF1/2 = 5nF, the effective capacitance of
CSTACK in series with CH1 is CEFF2 ≈ 4.8nF, and thus REFF2 = τ/CEFF2 ≈ 1Ω.
A
B
C
D
Figure 2-10. Charging event waveforms with time axis normalized to TPER. A) CF1 current, B) CF1 voltage, C) CH1 charging current, and D) CH1 Voltage (~VOUT).
Each column in Figure 2-10 is the result of a unique simulation for a given fSW
value (between 4MHz and 128MHz). Furthermore, overlaid in each subplot are results
for three ILOAD values: ~0mA, 5mA, and 10mA (green, blue, and red, respectively).
Figure 2-10A shows the current through flying capacitor CF1, with corresponding
57
capacitor voltage in Figure 2-10B. Figure 2-10C shows the related current through hold
capacitor CH1, for charging events only (namely the capacitor-to-capacitor charging
event between CSTACK and CH1 through REFF2). To simplify comparison of currents, the
plot of Figure 2-10C has been scaled by -1.
Finally, Figure 2-10D presents the voltage across CH1 which is also a proxy for
the load voltage VLOAD (they are very nearly equal). The time axis for all plots is
normalized to the overall switching period TPER. However, only one half-period is
actually shown since the charging events in the second half are effectively identical (but
take place via CH2 instead of CH1). Each row of the plot is meant to be read from left-to-
right, highlighting changes in waveform shape as the switching period decreases or,
equivalently, tSTOP/τ for each event becomes increasingly shorter. Thus, the events
move from complete charging to very short partial charging in the extreme case. It can
be seen in Figure 2-10D that VLOAD is ~2V when unloaded (when ILOAD ≈ 0 mA). This
load voltage, in green, is essentially constant for all fSW values. However, the finite
output resistance ROUT of the converter is apparent when considering the ILOAD = 5mA
and = 10mA cases. Particularly, there is a substantial voltage drop VD when the current
flows: for fSW = 4MHz this voltage drop VD,4MHz is ~130 mV for a 5mA load. Simulated
ROUT at 4MHz is then VD,4MHz / 5mA = 26Ω. When fSW is doubled to 8MHz, the voltage
drop is halved (VD,8MHz is ~ 65 mV), indicating a corresponding halving of ROUT for 13Ω,
as predicted by the SSL ROUT equation [23] associated with complete charging events.
Improved ROUT (and thus conversion efficiency) is largely explained by decreasing
voltage excursions ΔV on the flying capacitors (labeled in Figure 2-10B for VCF1) when
complete charging takes place and fSW is increased.
58
After again doubling fSW, at 16MHz, nearly complete charging still appears to take
place along with a significant improvement in ROUT: nearly another halving of VD (not
labeled) is observed. However, increases beyond this frequency, see the 32MHz
through 128MHz columns, result in diminishing improvements with increasingly short
partial charging events and ΔV excursions which never result in a complete charge or
discharge. Values for VD are then essentially static for a given ILOAD, regardless of
increases in fSW, indicating that ROUT has nearly hit its “fast-switching limit” (FSL) value
set by the path resistances [23]. In the extreme case, at 128 MHz and above, the
exponential nature of each charging event is no longer evident, capacitor voltages
between phases are changing less and less (asymptotically becoming effective DC
sources) and the charging currents also become increasingly constant over the duration
of each sub-cycle.
These observations are supported graphically in Figure 2-11, showing a plot of
simulated ROUT vs. fSW in Figure 2-11A and the ratio of tSTOP/τ in Figure 2-11B. ROUT is
inversely proportional to fSW at lower frequencies (supporting the SSL concept) when
complete charging takes place. Once the charging events are shorter than ~3∙τ, the
gray region in Figure 2-11B starting at ~16MHz, only increasingly shorter partial
charging events take place and ROUT asymptotically approaches the FSL value (of ~4Ω)
as set by path (switch) resistances. When simulating with 25% smaller flying capacitors
(CF1 = CF2) but unchanged resistances, the resulting dashed ROUT curve shows higher
59
associated values of ROUT at low frequencies (curve is shifted to the right compared with
the original) but ultimately approaches the same FSL ROUT value at high fSW6.
A
B
Figure 2-11. Simulation results summarized. A) ROUT vs. fSW and B) normalized event duration vs. fSW.
The individual equivalent circuits for charging/discharging events were shown in
Figure 2-9C and 2-9D. To tie together the behavior of these individual events with
overall collective converter performance, Figure 2-12 shows several related plots
6 The event duration plot of Figure 2-11B corresponds to the main curve only, not the dotted portion with
smaller flying capacitors.
60
extracted from the SPICE simulation for ILOAD = 5mA, all with respect to fSW. Figure 2-
12A includes the individual energy loss contributions for each clock cycle dissipated in
REFF1 (only one of two instances is plotted) and REFF2, called ELOSS,REFF1 and ELOSS,REF2,
respectively. Also included are the total energy loss ELOSS,TOTAL (= 2∙ELOSS,REFF1 +
ELOSS,REF2) and ELOAD, the energy getting to the load per cycle. A corresponding plot of
the total loss to transfer ratio (ELOSS,TOTAL / ELOAD), labeled ERATIO,TOT, is provided in
Figure 2-12B, along with overall efficiency of the transfer ηTOT.
A
C
B D
Figure 2-12. Extracted quantities from simulation. A) Event energy, B) efficiency and total energy loss:transfer ratio, C) power, and D) ROUT extracted from power.
61
Plotted efficiency ηTOT is calculated from the energies but (due to periodic steady-
state operation) is equivalent to PLOAD/PIN, where PIN = PLOAD + PLOSS is the power from
the VBAT source. These corresponding powers are shown in Figure 2-12C. As fSW rises,
and associated ROUT falls, PLOAD approaches the ideal 2V∙5mA = 10mW level. Similarly,
PLOSS drops quickly in the complete-charging (SSL) region but tends asymptotically
towards a finite value for partial charging at high fSW, in this case ~0.1 mW. The original
plot of ROUT in Figure 2-11 was extracted from the simulated output voltage drop.
Knowing ILOAD = 5mA, ROUT can be equivalently extracted from PLOSS which, in turn, is
the sum of the individual energy losses (ELOSS,TOTAL) scaled by fSW. For comparison,
Figure 2-12D presents an essentially identical picture of ROUT vs. fSW using the second
method. As a specific example, when approaching the SSL limit at 256 MHz, ELOSS,TOTAL
= 0.4 pJ for a PLOSS of 102.4 μW. Calculated ROUT is then PLOSS/ILOAD2 ≈ 4Ω, as
expected. Thus, all necessary conduction losses are contained in the REFF path
resistances for each event and overall converter behavior, characterized by ROUT, can
be understood at a fundamental level using simple equivalent circuits [62].
2.3.8 Comments on Dynamic Models for SC Power Converters
As part of this literature review a brief selection of publications discussing SC
DC-DC theory has been referenced. Beyond this, the dynamic behavior of DC-DC
converters (start-up, response to load transients, etc.) has been a topic of growing
coverage [82] [83] [84]. However, in terms of theory or qualitative description of design
tradeoffs, no single resource has provided the author’s desired transparency for
extending the DC-DC analysis to include use of the SC power converters for signal
62
amplification having a dominant AC component, as is relevant for this work, including a
proper assessment of energy transfer and efficiency7. No attempt to address this
apparent short-coming is made in this work. Alternatively, SPICE simulation, as
opposed to theoretical analysis, will be the primary tool for assessing design decisions.
2.4 Charge-Pump and SC Power Converter Architectures
Many architectures and implementations of charge-pumps (sometimes also
called voltage multipliers) exist with various levels of complexity and performance,
depending on application needs. The classic structures include the Cockroft-Walton
[58], Dickson [59], and Cross-Coupled Voltage Doubler [85]. Numerous variations and
alternatives have been published [60] [23]. The SC ladder topology [56], discussed in
detail in Chapter 3 of this dissertation, will be the primary focus of this work. It
distributes the largest processed voltage equally over many converter components and
is thus amenable to IC integration where the voltage rating of each device should be
used to full potential but never exceeded.
2.5 An Overview of Bootstrapping Techniques
Bootstrapping is a term with several specific meanings in the literature of circuit
design. For simplicity in comparison the author prefers to consider two main categories
for these techniques. Circuits falling into the first category use some form of positive
feedback with loop gain near but less than unity (usually in a continuous-time analog
circuit). Examples falling into the second category apply a feedforward technique with a
replica of the input voltage, supply voltage, or a related voltage, used for some
7 Note that this is a separate but related topic when compared to traditional and well documented SC
filters [101] [161] using opamps.
63
advantageous purpose, usually to create boosted voltages above the rails. A form of
this second category of bootstrapping is proposed in this work to extend the useful
operating voltage range of the IC. Typical examples of the first general category (using
positive feedback) are transistor and/or opamp circuits that must interface with large
source impedances [29] and self-biased current references [86]. Most circuits in the
second category are applied in clocked applications, such as ADCs, DC-DC converters
or switched-capacitor circuits, and often depend on a “bootstrapping capacitor” for
operation [30]. In the IEEE Standard Dictionary of Electrical Terms [87], techniques
employing this second form of bootstrapping are described very generally: “A circuit
design technique in which a junction point (node) is capacitively driven to a voltage of
greater magnitude than that available from the device power supply” (from [87]). Several
examples are provided below to illustrate the main concepts from both primary
categories.
Circuits of this first form have been known since the early days of vacuum-tube
electronics, published even before World War II [88]. Although not yet specifically
termed “bootstrapping” at the time, positive-feedback was used to increase the input-
impedance of cathode-follower circuits when biasing the grid terminal [89]. Examples
employing the same general principle are used currently in many biomedical [90] and
audio applications [91] and are still at the heart of recent publications [92]. In general,
circuits that process voltage signals (as opposed to current) and interface with large
source impedances must present a comparatively larger input impedance to ensure
adequate signal transfer. These circuits are good candidates for this type of
bootstrapping: a simple voltage divider takes place between the signal of interest, its
64
source impedance and the amplifier’s input impedance. Bootstrapping can be used to
modify the impact of an undesirable but necessary impedance (i.e. perhaps from a
biasing network or an unavoidable parasitic) by making it “appear” larger using active
circuitry. This technique can be especially valuable for single ended power supply
opamp circuits, for example, as described in [29] and is a fundamental part of the
Howland current source [93].
An example included in the second category is the bootstrapping of the VGS of an
NMOS switch in a track-and-hold circuit during the track phase [30]. The NMOS source
connection is the input voltage itself. Instead of tying the gate to the supply, as is usually
done for the NMOS in a T-gate, a single NMOS can cover the complete input range
alone if its gate voltage also follows the input, keeping VGS constant at a given bias
voltage (usually VDD). As a result (ignoring bulk effect or dealing with it appropriately
[94]) the switch on-resistance RON is also constant for all input levels, which can greatly
improve linearity and the total-harmonic distortion (THD) in integrated ADCs [95]. In a
practical implementation a bootstrapping capacitor CBOOT, typically pre-charged to VDD,
serves as the floating bias voltage source during the track phase. As detailed in [96], in
the hold phase auxiliary circuitry is needed to keep CBOOT charged and ready for the
next clock cycle and during this time the NMOS gate, in ADC circuits, is typically tied to
ground ensuring its off-state. As long as the sampled voltage never exceeds VDD, the
gate-oxide voltage (equal to |-VIN| max) should also remain safely within intended limits.
In this work a series of bootstrapped switches will be operate in tandem to process input
voltages above the supply; tying the gate to ground for deactivation would pose a
serious reliability issue and, as will be presented, must be avoided here.
65
A similar switch bootstrapping technique is applied to the high-side switch (HSS)
in many inductor-based buck converters [97]. When the output voltage is made low by
pulling it to ground potential through the low-side switch (LSS), a diode is used to
charge CBOOT to approximately VDD (ignoring the diode voltage drop). In the next half
cycle, when the LSS is off, the output voltage rises with activation of the HSS. The
diode turns off and the gate drive circuitry for the HSS is itself powered by the energy
stored in CBOOT; this drive circuit can then operate up to VDD volts above the output
voltage.
2.6 Conclusions for Chapter 2
A literature review was provided in this chapter to explain or support important
design decisions taken for the work introduced in this dissertation. Without inductors, an
SC approach is necessary for boosted voltages above the supply. For creation of high-
resolution drive waveforms with bidirectional current flow, direct implementation of
standard charge-pumps doesn’t appear possible. Bootstrapping techniques will be used
for a novel architecture that meets system and device level design constraints.
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CHAPTER 3 A 10V FULLY-INTEGRATED BIDIRECTIONAL SC LADDER CONVERTER IN 0.13 μm
CMOS USING NESTED-BOOTSTRAPPED SWITCH CELLS (TASK 1)
3.1 Application and Design Overview
3.1.1 Background
The ARL Micro-Flyer prototype [14] [15] [17] [18] and associated design
requirements for a compatible piezo-driver circuit were introduced in Chapter 1. A
summary of these considerations is as follows. The wing actuator presents a
predominantly capacitive load to the driver (~5 nF or less) and requires <500Hz
actuating waveforms in the 0-10V range, implying bidirectional (positive and negative)
load currents. Noting the especially small size of the prototype wings, an order of
magnitude smaller than those in [11], stringent limitations on mass/volume (an
approximate 0.1 to 10 mg max payload [16]) motivate a fully-integrated approach with
zero external components aside from the associated energy source. Thin-film batteries
compatible from a system standpoint typically provide 3-4V [21]. Furthermore, the final
envisioned system should also include a complex digital "brain" and RF communication
blocks on the same die as the drive circuitry, making a low-voltage CMOS process
attractive.
A 1.2V/3.3V 0.13 μm triple-well CMOS process with ≈10V N-well-to-substrate
breakdown voltage was thus chosen as a suitable tradeoff between voltage handling
capability and density of integration. Furthermore, as argued in Chapter 2, due to the
lack of suitable inductors on chip and the “light-load” nature of the application a
switched-capacitor approach [23] has been implemented. This chapter details the
design steps taken for the 1:3 step-up IC introduced in Chapter 1 for meeting the first
design task—the safe creation of drive waveforms above both supply and device rating.
67
The proposed approach is illustrated in Figure 3-1, along with example drive waveforms
for both Pitch and Stroke wing actuators. A nominal VDD = 3.3V supply voltage is
assumed, and the fully-integrated circuit implementation uses only on-chip MIM
capacitors and 3.3V I/O devices as switches, without external parts. With a low-voltage
band-limited waveform applied at the input (between 0V and the 3.3V nominal supply
voltage), the three-stage converter creates a 0-9.9V scaled waveform at the output,
operating effectively as a switched-mode amplifier with a 3x step-up.
Figure 3-1. Diagram of 1:3 step-up driver.
Throughout the VIN signal range, the circuit implementation must ensure that the
oxide voltages (VGS, VGD, VGB) as well as VDS never appreciably exceed the process
rating [98] [99], referred to here as "voltage compliance". Safe processing of the large
varying output voltage is accomplished by employing a bootstrapping technique, without
static bias circuitry or the creation of mid-range static supplies, applied to the SC ladder
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topology. High voltage 0.1 – 10 MHz clock drive signals track the much slower input
voltage and are derived using a proposed sub-circuit called the Nested-Bootstrapped
Switch (NBS) cell, simultaneously meeting the requirements of bidirectionality and
voltage compliance, the key challenges addressed in this work.1
3.1.2 Integrated Power Converters with Voltage Waveform Outputs
The goal of the piezo-driver circuit is to provide voltage waveforms with values
peaking above the supply voltage by 3x and as low as 0V with comparable drive
capability throughout. To better understand the proposed approach it is best to first
consider more typical methods for creating waveforms of this nature (possibly under
less stringent design constraints). Switched-inductor (SI) converters have ideal
conversion ratios primarily dictated by the continuously adjustable duty-cycle D [39].
Disregarding practical limitations, D is an analog quantity and can take on any value
between 0 and 1. Using pulse-width modulation (PWM) techniques, feedback control of
D can overcome line/load variation when a static DC reference is applied (DC-DC
conversion) or, as is most relevant for this work, a varying reference voltage (a
waveform) can be used for the creation of power signal waveforms both between the
supply rails (class-D amplifiers [28]) and above or below a DC supply input (DC-AC
inversion [100]).The resulting output waveforms can theoretically take on any value over
a finite voltage range (as set by the circuit implementation/topology, buck, boost, etc.,
along with component values) and can accomplish this with comparably high transfer
efficiencies [47]. However, inductors suitable for power conversion are not realizable in
1 The work presented in this chapter has been published by IEEE, presented first in [19] and further
developed in [113].
69
standard CMOS process technologies [23], and capacitors are the only available energy
storage element. Thus, a capacitor-based approach is the only practical option when
output signals must exceed the supply range in a fully-integrated solution using a
conventional foundry process.
In the realm of power electronics, as opposed to opamp-based low-power signal
amplifiers [101], on-chip switched-capacitor (SC) implementations have been
investigated mainly for DC-DC conversion. In this case, the ideal conversion ratio is a
rational number strictly set by the actual topology chosen and the number of stages
[81], and peak efficiency only occurs at this specific output value. For a given
configuration, operation apart from the ideal output level comes with a direct price in
terms of efficiency - fractionally more power must be burned in the effective output
resistance ROUT, representing increased conduction loss. Feedback control of ROUT is
typically accomplished by altering the switching frequency fSW which also impacts the
converter's dynamic losses due to actuating the MOS power switches. For a static
configuration, operation can be optimized [23] for only a single VIN:VOUT ratio and
combination of component sizes (capacitors and switches), fsw and loading2.
Several publications [23] [102] have proposed methods for reconfiguring the
actual SC architecture as part of the feedback regulation scheme (changing the ideal
conversion ratio) and allowing for a set of output levels having efficiency "peaks".
However, when processing voltages above the supply and the IC's device rating these
large voltages must be carefully distributed over several or many devices [5] [10]; for
2 The duty-cycle for an SC converter is usually set to a constant ~50% (for two phases, ignoring the non-
overlapping time) and doesn’t provide a comparable “knob” for feedback control as in SI converters.
70
reliability, it is imperative that all devices remain voltage compliant. It is especially
challenging to implement voltage compliant switching schemes for high conversion
ratios and a corresponding large number of stacked domains on-chip [103]. As the
configurability of a converter increases, implying a higher number of efficient output
levels (peaks), more complexity is required in terms of part count and clock signaling
making the aspects of voltage compliance increasingly difficult. Thus, only a limited
number of levels are permitted for practical reasons. Most examples in the literature
target DC-DC applications for a wider range of DC inputs and loading conditions (such
as [102] with 7 configurations), but it is also possible to implement a DC-AC inversion
scheme analogous to those using SI converters with a single input/supply voltage value
and feedback control. An SC implementation of this type permits only discretized output
levels of high-efficiency, not a continuous range like the SI case; resulting waveforms
are then of low-resolution only (see [104] and [105] using discrete parts) or the
complexity is high to improve waveform resolution (see [106], also off-chip). An on-chip
SC circuit of this type was proposed in [107] for creating drive waveforms in a MEMS
application but with only 16 discretized output levels, essentially achieving 4b of
resolution with no mention of efficiency.
3.1.3 Proposed Switched-Mode Amplifier Architecture
In this work, for SC-based waveform creation, we propose the simple concept of
operating a ladder converter as a switched-mode amplifier using a largely standard (and
static) step-up configuration with three stages as shown in Figure 3-2. A key difference
here is that the input voltage VIN is allowed to vary and is the signal to be amplified.
Assuming ideal switches and proper actuation throughout the signal range, the output
voltage is forced to follow with an effective gain of 3 (for "light loads" with |ZL| >> ROUT).
71
A benefit of this approach is that the SC converter itself is always operating with the
constant n=3 step-up—imposed by the nature of the topology—at the point where it is
most efficient from the standpoint of conduction loss [23] and without discretized levels.
Due to the predominantly capacitive load, feedback regulation is not strictly required
and a single optimized value of fsw is applicable, allowing for a simple implementation
with less circuitry and device area. Therefore, even though feedback control of fSW is
feasible (and beneficial) it is not the topic of this work or explored further here.
Figure 3-2. SC ladder converter with ideal switches.
The ladder converter operates using two non-overlapping clock phases, Φ1 and
Φ2 (with complements Φ1 and Φ2 ), and charge-transfer behavior follows the
description in [23]. The output voltage is developed across the load capacitor (the piezo
capacitance) in Φ2 by stacking three instances of VIN: the VIN input source itself and the
72
voltages on C1||C2 and C3. The top plate voltage of C1 sits at ~2VIN. At all times, the
voltage across any device (capacitor or switch) is no more than the applied input
voltage. This also holds true, approximately, if VIN is varying, as long as the change in
VIN is negligibly small from one clock period to the next (by design, fIN << fSW). This
architecture is thus perfectly suited for maximizing output voltage range while remaining
voltage compliant, as compared to alternative methods including other SC topologies,
and is thus very attractive for a completely integrated solution. If necessary, it can be
extended using more stages. Furthermore, with ideal switches (and not diodes) the
ladder converter (as with other SC topologies) is inherently bidirectional: if the input and
output designations are swapped, it then operates in the step-down mode and still
attempts to continually force the 1:3 relationship imposed by the conversion ratio. For
example, noting the naming convention in the figure, when VOUT is below 3∙VIN charge
will flow outwards to the load capacitor to counteract the imbalance. Likewise, if the
output is above this level, charge then flows backwards from the output load
capacitance and inwards to the VIN source. This behavior, which differs from that of
“push-pull” circuitry since only a single current path exists, continues over the input
range from 0V to VDD (and back).
Note that VIN refers to a secondary drive signal at a low voltage (a waveform
varying between the supplies), distinct from the ever-present static supply VDD but
drawing power from it. This signal actually drives the primary power path, and efficient
creation of this low-voltage low frequency analog waveform from the static supply
(perhaps by a “pre-driver” to feed the SC ladder driver, the second task of this
dissertation) is considered an important but secondary problem apart from handling
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large varying output voltages with bidirectional current flow as addressed here. In effect,
the challenge of efficiently creating continuous waveforms from a static supply has been
transferred from the more complex high-voltage domain to become a manageable and
more traditional "low-voltage problem". For the material considered in this chapter a
standard 50Ω signal generator will replace the role of the pre-driver (whose actual
implementation is the topic of Chapter 5).
A
B
Figure 3-3. Results of MATLAB sizing routine and embedded model. A) Predicted efficiency per CTOT and B) corresponding fSW.
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3.1.4 Sizing of MIM Capacitors and MOSFET Switches
Considering the DC-DC analysis presented in [23], it is interesting to note that an
SC converter's output resistance ROUT is not a function of the applied input voltage VIN,
in either the slow-switching limit (SSL) or fast-switching-limit (FSL) regions of operation.
Thus, with a slowly varying VIN, it might be reasonable to assume that the DC-DC
analysis still holds and ROUT remains approximately constant when applying the
converter as a switched-mode amplifier for low-frequency varying waveforms. This is
the initial assumption held here for sizing.
With MATLAB as a framework, switch and capacitor sizes for the SC ladder
configuration were optimized using a charge vector representation of the topology [56].
The associated simplified model is imbedded in the background of Figure 3-3A: the
turns ratio of the ideal transformer (applies to DC also) represents the conversion ratio;
RL is an effective resistance chosen here to draw similar peak current as the overall
piezo model (MΩ range); ISW is included to account for the load-independent switching
loss; and ROUT is the output resistance constraint, which represents conduction loss and
effective drive strength. For the N=3 ladder topology and its associated charge-vector
representation, with RL = 1MΩ (ILOAD of ≈ 10 μA), Figure 3-3B provides estimated fSW
values needed to meet two specified ROUT boundary conditions (10kΩ and 100kΩ)
versus a total allotted on-chip ladder capacitance Ctot. ROUT is dominated by switch
resistance in the case of high fSW and primarily by Ctot at lower fSW. Thus, using several
CMOS process technology constants and fixing Ctot, switch resistances were optimized
to meet the ROUT = 10kΩ constraint at an intermediate fSW between the two extreme
cases (labeled fSW-opt). Switching frequency can then be relaxed to a lower value
(labeled fSW-slow) resulting in ROUT ≈ 100kΩ (using the SSL approximation [23]). A
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corresponding efficiency plot (vs. CTOT, with fsw = fSW-opt from the bottom plot) is also
provided in Figure 3-3A but should be interpreted as a developmental theoretical target
which can be asymptotically approached but never attained.3
Assuming MIM capacitor structures – chosen for minimal parasitic substrate
capacitance (CSUB) and acceptable density (1fF∙μm-2 or equivalently 1nF∙mm-2) – a total
on-chip capacitor area of 1 mm2 was deemed acceptable for meeting system goals.
With Ctot = 1nF, the capacitors were sized accordingly as C1=500 pF and C2=C3=250
pF. Resulting prescribed switch resistances range nominally between 150 – 300 Ω and,
with assumed use of thick-oxide (~70Å) 3.3V I/O devices, the peak VOUT is nominally
~10V.
For verification, the converter from Figure 3-2 was simulated in SPICE using
ideal switches (with resistances) and the chosen SC ladder component sizes from the
MATLAB framework. Recalling that ROUT is indicative of the converter's drive strength at
DC and predicts the voltage drop in VOUT due to a non-zero DC load current, the SPICE
simulations also showed that the ROUT estimate, with capacitive load CL, could
reasonably predict output rise/fall times for a step input and the converter’s bandwidth
for low-frequency waveforms via the τ = ROUT∙CL time constant. For a 1MΩ || 4nF load,
ROUT vs. fSW was extracted from transient simulations with a DC input, as shown in
Figure 3-4A. Supporting the MATLAB model predictions, ROUT is ~10kΩ at fSW = 2.3MHz
3 The overall model in the script accounts for the idealized architecture itself only, additional switching
losses associated with the bootstrapped clock drive scheme (discussed in section 3.2) are not included. In other words, the gate-drive scheme is assumed to be free of energy cost and the efficiency estimations displayed merely represent a theoretical maximum value for the SC ladder architecture alone, for a given set of optimized component values and operating point. With practical dynamic losses in the drive scheme, combined peak efficiency will be lower (perhaps much lower) and may take place at a lower value of fSW then predicted. In terms of the research associated with this dissertation, meeting or closely approaching these efficiency targets was of secondary concern only.
76
and ~130 kΩ at fSW = 165 kHz. Results from 0-3.3V sinusoidal input waveforms are
summarized in Figure 3-4B, showing VOUT/VIN (in dB) vs. fIN. For a numerical check, with
fSW = 165 kHz the predicted low-frequency gain is 1MΩ / (1MΩ + 130kΩ) = ~ 2.65 V/V
(or 8.5 dB) and agrees well with the plot. The calculated f-3db ≈ 1/2π∙(1MΩ||130kΩ)∙4nF
= 350 Hz, which is slightly lower than the actual simulated SPICE output, extrapolated
to be slightly above 500 Hz.
A B
Figure 3-4. Summary of SPICE transient simulations using ideal capacitors and ideal switches with on-resistance. A) ROUT vs. fSW and B) VOUT/VIN vs. fIN.
A small caveat is now warranted. Recalling that the network theory for modeling
ROUT was derived for DC-DC steady-state conversion [23], it is not strictly applicable
here with varying input/outputs. For instance, not only is choosing "too large" of a total
capacitance futile in improving performance for DC-DC applications (operation would
than take place strongly in the switch resistance limited FSL region), but for varying
inputs it can become counterproductive due to a self-loading effect: the ladder
capacitors themselves must be charged/discharged to follow the input, not just the
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capacitive load. In this design, the total ladder capacitance is about 1/5th of the
maximum expected load capacitance of 5nF. Also, for output waveforms with small
ripple and for reasons of voltage compliance, fSW/fIN must remain above some minimum
value. At the necessary frequencies for the application, considering its associated load
model, and with the capacitor and RSW values used, the modeling error appears
negligible. Essentially, ROUT has been used to predict nominal system behavior here but
the accuracy of this method is not guaranteed in the general case.
Figure 3-5. Three-stage SC ladder with proposed switch arrangement and ideal floating switch drivers (voltage source clocks, in gray).
3.2 Circuit Implementation
3.2.1 Bidirectional SC Ladder Converter in Triple-Well CMOS
Figure 3-5 shows the fully integrated 3-stage ladder converter with the proposed
MOSFET switch arrangement. The thick-oxide MOS switches are nearly minimum
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length and have widths set to meet the effective “on” resistance (RSW) values prescribed
by the MATLAB framework. At these dimensions, the switches will contribute negligibly
to total IC area, dominated by the ~1nF on-chip capacitance. Implementing the PMOS
pull-up transistors instead as T-gates (TGs) allows for full swing charging and
discharging of the flying capacitors and load.
Figure 3-6. Voltage compliant gate drive signals for each voltage domain.
The primary difficulty lies with generating appropriate gate-drive signals to control
each MOS switch while VIN cycles between 0 and VIN-MAX, with the assumption that VIN-
MAX is equal to the maximum permissible oxide voltage VOX (3.3V), as shown in Figure
3-6. For instance, to activate MN3 a switching signal with magnitude larger than VIN, by
at least the threshold voltage VTH of the NMOS, must be applied to the gate during Φ1,
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and this voltage must always remain compliant (preferably above VIN by exactly VOX to
minimize RSW but never above this value). Predictable deactivation of the switch must
also take place. A solution that guarantees deactivation of N3 in Φ2 would be allowing
VGS_N3 to go negative by simply connecting the gate to ground, but since P2
subsequently pulls the drain of N3 up to 2VIN, a maximum |VGD_N3| stress of 2∙VOX would
result. Similarly, for N5 the same technique would cause up to a 3∙VOX stress.
Figure 3-7. Bulk and well connections (with p-type substrate at ground potential).
The use of ideal floating 3.3V clock sources (shown in gray) would circumvent
this problem. Each clock source operates in one of three voltage domains associated
with its respective SC ladder stage: “low” (L), which is static, and the dynamic “med” (M)
and “high” (H) domains. The switches are deactivated by safely tying the gate and
source voltages to the same potential (VGS=0V). As illustrated in Figure 3-6, the M
clocks move on top of VIN, transitioning between VIN or (VIN + VDD) during the
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appropriate phase, Φ1 or Φ2, peaking at 6.6V. In a similar manner, the H clocks follow
the envelope of 2∙VIN, peaking at 2VIN + VDD or 9.9V. Bulk and well connections, shown
explicitly in Figure 3-7, are also biased to a certain voltage domain to ensure compliant
gate-bulk voltages [108] but without loading the switching nodes, only those nodes
moving at multiples of the slowly varying input. The output voltage is then fundamentally
limited by well-bulk breakdown, which for this process is ~10V. Secondary benefits of
using floating drive in this fashion are relatively consistent RON values over the complete
input range, due to constant gate-drive and minimal bulk-effect, and waveform drive
strength that is approximately equal in either current direction and at any voltage.
Figure 3-8. Traditional gate-drive using floating CMOS inverter drivers powered by subsequent stage voltages [23]: not directly compatible here.
The ideal floating sources must be replaced by practical circuitry. One possible
method is to use floating CMOS inverter drivers powered by the SC ladder stage
capacitors themselves [23], as illustrated in Figure 3-8 for the H domain. However, since
in this application the stage voltages (including the output) vary and are designed to
operate down to 0V, these inverters would require their own separate floating power
sources and level shifted reference clocks [103], perpetuating the issue. We propose
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pre-generating approximations of the ideal gate drive signals shown in Figure 3-6
referenced to ground, using a feedforward approach by bootstrapping clock signals to
VIN and 2VIN. The gate voltages are then specifically defined. All SC ladder switches
transition between on/off states predictably if their corresponding source voltages (stage
voltages) approach their unloaded ideal values with error ≪ threshold voltage VTH
(MN5’s source is at ≈2VIN, etc.), a condition enforced by light load operation (|ZL| ≫
ROUT). These signals are created using a combination of bootstrapped switches (BTS)
as detailed in the next sub-section.
Figure 3-9. Typical bootstrapped switch used in data-converters [96], in the “offstate”. N0 represents any ladder stack NMOS. Example voltages shown for N5.
3.2.2 Development of Voltage Compliant Nested-Bootstrapped Switch (NBS) Cell
Most BTS topologies [30] [96] were primarily introduced for improving linearity in
SC data-converters and track-and-hold amplifiers. A representative example [96] is
shown in Figure 3-9. When the main BTS N0 is inactive a bootstrapping capacitor
CBOOT is pre-charged to VGS,ON (usually VDD). During the “on” state, this pre-charged
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capacitor is connected from gate-to-source of the BTS using several auxiliary devices;
the gate voltage then tracks the input voltage and provides nearly constant VGS and
RON. The key drawback is that CBOOT only acts as a floating voltage source for the “on”
state. When the switch is deactivated (as illustrated), instead of forcing VGS=0V, the “off”
state is assured by tying N0’s gate to ground (through the stacked NMOS). This is
important for SC integrator-based data converters, such as that in [95], to stop signal
leakage during the integration phase when VIN,B can take on any value4 above or below
VIN. However, even though the off-state is properly forced in this topology, the BTS
switch connections VIN,A and VIN,B cannot then safely exceed VOX without overstressing
the device. Recalling that voltages are as high as 3x the supply in this work, and that
device “N0” could represent any NMOS in the ladder stack, Figure 3-9 illustrates the
situation if N0 had replaced N5, highlighting the unacceptably large resulting |VGS|.
Advanced BTS options, such as the Double-Sided Bootstrapped Switch [109]
[110], could potentially be modified to overcome this “off-state” voltage stress limitation
by tying the NMOS BTS gate to the switch path terminal with the lowest voltage, either
VIN,A or VIN,B, instead of ground. Since several BTS cells will need to be cascaded (for
example, when creating the H domain clocks) and linearity only a secondary concern, a
simpler approach is much preferred to minimize both IC area and dynamic power
dissipation. A fact that simplifies this task is that the ladder voltage domains, during
normal operation, are well defined and follow the slowly varying input. Furthermore, the
use of a triple-well process provides additional flexibility not always afforded in many
4 Typically, for a data-converter, VIN,B would settle to the common-mode input voltage of the integrator
OTA.
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BTS implementations: the bulk-effect can be largely avoided in the BTS (as already
illustrated for the ladder stack itself). A relatively simple voltage compliant solution is
developed as part of this work for creating the bootstrapped level-shifted clocks.
A
B
C
Figure 3-10. Development of “Nested-Bootstrapped Switch” (NBS) cell. A) Dickson circuit concept, B) TG switch with overstress and C) Inner and Outer networks.
84
The basic concept for the new BTS starts with the ground-referenced clocking
scheme used in the classic Dickson converter [59], as configured in Figure 3-10A. The
goal is to safely create the M domain clock signal Φ1M, which alternates between VIN
and (VIN + VDD) and is applied to SC ladder switch N3. When Φ1 is low, the varying
input voltage is applied through diode D1 to bias a bootstrapping capacitor (CBOOT).
When Φ1 is high, the diode is deactivated and (ignoring the diode drop VD) the top-plate
voltage of CBOOT is (VIN + VDD). Conceptually, the top-plate voltage of CBOOT is directly
providing the desired signal. However, the use of a diode here results in unacceptable
error. Non-zero VD results in actuation failure for small VIN, and most importantly, the
rectification property of the diode will not allow CBOOT to discharge for falling VIN.
It is thus imperative to replace the diode with a bidirectional switch. A simple
option is the direct use of a CMOS TG switch, as shown in Figure 3-10B for when the
medium domain clock is active “high” and VIN=VDD=3.3V. A voltage compliance violation
of 2∙VOX clearly occurs for the deactivated TG NMOS. Instead, as shown in Figure 3-
10C, the switch can be implemented with an NMOS primary switch driven by a
secondary diode bootstrapping network, referred to as the “inner” and “outer” networks,
respectively. CBOOTA plays the role of the original capacitor from Figure 3-10B and
samples VIN over the complete input range and in both directions. CBOOTB in the outer
network is biased to the non-varying VDD supply voltage through Schottky-barrier diode
SBD1 (available in the process with no extra masks [111]), ignoring the ~0.2V diode
drop VD. Since the voltage across CBOOTB is constant, the recently mentioned diode
related concerns are not an issue in the secondary network. To ensure voltage
compliance of the primary NMOS switch, the bottom plate of CBOOTB is not clocked via
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an inverter but by an analog MUX that alternates between 0V and VIN. Thus, the NMOS
has a constant VGS gate-drive voltage of approximately VDD when activated and is
effectively bootstrapped to VIN (as is the load transistor N3) during this “on” state; hence
the term “nested bootstrapping”. 5 Deactivation of the primary switch N7 occurs primarily
by controlling its source voltage via CBOOTA and by forcing its gate to sit at ~VDD
(ignoring VD) when the Φ1 clock is high. However, unless VIN is large, charge from
CBOOTA will flow backwards into the source of N7 towards VIN, discharging the capacitor.
A B C Figure 3-11. Leakage path identification and removal. A) Simplified circuit, B) circuit
after flipping and switching S/D connections, and C) circuit with TG solution.
The identification and removal of this leakage path are shown in several steps in
Figure 3-11 parts A through C. The problem is highlighted in Figure 3-11A as ILEAK. A
simplified schematic in Figure 3-11B redraws the circuit upside down and swaps S/D
5 The proposed scheme could also be described as "pseudo-bootstrapping": the inner network only
approximates the gate-drive signal of a true BTS [21]. N3’s gate sits at VG = VDD + VIN' during the on-state, where VIN' is a sampled value of the slowly moving VIN (stored on CBOOTA). In [21], VDD is sampled instead and is stacked directly on the VIN signal source (VG = VDD + VIN). The outer network, with CBOOTB, operates in this manner (ignoring diode-drop VD). With fSW>>fIN, both methods have nearly identical gate overdrives but no true self-activating network exists here. THD sensitive applications, i.e. data-converters, may be negatively impacted by this “pseudo” method.
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terminal distinctions of the primary NMOS transistor symbol: with VIN=1V the device is
operating in the saturation region as a poorly controlled current-source. Placing a large
impedance in the leakage path, as illustrated, would eliminate the problem without
altering bootstrapping behavior but must be removed in the subsequent clock phase.
The addition of the CMOS TG in Figure 3-11C (shown deactivated) provides the desired
behavior. Assuming a small NW-substrate capacitance CH at the TG-PMOS source-bulk
connection, the high-impedance node will rise up to approximately VDD-VTHn, or one
threshold voltage drop down from the primary NMOS’ gate potential, but not higher –
protecting the device and deactivating its channel while also stealing limited charge
from CBOOTA. This behavior is quite similar to the shielding action of a stacked-NMOS
switch [5]. The TG itself also sees voltages limited to |VDD|, in both phases, and
operates safely.
Figure 3-12. Nested-Bootstrapped Switch (NBS) cell.
The final proposed solution is shown in Figure 3-12 and is referred to as the
Nested-Bootstrapped Switch (NBS) cell. The NMOS and CMOS TG combine to form a
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compound switch. Generalized terminal names are used: VA (the bootstrapping
reference signal to be tracked), ΦA and its compliment (clocks to control the T-Gate), VB
(sets the bias for CBOOTB), CKA and CKB (which clock their corresponding bootstrapping
capacitors), and VO-NB (the “nested-bootstrapped” output).
Figure 3-13. Simulation results (BSIM3v3 models) showing Φ1M and VGS-N7 with varying VIN.
As an example, the cell in Figure 3-12 is configured for creating Φ1M.
Corresponding node voltages are shown in the figure and specified for each phase (in
parentheses for when VO-NB is high) ignoring the negligible Schottky diode drop VD. Bulk
connections for the NMOS devices (not shown for N7) are tied to VIN, ensuring complete
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compliance of the oxides. Inspection reveals that |VGS|, |VGD|, and |VGB| of all devices
are limited to VOX (3.3V), during both the “on” and “off” phases and over all input
voltages (0 – 3.3V). Parasitic capacitance CH, which should be minimized, holds ~VIN
when the input is large but otherwise routinely rises to ~ (VDD – VTHn). SBD1 is clocked
through a CMOS inverter driver (the Φ1L signal here), instead of being directly tied to
VDD, for two key reasons: (1) to guarantee the diode “off” state for small VIN and (2) to
simplify the cascading of cells such that aside from the bootstrapping input all other
input-side connections (on the left) are clock signals referenced to the same voltage
domain (as will be illustrated later in the chapter). SBD1 has a maximum reverse bias of
nearly 2VDD (6.6V), far below its 11V breakdown voltage. Nominal simulation results are
provided in Figure 3-13 showing the desired Φ1M bootstrapped clock signal and the
associated VGS of the primary switch N7. Aside from short spikes during the non-
overlapping time, N7 is safely limited to a stress of approximately +/- VDD.
Parasitic capacitances can play a large role in the behavior of the NBS cell.
Figure 3-14A and 14B show a simplified model of the inner and outer bootstrapping
switch networks accounting for the most influential capacitances, both desired and
lumped parasitics (labeled in gray), for Φ1 and Φ2, respectively. Resistances are
neglected and settling each half-period is assumed. CDRV is the lumped effective load
capacitance that the NBS cell must drive with the bootstrapped clock signal (via the
“inner” bootstrapping network) and is typically dominated by the gate-capacitance of a
power switch in the SC ladder but also incorporates all parasitic capacitance to ground
at the VO-NB output node due to contributions of the devices themselves and routing.
Similarly, CG7 is the internal load that the “outer” bootstrapping network must drive and
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is dominated by the gate-capacitance of N7. The effective capacitance of the SBD when
“off” is represented by CSBD while CDSN7 and CDSTG are the effective drain-source
capacitances of the devices in the compound-switch, N7 and the TG, respectively; each
of these parasitic elements should be minimized. It should be noted that in Φ1 (see
Figure 3-14A), the N7 switch can be either connected (“on”) or disconnected (“off”)
depending on the value of VIN. Specifically, the switch should be “off” for large VIN with
VHiZ ≈ VIN and for small VIN, the switch will remain “on” until VHiZ is charged to
approximately (VDD – VTN), as described previously.
A
B
Figure 3-14. NBS cell simplified model considering capacitive loading. A) Operation in Φ1 and B) operation in Φ2.
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A simplified cross section of the layout of the NBS cell’s MOS devices is
presented in Figure 3-15, illustrating some key parasitic junction capacitances. Sizing of
the bootstrapping capacitors depends largely on loading and the parasitic capacitances
of the NBS cell; undesired charge-sharing detracts from the bootstrapping/shielding
actions and must be overcome with larger CBOOT. Thus, switch and isolation wells, for
each device in the NBS cell, were sized to nearly process minimums. Instead of placing
all the devices in a single N-well, perhaps to save total area, each of the devices were
placed in a separate isolating well to minimize the individual junction areas (and thus
capacitances) while meeting DRC rules for the process. The devices were separated by
a distance about 2x larger than then process minimum to provide a safety margin with
large reverse bias on the wells (up to ~10V). When possible, the well bias connections
should be tied to non-switched slowly varying nodes (VIN, etc.) to further minimize their
impact on circuit behavior and the well capacitance of the TG-PMOS (the key
contributor to CH) should be made small.
Figure 3-15. Simplified process cross-section showing important parasitics.
A first pass estimate for sizing the CBOOT capacitors, guided by Figure 3-14 and
noting the capacitive-divider nature of the circuit, should start with an estimated value of
the load capacitance CDRV, the assumption of nearly minimum size switches, and
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neglecting the effects of the parasitic components. The bootstrapping capacitors with
their respective loads then form simple capacitive voltage dividers in one clock phase
that are recharged to VIN or VDD (ignoring VD) in the subsequent half-cycle. Ideally, the
voltage across each bootstrapping capacitor (CBOOTA and CBOOTB) would stay nearly
constant over both phases. Thus, as a simple rule-of-thumb the following relationships
should hold: CBOOTA >> CDRV and CBOOTB >> CG7 (meaning ~20x or more). It is best to
then interact with the simulator (using accurate models with all relevant parasitics
included) to iterate and resize the devices until the desired behavior is observed for all
operating conditions. Here, resulting CBOOTA and CBOOTB range from 1-10 pF.
3.2.3 Voltage-Compliant High-Voltage Signals with Multiple NBS Cells
Combinations of NBS cells can be used to create arbitrary switching waveforms at
voltages above the oxide rating and supply. To produce Φ1H, all that is required is a
signal of 2VIN serving as the input voltage to an NBS cell having CBOOTA clocked by Φ1L;
the result is a clock signal that tracks (switches on top of) 2VIN. The conceptual
development of the Φ1H clock signal is shown in three steps at the bottom of Figure 3-16
using a simplified view of the NBS cell, as if it were only a diode and capacitor. This
approach proved helpful as a design aid with the “diode” in the simplified NBS cell
symbol actually representing the bidirectional compound switch and the capacitor
CBOOTA. In step one, VIN is biased onto the CBOOTA capacitor of NBS1 which is clocked
from below by an analog mux: a clock signal is developed that alternates between VIN
and 2VIN. NBS2 is configured as a voltage rectifier (a peak detector), resulting in the
replica 2VINr stored on its CBOOTA. Finally, this replica is fed into the input of NBS3,
which appends (“bootstraps”) a 3.3V clock on top: this is the desired high-voltage drive
signal for use in SC ladder block ΦH domain.
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Figure 3-16. Cascading NBS cells to create Φ1H using several M domain clocks.
A detailed example for Φ1H, showing a complete depiction of each cell and voltage
compliant connections, is also presented in Figure 3-16. The previously described ΦM
domain clocks (developed similarly for both phases and their inversions) are used to
drive subsequent NBS cells (labeled NBS1.A to NBS3). Alternating VIN - 2VIN clocked
waveforms (following Φ1 or Φ2) are applied to the CBOOTB capacitors (CKB connections)
of NBS2 and NBS3 to limit the oxide voltage of the NMOS device. For small VIN levels,
the NMOS is essentially left active (regardless of the clock state, high or low), and
actuation of the compound switch depends primarily on the TG; as VIN rises the NMOS
plays an increasingly important role. Careful consideration of the bulk connections for
the NMOS (as shown) is also necessary for compliance: for NBS1, NBS2, and NBS3 it
is tied to VIN, VIN, and 2VINr, respectively.
Figure 3-17 depicts the entire system as driven by NBS cells. The non-overlapping
clock generator drives SC ladder switches N1, N2, and P1 directly, in the L domain, as
well as several instances of analog MUX cells labeled “X” (see Figure 3-12). Three of
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four M domain NBS cells directly drive N3, N4, and P2, and all are used to develop the
various H signals. Replica 2VINr is created independently from the SC ladder to
minimize interaction and loading between the clock generation circuitry and the SC
ladder converter itself (which also has a node at ~2VIN). The NBS cell labeled “ΦVIN”
constructs the signal alternating from VIN to 2VIN, and NBS cell “VR” is the synchronous
voltage rectifier. Anti-parallel SBDs tie together 2VIN and the replica; these nodes are
largely independent but forced to nearly the same voltage during momentary loading for
protection. In total, three NBS cells reside in the H-domain and drive N5, N6, and P3 of
the ladder.
Figure 3-17. Detailed system diagram.
Results from a top-level simulation using BSIM3v3 device models (provided by the
foundry) are presented in Figure 3-18 for a slow VIN ramp from 0 to VDD (= 3.3V) and
back. The driver operates with fSW = 500 kHz and CL = 2nF. Displayed in the time
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domain output are the complete VIN, 2VINr and VOUT node waveforms, but several short
segments (~0.15 ms duration each) of the medium (M) and high (H) domain clock
signals are also included as an overlay. These clocks are of sufficiently high frequency
to appear as a continuous opaque block of either light (H) or dark (M) gray in the plot;
thus, only segments of the clock waveforms are shown but they are of course
continuous. Detailed waveforms of selected clock signals in each domain are inset in
the plot background (“zoomed”) and show proper non-overlapping behavior.
Figure 3-18. Detailed simulation results using BSIM3v3 device models.
To characterize the simulated driver, an ideal VCVS SPICE element with gain = 3
(and the same applied VIN signal) was fitted with an effective output resistor ROUT,EQ in
series and used to drive a capacitor equal in size to CL creating an idealized output
voltage VIDEAL. With ROUT,EQ tuned to 45 kΩ the practical and ideal output waveforms,
both of which are plotted in Figure 3-18, are nearly identical. This result fits well with the
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model predictions in Figure 3-3 and simulations in Figure 3-4A. Specifically, for fSW =
0.5MHz and Ctot = 1 nF the drive resistance ROUT should fall between 10k and 100k Ω.
3.3 Experimental Results for 1:3 Step-up Driver
A prototype test chip in the 0.13um triple-well CMOS process was fabricated to
prove the feasibility of the design techniques presented in this chapter. Figure 3-19
shows measured input/output voltages for representative 500Hz stroke and pitch
waveforms with CL=5nF (the largest specified value) and fSW = 8MHz. A peak output of
~10V is observed and the expected 1:3 VIN:VOUT ratio is attained. Figure 3-20 presents
the step response (3V input) of the converter for various fSW, resulting in nearly
symmetric rise/fall times of 57μs to 513μs for a 4nF||10MΩ load, characterizing the
bidirectional drive. Optimized for ~2MHz, the converter is in the fast-switching limit [23]
by ~8MHz.
Figure 3-19. Typical stroke and pitch waveforms under worst-case specified loading conditions and highest signal frequency.
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From a theoretical perspective, the prototype is largely voltage compliant by
design (detailed measurement of most internal nodes is not feasible). However, due to
an oversight, four transistors in the design (as configured in Figure 3-17) were clocked
improperly and experience systematic overstress in practice as high as 2VDD when
VIN=0V. Specifically, this is related to clocking several CKB nodes of the H-domain NBS
cells with signals alternating between VIN and (VIN + VDD) rather than the proper VIN and
(2VIN). The corrected scheme as detailed in Figure 3-16 is recommended, noting that it
shows two NBS cells creating the preferred signals (NBS1,A and NBS1,B) and not just
one as used in Figure 3-17 (called “ΦVIN”).
Figure 3-20. Step responses for various fSW.
Counterintuitively, even in this implementation, all devices (including the four
mentioned) should remain voltage compliant when VIN is at its maximum value of 3.3V
and VOUT ≈ 9.9V. The SC ladder core drive signals remain unaffected, as does the
VIN:VOUT relationship, and issues associated with the overstress did not manifest in
measurement but were discovered during a careful review and confirmed by simulation.
Nevertheless, long term performance of this prototype is expected to degrade due to
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time-dependent dielectric breakdown, and measured peak efficiency values might differ
in a corrected implementation.
Figure 3-21. Efficiency vs. VOUT and POUT for various fSW and resistive loads.
Efficiency measurements for DC operation are shown in Figure 3-21. In general,
overall efficiency is a function of the waveform and becomes reduced as fIN rises. This
can be conceptually explained using the simple ROUT model of Figure 3-3 with a
combined RC load. Capacitive load current iC increases with fIN and dissipates energy in
ROUT (≈IC,RMS2∙ROUT) but does not contribute to useful output power in RL. Thus, the
converter was first characterized at DC only for various resistive loads and fSW values
(250kHz-4MHz). The fully integrated converter is capable of >70% efficiency for a wide
range of resistive loads, 77% at ~800μW load with 9V output, but similar values are
possible at output levels near 100μW with reduced fSW. Additionally, the converter is
capable of driving an extremely light load, approaching 10μW, with 50% efficiency.
The resistive component of the wing actuator load is in the MΩ range. Thus, for
operation with sinusoidal signals, Figure 3-22 shows bandlimited voltage, current, and
power waveform measurements for a 4nF||1MΩ load at fIN = 150Hz (the nominal case)
and fSW = 400kHz. Currents are obviously bidirectional, sensed using a 10Ω resistor in
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20kHz bandwidth. POUT is directly computed, peaking at 158 μW, but PIN also includes
the measured average supply power contribution (~12.9μW at 400kHz). Over one cycle,
POUT, AVG = 36.6 μW and PIN,AVG = 60 μW for an efficiency of ~60%. An estimated
breakdown is as follows: 11.9 μW conduction loss PCOND in ROUT (~76.8kΩ) and 11.5
μW dynamic loss (PSW ≈ 0.23μW in the SC ladder, and the rest PNBS in the NBS cell
based gate drive scheme).
A
B
C
Figure 3-22. Measured waveforms. A) voltage, B) current, and C) power.
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Extended measurements, using the same 1MΩ | | 4nF load and setup, are
provided in Figures 3-23 and 3-24. Extracted ROUT vs. fSW (Figure 3-23) shows
acceptable but higher levels than those predicted by the SPICE simulation with ideal
switches (endpoints of 148kΩ and 36kΩ vs. 130kΩ and 10kΩ). The fIN bandwidth
dependency on ROUT, and ultimately fSW, is depicted in Figure 3-24A in terms of an
effective gain ratio VOUT / VIN in dB. The general trend is comparable to simulations, but
bandwidths are somewhat larger than that predicted by a simple (ROUT||RL)∙CL low-pass
roll-off (all f3dB ≥ 500Hz). Measured efficiency vs. fIN, see Figure 3-24B, shows that
efficiency of ~80% is possible at low fSW and fIN. Operation at higher fSW provides
increased signal bandwidth and lower attenuation but with an efficiency penalty due to
added dynamic loss of the gate-drive scheme. For fIN = 150 Hz, an fSW of 400 kHz
results in a reasonable balance of step-up ratio attenuation and efficiency.
Figure 3-23. ROUT vs fSW.
To further illustrate the converter’s operation as a switched-mode SC amplifier,
Figure 3-25 shows the 3x step-up behavior remains even for small input signals (50mV
100
peak,100mV DC offset). A ripple voltage is apparent at the VIN terminal as transient
input currents flowing during each half cycle interact with the finite resistance of the 50Ω
source generator.
A
B
Figure 3-24. Measurements vs. fIN. A) VOUT/VIN in dB and B) efficiency.
A die photo of the 1.5 mm x 1.46 mm IC, including pads, is shown in Figure 3-26
and is dominated by the area of the MIM capacitors, the NBS cells and ladder switches
taking a much smaller proportion (~1.4 mm x 0.2 mm). However, one key benefit of
using MIM structures is that they sit near the top of the metal layer stack and in the final
envisioned solution the digital “brain” for the Micro-Flyer robotic insect can then reside
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beneath. Two on-chip decoupling (MOS) caps help to ensure minimal supply droop
during switching transients.
Figure 3-25. Response to a small input signal.
A prototype of the ARL Micro-Flyer wing, as described in Chapter 1, was driven
by the SC ladder IC at resonance (~70Hz) for stroke actuation and photographed to
capture actuation angle.
Figure 3-26. Die photo of prototype test chip.
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Figure 3-27 shows an array of these photographs for various output voltages and
supports use of the design in the final application.
Figure 3-27. ARL Micro-Flyer prototype as driven by proposed SC ladder IC.
While a completely fair comparison to other examples in the literature is difficult,
due to the specific nature of this prototype design, an attempt has been made in Table
3-1 to relate this work with examples that employ similar circuit or system-level
techniques on-chip for processing larger voltages by distributing this voltage over many
devices. An emphasis has been placed on at least partial SC implementations.
Reference [10] is a hybrid SI/SC converter with integrated capacitors and is largely
compatible with the application targeted in this work (input/output voltage range, etc.).
However, an off-chip inductor is required and the design is capable of unidirectional
drive only. In [51] a two step-approach employs a dedicated DC-DC boost converter to
power a class-D amplifier (both steps operate in a high-voltage domain), creating ~10V
waveforms. It requires off-chip components, is optimal for resistive and comparatively
larger loads (W vs. μW), and it is not obvious how to scale down the design while
maintaining high efficiency.
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Table 3-1. Comparison table
Ref [10] Ref [51] Ref [61] Ref [107] This Work
Technology 0.13μm CMOS
0.18μm CMOS
0.18μm CMOS
65nm CMOS
0.13μm CMOS
Input Range 1.2 - 2V 3.3V 1.8V 1.2V 0 - 3.3V
Out. Range 6-10V 0-10V -0.7 - 14.8 0 – 7.5V 0 to 10V
fSW
Range 45MHz 1MHz ≥50MHz 1-200 MHz 20k - 10M
Pos. & Neg. ILOAD
?
No: Pos. (SI/SC step-up)
Yes (SI/class-D)
Yes (Dickson)
Yes Yes (Ladder)
Area 0.15mm2
2.08mm2
0.49mm2
0.35mm2
2.19mm2
Ext. Components
43nH 4.7µH, 100uF, diode
None None None
Load Capacitor
4.4nF N/A 22pF <32pF* 0.1 - 5nF
Max. Current
2.5mA @ V
O=7V
150mA @ V
O=10V
0.7uA @14.8V
NR** 93µA @V
O=9.3V
Peak Efficiency
37% @ V
O=7V
74% @ V
O=10V
<10% @14.8V*
NR** 77% @V
O=9V
*Estimated from reported data. **Not Reported
Perhaps the most relevant examples for direct comparison are [61] and [107];
both are integrated SC designs, exclusively, and are capable of waveform creation with
capacitive loads. Instead of a single power path as proposed here, in [61] two
interdependent 10 stage converters create floating power supplies of constant potential
difference, one “high” for the pull-up power path and the other “low” for pull-down. The
circuit outputs a selectable push/pull current of constant 0.7μA magnitude for PLL
applications and is demonstrated with a 22pF load, as compared to 5nF in this work.
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Overall, circuit complexity as well as efficiency concerns (unreported but estimated at
<10%) make the method less attractive as a piezo-driver. The PMOS diode based
design in [107] is compatible with standard CMOS but also relies on two independent
power paths, effectively doubling the circuitry, is exemplified with a load in the range of
pico-Farads [112] (estimated, not directly reported), and is capable of coarse 16 level
(~4b) waveforms; the analog approach here has no such limitation.
3.4 Conclusions for Chapter 3
In this chapter a 1:3 step-up SC ladder converter was introduced as a HV piezo-
actuator driver, intended for “task 1” as defined in chapter, for creating and safely
handling large waveform voltages on chip in a triple-well 0.13 μm CMOS process with
bidirectional load currents. One main concept proposed was the use of the SC ladder
converter as a switched-mode amplifier for low-frequency signals (0-500 Hz), using a
much higher frequency clock (20 kHz to the low MHz) along with a static 3.3V supply.
Enabling this concept is the use of a floating clocking scheme that follows the input
voltage (and a multiple of it) as it varies with the clock signals being developed by a
proposed circuit block called the “NBS cell”. These cells are flexible and can be
cascaded to process large signals in a voltage compliant manner. A prototype of the
converter supported the design concept.
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CHAPTER 4 POTENTIAL DESIGN IMPROVEMENTS FOR SC LADDER STEP-UP DRIVE STAGE
(TASK 1)
4.1 Background
In Chapter 3, an SC ladder based step-up drive stage was proposed for creating
waveforms with voltage swings above both the supply and voltage rating of individual
devices [113]. While the original implementation has proven to be functional in the
actual application for Task 1 of this dissertation, a smaller and/or more efficient design
would be preferable. This chapter serves to document design options and potential
improvements developed during and after measurements of the original work.
Specifically, a more portable implementation using only standard MOS devices (without
custom diodes) is first proposed while also simplifying the gate-drive scheme to use
fewer devices, representing an effective efficiency and area improvement. As compared
to the original single-phase output prototype, the merits of a dual-phase output ladder
structure are discussed (occupying essentially the same total on-chip area) and the
overall approach is presented in a more generalized manner for increased conversion
ratio N greater than 3. Considering the symmetry of a dual phase approach, it will be
shown that proper use of the cross-coupled switch has the potential to improve
efficiency significantly when compared to the NBS cell based solution. Without
additional measurements, SPICE simulations (using BSIM3v3 models provided by the
foundry) serve to illustrate and verify the potential design enhancements.
The chapter is organized as follows. Section 4.2 provides a review of the overall
concept with emphasis on topics pertinent to the proposed improvements. Section 4.3
and Section 4.4 present specific circuit and system-level augmentations, respectively,
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using an incremental approach. Supporting simulation results are discussed in Section
4.5 with a brief conclusion in Section 4.6.
4.2 Concept Overview
Relevant background material is briefly reviewed here with emphasis on
important concepts which should aid in the forthcoming discussion. The 3-stage SC
ladder converter [23] is shown in Figure 4-1 (repeated from Chapter 3 for convenience)
with ideal switches activated by non-overlapping clock signals Φ1 and Φ2.
Figure 4-1. SC ladder converter with ideal switches.
As described in Chapter 3, when operating effectively as a step-up amplifier
[113], VIN is distinct from the static supply voltage VDD and is in general a bandlimited
waveform with frequency fIN (nominally DC – 500 Hz in [113]) that can vary from 0V to
VDD. The clock signals operate at a much higher frequency fSW (ranging 0.1 – 10 MHz
in Chapter 3 [104]). In Φ1, flying capacitor C2 is connected to the VIN source and
107
recharged. In subsequent cycles charge is transferred from one ladder stage to the
next, ultimately charging or discharging the load capacitor CL. With N=3 stages, the
unloaded output voltage VOUT is ideally 3∙VIN and is developed over several clock cycles
before reaching periodic steady-state operation. Charge transfer to CL takes place in
phase Φ2 only, a relevant point to be revisited later. CL itself must support any
additional load current during Φ1.
For DC-DC conversion [23] and for waveform operation within certain relative
limits (CL range, fIN vs. fSW, etc.) [113], the SC converter can be represented using an
ideal transformer model with conduction loss and effective drive strength characterized
by output resistance ROUT [23]. As a function of fSW, actual values of ROUT can be
predicted theoretically using a charge-multiplier vector representation of the topology
[56] along with sizing information (capacitor sizes and switch resistances).
Subsequently, waveform driver 3dB bandwidth, for a predominantly capacitive load, can
be approximately predicted using the time constant ROUT∙CL [104].
For the given topology and a set of component sizes, a plot of ROUT vs. fSW (see
[23]) shows two asymptotic regions of operation referred to as the slow-switching limit
SSL (at low fSW) and the fast switching limit FSL (at high fSW). The expression for ROUT
in the SSL is dependent only on capacitors but not on switch and path resistances
(essentially, it assumes that each effective RC charging event during each sub-cycle
perfectly settles). For a two-phase architecture [23]:
𝑅𝑂𝑈𝑇,𝑆𝑆𝐿 = ∑(𝑎𝑐,𝑖)
2
𝐶𝑖𝑓𝑠𝑤
𝑀𝑖=1 (Eq. 4-1),
where M is the number of capacitors, Ci is the ith capacitor in the converter and aC,i is
the ith entry of the topology’s capacitor charge multiplier vector aC. It is a function of the
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conversion ratio N (encoded in the length of the vector). Conversely, for the FSL, ROUT
is dependent only on switch resistances (conceptually, it implies nearly constant current
flows and capacitor voltages during each sub-cycle charging event [74]):
𝑅𝑂𝑈𝑇,𝐹𝑆𝐿 = 2 ∑ 𝑅𝑆𝑊,𝑖 𝐾𝑖=1 ∙ (|𝑎𝑟,𝑖|)
2 (Eq. 4-2),
where K is the number of switches, RSW,i is the resistance of the ith switch and ar,i is the
ith element of the charge multiplier vector ar for switches.
A key topic in Chapter 3 (and [113]) and expanded here is the implementation
and proper actuation of practical switches in the ladder network as VIN varies from 0V to
VDD (and back). It was shown that use of NMOS pull-down and TG pull-up switches
allows for full-swing behavior over a complete VIN cycle [113]. The key remaining
challenge is creation of voltage-compliant gate-drive signals for the switches. As
discussed in Chapter 3 each stage of the ladder operates, in general, in its own varying
voltage domain and requires a set of non-overlapping clock signals, either in the static
ground based “low” domain or following a multiple of VIN (i.e., for the “medium” and
“high” domains with N=3).
The NBS cell introduced in [19] and displayed in Figure 4-2 (repeated from
Chapter 3 for convenience) is a functional option for safely creating and processing
these waveforms above the supply and device voltage rating. Its operation depends on
use of the non-overlapping clocks Φ1 and Φ2 (and their complements) and appending
them to low-frequency varying signals (i.e. VIN). However, the original cell utilizes a
custom Schottky barrier diode (SBD) that, in addition to the diode voltage drop VD, has
several drawbacks when compared to a MOS switch. The SBD’s simulation model was
created independently using characterization data of a limited sample size, taken at
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room temperature, and was not provided by the foundry. Many foundry CMOS
processes support typical PN junction diodes only [114] and not Schottky devices
whose behavior can be quite temperature dependent [115]. Thus, the NBS cell in its
original form was designed using an imprecise diode model and is not easily ported to
another process or process node, especially considering practical process variation. For
increased portability, robustness, and better modeling, it is prudent to investigate MOS-
only alternatives to the NBS cell. This investigation, the topic of the next sub-section,
leads intuitively to subsequent proposed improvements at the system-level.
Figure 4-2. Nested-Bootstrapped Switch (NBS) cell.
4.3 MOS-Only NBS Cells and the Cross-Coupled NMOS Switch
Figure 4-3 shows one proposed alternative to the original NBS cell, referred to as
a “MOS only NBS” or an MO-NBS cell. The diode has been replaced by a compound
switch formed by P9/N8, using the same structure as that of the VIN path (namely the
P0/N0/N7 combination) but with the gate of NMOS “footer” device [5] N8 clocked by the
cell output VO-NB itself. The pull-up NMOS device N9 of the additional compound switch
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transmission-gate (TG), shown in gray for clarification, is not needed due to the fact that
CBOOTB should always sample ~VDD and never small voltage values; N9 can then be
removed. The bulks of N0, N7, and N8 are typically tied to the input connection node
VA. Simulation results in Figure 4-4A through 4-4C show the functionality of the MO-
NBS cell as a viable alternative to the original NBS approach from Chapter 3, including
complement SC ladder drive waveforms zoomed to a clock transition at maximum VIN
and corresponding cell device voltages, compliant and limited to approximately +/- VDD.
Figure 4-3. MOS-Only Nested-Bootstrapped Switch (MO-NBS) cell.
For further refinement, first recall the bulk connection of N7 is tied to VIN (for
safely creating the Φ1M domain clocks in Chapter 3). If two NBS cells are cross-
coupled, as shown in Figure 4-5A along with N3 and N4 from the “medium” domain in
the SC ladder stack, then the complete “outer” bootstrapping network can be removed.
Going one step further, the compound switch TG formed by P0/N0 (which provided a
Hi-Z off state in the original NBS cell [113]) is no longer necessary and can also be
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eliminated: the gate-drive signals from the two NMOS devices are perfectly
complimentary and the original leakage issue solved by the TG is non-existent.
A B C
Figure 4-4. Simulated complement drive signals using MO-NBS cells. A) Three voltage domains stacked, and both B) and C): assorted H-domain cell voltages
This solution shown in Figure 4-5B is, of course, the standard cross-coupled
NMOS (CC-NM) switch prevalent in SC voltage doublers (see [116] [85]) but with
exploitation of one subtle feature not originally obvious to the author – the sampled
signal on the CBOOTA capacitors, usually VDD in most doublers, can differ from VDD and
can generally be of magnitude much lower than the clock signals’ (i.e. Φ1L and Φ2L)
peak values, or much higher. Namely, the switches actuate properly even if the
sampled signal varies in an analog fashion (slowly, over many cycles), from 0V and up
to VDD or higher, while the inverter driven clock alternates between 0V and VDD (or the
desired VGS “on” value). For reasons of both actuation and voltage compliance, the p-
type bulk (“triple-well”) and isolation N-well connections of N7 should be tied to VIN and
the sampled signals on each capacitor should approximately match, even when loaded.
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The capacitors themselves must, of course, withstand the maximum sampled VIN
voltage.
A
B
Figure 4-5. MO-NBS simplification steps. A) Two-cross coupled cells, “outer” networks removed and B) after removing N0/P0: the CC-NM switch.
The cross-coupled switch is certainly not new in the literature [117] and has
already been applied in the proposed manner for properly actuating the chopper
switches in offset-corrected CMOS opamps [118] [119] and, more recently, improving
SC opamp circuits [119]. Although this feature does not appear to be commonly
exploited or emphasized in many SC power converter examples, it has in fact been
implemented much earlier in [120]) and perhaps elsewhere. Noting the much smaller
device count, to decrease dynamic losses and improve the SC ladder drive scheme, the
CC-NM switch should replace as many NBS cells as possible in the SC Ladder step-up
amplifier circuit.
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A B C
Figure 4-6. Simulation results for CC-NM. A) VIN ≈ 0V, B) VIN ≈ 1.65V, C) VIN ≈ 3.3V.
The buffers driving the capacitors of the CC-NM are clocked by signals Φ1L and
Φ2L, respectively. Thus, the clock signals formed on the top capacitor plates (from the
schematic symbol point of view) are automatically Φ1M and Φ2M, as described in [113]
and Chapter 3. As shown in the BSIM3v3 simulation results of Figure 4-6 (zoomed to
signal transitions and with time axes referenced to the start of a 2μs clock period), these
pseudo-bootstrapped [113] or “level-shifted boosted clocks” [119] are gate drive signals
in the “medium” voltage domain alternating between VIN and (VIN + VDD) – a pair of full-
swing non-overlapping clock signals “riding on top of” the slowly varying VIN. With fIN =
500Hz, Figure 4-6 shows three excerpts from a transient simulation, at minimum, half-
range, and maximum VIN, in parts A, B, and C, respectively. Non-overlapping time is
~4ns. The only sizable dynamic load for the CC-NM is the combined gate capacitance
of the corresponding cross-coupled device (N7) and the actual switch being driven (N3
or N4). Compared to the original NBS cell solution for the same two m-domain signals,
this saves a total of 4 transistors, 2 capacitors and 2 diodes, representing a significant
decrease in dynamic power loss and a more portable solution without the custom SBD.
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Specifically, with operation at fSW = 500kHz and fIN = 500 Hz, simulations show a 4x
improvement in dynamic power loss (2.48 μW vs 0.62 μW) when a pair of medium-
domain NBS cells are replaced by the CC-NM switch. From a system standpoint, while
holding overall efficiency constant, the exchange should result in higher allowable fSW
and therefore lower ROUT (improved drive strength, wider VIN:VOUT signal bandwidth) for
a given SC ladder size and CL. Alternatively, the system can shrink in size.
Sizing estimates for the actual CC-NM and corresponding CBOOT capacitor can
be made by hand calculation, noting the capacitor-divider nature of the circuit. For each
clock cycle, when “high” (at VIN + VDD), the CBOOT capacitors lose charge to the gate(s)
of the MOS devices being clocked, due to both self and external loading. CBOOT must be
made large enough such that this associated voltage drop is acceptable and the VGS-ON
of the ladder device remains high enough for optimum actuation (preferably, nearly
VDD). Final sizes should be confirmed using post-layout parasitic extracted views and by
interacting with the simulator.
4.4 System-Level Improvements by Exploiting Symmetry
At the system-level, the symmetry of the CC-NM structure should be fully
exploited (for all domains), with all possible NBS cells replaced by cross-coupled
switches and the loading for each CBOOT capacitor made approximately balanced for
each phase. A closer look at the actual SC ladder, provided in Figure 4-7, reveals that
the load experienced by the Φ1M and Φ2M CBOOT capacitors is not equal over the
complete range of VIN. In the single-phase output network, N3 has its gate tied to source
forming a nominally constant capacitive load of CGS + CGD throughout. N4, on the other
hand, is affected by the bulk-effect (0V to VDD, but not more) and consequently has a
somewhat different signal dependent capacitance. Furthermore, and most importantly,
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the pull-up transmission-gate PMOS of each stage (for example, P2) loads one phase1
only. Thus, the use of a dual-phase output SC ladder architecture [23] for the step-up
amplifier, as shown in Figure 4-8, is proposed to provide a completely symmetric load
for gate-drive circuitry over the VIN signal range.
Figure 4-7. Single-phase output three-stage SC ladder [113].
Two single-phase ladder stages are now running staggered and in parallel, each
of which can be characterized by an output resistance. In Φ1, the left half provides
charge to the load (as represented by IΦ1) as does the right half in Φ2. The overall ROUT
is then the parallel combination of the effective resistances of the left and right sides,
ROUT,L and ROUT,R, respectively. To keep total ROUT and aggregate on-chip capacitor
area largely unchanged, the capacitors of each ladder side can be assigned half of their
1 More precisely, these PMOS devices load the complement signal of one phase only (either Φ1
and Φ2 ).
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corresponding single-phase output values, as confirmed by the SSL expression for SC
ladder output resistance in Eq. (4-1).
Figure 4-8. Dual-phase SC ladder.
An added benefit of the dual-phase approach is that the loading at the ladder VIN
terminal is approximately constant (ignoring non-overlapping time) over each complete
switching period. This can simplify the design of “pre-drive” circuitry (Task 2, the topic of
a subsequent Chapter) when compared to the single-phase output case which presents
grossly different impedances in Φ1 vs. Φ2.
The NMOS switches in the dual-phase architecture ladder stacks can be directly
driven using the CC-NM switch combinations. The PMOS devices, however, require
clock signals that stay high longer than they stay low (to keep the PMOS off during the
non-overlapping time). Unfortunately, a single pair of cross-coupled NMOS devices
cannot have both devices high at the same time without discharging the CBOOT
capacitors, resulting in complete malfunction or, at best, significant degradation.
117
Figure 4-9. Dual-phase SC ladder with combined CC-NM and MO-NBS drive.
One possible option for the PMOS ladder stack devices is then direct use of MO-
NBS cells, as shown in the combined CC-NM / MO-NBS system example of Figure 4-9.
Support for MO-NBS operation for the PMOS complement drive signals was provided in
Figure 4-4A. With proper clocking, these cells experience shoot-through charge loss
during each on-off transition only and not during the comparatively longer non-
overlapping time. In this system implementation there is no use of a replica 2VIN signal,
as was included in the original solution proposed in Chapter 3 [113]; simulations support
proper system operation even when the drive circuitry and main path interact. Thus, the
extraneous and power hungry 2VINr circuitry has been removed for a more compact
and efficient solution. The two 2VIN nodes and C1 capacitors from Figure 4-8 have been
connected and combined resulting in a single (unlabeled) capacitor in gray in the center
of the schematic. Simulations verifying the system are provided in Figure 4-10 using the
same CTOTAL (~1 nF, 0.5 nF per leg) and estimated chip area as the original solution in
Chapter 3 [113].
118
Figure 4-10. Simulation results for CC-NM / MO-NBS implementation of Figure 4-9.
The device count of the MO-NBS cell (5 transistors, 2 capacitors) remains higher
than the CC-NM switch per drive signal (1 transistor, 1 capacitor) implying the potential
for further improvement. One promising solution involves application of two pairs of CC-
NM switches, for each pair of PMOS ladder stack switches, driven by clock reference
signals with asymmetric on-off times (or duty cycles > 50%). This methodology has
been supported by simulation (results not provided) but due to the cost of creating
reference clocks using modified timing, overall, this approach does not provide a clear
savings of area and power.
A natural alternative solution to consider for driving the PMOS devices is the
cross-coupled PMOS (or CC-PM) switch [120]. As presented in Figure 11, this circuit
arrangement results in negative clock signals that swing below VIN or the reference
119
input signal, a useful trait often applied in negative output voltage charge-pumps [121].
Specifically, signals Φ̅1𝐿,𝑁𝐸𝐺 and Φ̅2𝐿,𝑁𝐸𝐺 are complement clocks that alternate between
VIN and (VIN - VDD) during the appropriate phase, reaching a minimum value as low as –
VDD below ground when VIN = 0V. A key feature of the CC-PM cell, as VIN varies, is
nearly constant PMOS VSG “on” voltage of VDD = 3.3V (essentially the “pseudo-
bootstrapping concept” of Chapter 3 but for PMOS devices) and thus nearly constant
RSW switch resistance. However, this form of operation below the substrate ground
reference voltage is associated with several potential but manageable risks, including
latch-up and substrate noise injection. Well connections and guard rings must be
carefully considered [122] [123].
Figure 4-11. Cross-coupled PMOS for negative clocks.
In the author’s view, the most compact and overall efficient implementation of the
SC ladder step-up amplifier would take advantage of CC-PM switches [120], accepting
this small but additional reliability risk (which has been overcome in many commercial
examples [124] [125] and, as will be shown, the proposed circuitry of Chapter 5). The
original drive scheme of Chapter 3 has three voltage domains: low (which is ground
referenced) and the “moving” medium and high domains. A small but important change
in perspective is necessary to optimally implement the CC-PM drive concept – each
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PMOS switch in the SC ladder, including that of the original “low” domain, must be
referenced to its source connection (i.e. VIN for P1 and 2VIN for P2, etc.), splitting the
originally defined domains in two. As illustrated in Figure 4-12, a single pull-up PMOS
can be then be used without need for the T-gate NMOS (N2, N4 and N6 have been
removed) and switch on-resistances, for all devices, remain essentially constant over
the VIN range.
Figure 4-12. Concept for PMOS drive with negative-going voltage signals.
A complete practical circuit level implementation is proposed in Figure 4-13,
referred to as a “Compact Dual-Phase SC Ladder Drive Stage”. The topology is fully
symmetric and all devices equally utilized. Situated in the center of the schematic are
two CC-NM cells and conventional CMOS inverter clock signals (Φ1L and Φ2L) to drive
pull-down switches N1, N3, and N5. Using a similar naming convention as the original
Chapter 3 step-up amplifier circuit, the resulting NMOS drive signals, in red, are Φ1M,
Φ2M for the “medium” m-domain and Φ1H, Φ2H in the “high” h-domain. Placed on either
outer side of the schematic are three CC-PM cells split at their center points, labeled
a,b,; c,d; and e,f, respectively, which are electrically connected. The CC-PM cells drive
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the main ladder pull-up power switches P1, P2, and P3. The associated clock signals,
labeled in blue, reside in voltage domains that track multiples of VIN but with negative-
going complement clock signals. Specifically, signals Φ̅1𝐿,𝑁𝐸𝐺 and Φ̅2𝐿,𝑁𝐸𝐺 (as in Figure
4-11) are in the varying low-domain tracking VIN; Φ̅1𝑀,𝑁𝐸𝐺 and Φ̅2𝑀,𝑁𝐸𝐺 track 2VIN and
peak as high as 6.6V; finally, Φ̅1𝐻,𝑁𝐸𝐺 and Φ̅2𝐻,𝑁𝐸𝐺 follow 0-9.9V VOUT signal. With the
additional of a non-overlapping clock generation circuit block (not shown), this single
schematic should replace the comparitvely complex approach implemented in Chapter
3. Additionally, the simplicity of the design technique makes extending the ladder to
higher conversion ratios (N>3), even by inspection, a direct and straightforward task.
Figure 4-13. Compact Dual-Phase SC Ladder Drive Stage.
The most important consequence of this improved implementation is the potential
to fit two copies of the SC ladder step-up driver in the same area as the original with
comparable drive strengh and overall efficiency. By signicantly cutting down the number
of clocked devices (by at least a factor of 4) the circuit can operate at twice the fSW value
but with identical or improved switching losses. As expressed in Eq. (4-1) for SSL
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operation and confirmed by simulation in Section 4.5, if fSW doubles then total ladder
capacitance CTOT can be cut in half without appreciably altering ROUT.
4.5 Supporting Simulation Results
A detailed transistor level design of the circuit in Figure 4-13 was implemented in
the same 1.2V/3.3V 0.13μm CMOS process as the original SC ladder of Chapter 3.
While an associated layout for fabrication was not completed (this is considered “future
work”, as discussed in Chapter 6), top-level SPICE simulations were conducted using
BSIM3v3 device models from the foundry with inclusion of parasitic well diodes, for all
important devices in the drive scheme, and practical inductive bond-wire models for
interconnects.
Compared to the design in Chapter 3 using 1nF total capacitance, the simulated
dual-phase ladder uses 0.5 nF total (or 250pF per phase); the original layout area was
dominated by the ladder MIM capacitors and thus two channels should now occupy the
same space. To keep ROUT and drive strength roughly equivalent between the two
designs, the expected fSW must also scale by 2x, implying the switch resistances should
be halved and thus transistor widths in each ladder approximately doubled. These
changes were effectively applied to the simulated design.
For verification, transient simulations with fIN = 500 Hz and CL = 2 nF were run
over the industrial temperature range [126], namely at -40°C, 27°C, and 85°C, and
confirmed using corner models from the foundry. For an initial set of simulations, the
MIM capacitors were held constant, using the nominal model, and only transistor
parameters were varied. Extracted switch resistances (RSW) for the symmetrically sized
SC ladder NMOS pull-down and PMOS pull-up switches are shown, for each corner
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case, in Figure 4-14. Associated transient simulation output waveforms, with fSW =
1MHz, are plotted in Figure 4-15, stacked and sharing the same axis.
A B
Figure 4-14. Extracted RON for main SC ladder switches over corners and temperature.
To characterize the simulated converter, using the same method as in Chapter 3,
the plot also includes the output “VIDEAL” from an ideal gain=3 voltage-controlled voltage-
source2 fitted with a series resistor ROUT,EQ. In this case, ROUT,EQ is 41.5 kΩ, a slight
improvement over the original 45 kΩ at analogous operating conditions. As supported
by the “zoomed in” portion of Figure 4-15, the waveforms are nearly indistinguishable
from each other, displaying negligible dependence on temperature and process
variation at the chosen fSW value. Furthermore, noting the 40μs scale, the tuned value of
ROUT,EQ is relatively accurate and need not change for each corner/temperature case.
This robust behavior is explained by operation strongly in the SSL region of operation,
where ROUT is most sensitive to changes in ladder capacitance, C1 through C3, (and
2 With identical VIN and RC loading.
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fSW) but not switch resistance. The drive scheme itself, based on the CC-NM and CC-
PM switch scheme, does not appear to present any additional weakness.
Figure 4-15. Results of transient simulations for compact dual-phase SC ladder drive stage over device corners and temperature (with nominal MIM capacitors).
Two additional simulations were run at room temperature (27°C) with nominal
transistors but minimum and maximum MIM capacitor models (also provided by the
foundry); associated output waveforms are provided in Figure 4-16. Capacitor size has
potential impact on the switch-drive scheme and the behavior of the main dual-phase
ladder. As compared to variation in RSW, the resulting dependency on capacitor size
variation (approximately +/- 15%) is prominent but not excessive, taking note of the 600
μs scale in the magnified inset. Validating the SSL assertion (see Eq. (4-1)), resulting
ROUT,EQ values (associated VIDEAL waveforms not shown) are inversely proportional to
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total ladder capacitance and range from 48kΩ to 36 kΩ, also a shift of nearly +/- 15%
from the nominal case. Peak voltages remain in an acceptable range throughout
(~9.65V to ~9.75V).
Figure 4-16. Transient simulation outputs for minimum and maximum MIM capacitor densities and nominal transistors (27°C).
Figure 4-17 presents a more complete picture of achievable drive strength for the
step-up amplifier stage, which improves with increased fSW and is represented by ROUT.
The specific ROUT values for each transient simulation condition were extracted from the
phase difference between VIN and VOUT and by assuming a first-order ROUT∙CL model.
Even up to 8MHz, the highest simulated frequency due to otherwise excessive
simulation times, the converter appears to operate in the SSL region with an
approximate halving of ROUT for each doubling of fSW. Minimum simulated ROUT is
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approximately 5kΩ, which is more than satisfactory considering the empirical
performance of the Chapter 3 original at higher ROUT values. Also, it is a reasonable
supposition that lower ROUT is likely achievable at increased values of fSW over 8MHz,
until reaching the switch resistance limited FSL region [23]. The expectation of widened
SSL range is especially sensible considering the overall decrease in total ladder
capacitance CTOT (500 pF vs. the original 1 nF) and the halving of RSW between the
Chapter 3 and Chapter 4 designs.
Figure 4-17. Extracted simulated ROUT vs. fSW.
The simulation results presented thus far indicate proper converter performance
in terms of drive behavior. Verifying the potential decrease in dynamic loss is an
important secondary goal. The average current drawn from the static VDD = 3.3V supply
for the original bootstrapped-drive scheme of Chapter 3 was very well predicted by
simulation, off by only a few percent from measurement, and represents a solid first
indicator of dynamic power dissipation. At fSW = 1 MHz, the measured NBS-based
solution drew 9.8μA compared to just below 3μA for the simulated dual-phase SC
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ladder. This improvement factor of approximately 3x is impressive and brings credence
to the discussed design enhancements, especially when recalling the simulated
implementation uses half the capacitance as the original, is simpler to implement, and is
characterized by similar levels of predicted ROUT. Additionally, the design requires only
standard and proven device models from the foundry and no custom diodes (whose
models are based on a very limited sample size). Thus, the simulations are inherently
more reliable than those of Chapter 3, especially over temperature and when
accounting for process variation. The design itself is more portable from one process to
another.
4.6 Conclusions for Chapter 4
In Chapter 3, an SC ladder based 3x step-up drive stage was proposed to meet
the requirement of “Task 1”, that of driving a 10V 5nF piezo-actuator for the Micro-Flyer
Application. Measurements strongly supported the design concept. However,
subsequent considerations prompted an investigation into potential design
enhancements, primarily to improve efficiency and solution size. Chapter 4 has served
to document and explain the most promising sources of improvement. Namely, a diode-
less NBS cell, the MO-NBS cell, was introduced that is more portable and does not use
custom components. Like the original NBS cell, it is capable of driving either NMOS or
PMOS power devices. However, by cross-coupling the outputs of MO-NBS cells, after
simplification, the resulting circuit was shown to be nearly operationally equivalent to the
cross-coupled NMOS (CC-NM) switch pair when driving NMOS devices. Alternatively,
the cross-coupled PMOS (CC-PM) can be used to create inverted “pseudo-
bootstrapped” clock signals for driving PMOS switches.
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At the system-level, due to their lower part-count, combinations of CC-NM and
CC-PM switches should replace the NBS cells completely, and redundant replica 2VINr
circuitry should be removed. The symmetry of the cross-coupled switches should then
be fully utilized; this is best implemented with a dual-phase but half-sized SC ladder
stage. Using PMOS-only pull-up switches in the main ladder, instead of T-gates, allows
for even lower device count but requires the addition of a varying complement low-
domain clock signal set. Noting the potential decrease in dynamic losses, the overall fSW
range can double without significant penalty in efficiency compared to the original
solution (on the contrary, reliable indicators predict it will improve). Thus, for overall
operation comparable to the Chapter 3 implementation, the sizes of the SC ladder
capacitors can potentially be halved. Two copies of the circuit, referred to as a
“Compact Dual-Phase SC ladder Step-up Drive Stage”, should then fit in the area of the
original. More importantly, detailed simulations predict reduced or similar overall power
consumption for the enhanced solution (for a single channel, with similar ROUT). The
proposed concept, of course, has only been supported by simulation and development
of a suitable prototype for measurement is considered future work. Measurements of
such a prototype will not be included in this PhD dissertation.
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1:3
Step-up
Driver
VOUT
VIN
0V
3.3V
VDD=3.3V CLK
0.13 μm CMOS
VREF
VCLK
CACT
IDRV
IIN
VDRV
Pre-Driver
VIN VOUT
CEFF
VREF
(Buffer)
IBAT
CHAPTER 5 A 3.3V BOOTSTRAPPED PIEZO-ACTUATOR CAPACITIVE LOAD (PRE)-DRIVER FOR ENABLING ENERGY RECOVERY AND CLASS G TECHNIQUES (TASK 2)
5.1 Background
In Chapter 3 a fully-integrated 1:3 SC ladder step-up converter design was
introduced for driving a piezo-actuator load while meeting the objectives of “Task 1”,
defined in Chapter 1, for the Micro-Flyer application. This converter design, with
potential improvements presented in Chapter 4, takes as an input a band-limited
arbitrary signal at a low-voltage (bounded by the 3.3V supply) and provides the 3x step-
up to create output signals approaching 10V. From a usage standpoint it operates in a
manner similar to a conventional amplifier. However, its input does not present a high
impedance to preceding “pre-drive” circuitry, also introduced in Chapter 1.
Figure 5-1. Task 2 – Efficient “pre-drive” of the step-up driver.
The development of an appropriate pre-drive circuit (in the same triple-well
0.13μm technology as the SC ladder), defined as “Task 2”, is the primary topic of this
chapter. Additionally, because of similarities in design objectives, the same architecture
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will be applied directly as a driver for an electric-field sensor [20] requiring 3.3V (pk-pk)
swing to an ~8 nF 15 kHz piezo-actuator load.
A
B
Figure 5-2. SC ladder simplified models. A) transformer model, B) equivalent load model as seen by preceding circuitry.
The primary objective of the pre-driver is efficient rail-to-rail drive of CEFF, the
effective capacitance seen looking into the SC ladder input. For convenience, the
system diagram from Chapter 1 is repeated in Figure 5-1. To explain the origins of this
effective capacitance, a standard model of the SC ladder converter is shown in Figure
5-2A as portrayed by an ideal transformer (which includes DC operation) [23]. The turns
ratio N represents the conversion ratio of the converter (such that N=3). ROUT is the
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output resistance of the converter, and for the discussion here it is assumed small (it is
adjustable by altering fSW). Assuming the DC model is still applicable to low frequency
signals (see Chapter 3), the charge pump action of the circuit provides the 3x step-up at
the output. Due to conservation of energy (PIN ≥ POUT), the converter must draw at least
3x the load current at its input terminal. An effective impedance transformation results,
similar to that of a conventional transformer, taking the load impedance and scaling it
down by a factor equal to the square of the step-up ratio (n=3), as viewed from its input
(VIN/IIN). Thus, in addition to the capacitance of the SC ladder itself, the converter
presents an equivalent capacitance of 32∙CL to the preceding circuitry, nominally as high
as 45 nF. It is this capacitance that dominates CEFF, but it must also include a capacitive
component due to the SC ladder itself (the total capacitance used is ~1nF), and so a
target specification of 50nF was chosen for the pre-driver. The resulting simplified
loading model used for designing the pre-driver is presented in Figure 5-2B. REFF is the
equivalent resistive component seen at the SC ladder input. At the frequencies of
interest the current draw through REFF is often negligible compared to that of CEFF and it
will be largely ignored. A caveat about the load model should also be expressed.
Because the model is based on averaged steady-state behavior [23], the actual
switched-mode details are not included. For example, the single-phase SC ladder
converter (with the output driven in one half-cycle only) presents very different transient
loading conditions1 in Φ1 vs. Φ2. CEFF and REFF represent an average loading valid at
low-frequencies only. For the 8-10 nF E-Field sensor application these passive
1 This imbalance can be largely addressed by use of a two-phase output architecture as discussed in
chapter four.
132
components can be replaced directly by the associated PZT load, as defined in Chapter
1. Considering the specified frequency range and values of CEFF, the pre-drive circuit
must drive peak capacitive load currents (in both directions) on the order of 240 μA for
sinusoidal signals (3*80uA) and 3.6mA for bandlimited square waves. The directly
driven PZT-based E-Field sensor calls for a peak sinusoidal current of about 2mA max
at 20kHz.
For this task it is assumed that a reference drive signal from a high-impedance
source is available with specifications easily duplicated using on-chip circuitry, i.e. from
a low-power DAC or a simple oscillator (as opposed to an off-chip 50Ω signal
generator); the drive capability must originate from the proposed pre-driver circuit. With
this view the pre-driver is effectively an efficient voltage buffer with high-input
impedance and low-drive resistance. Four major design features must be met
simultaneously for compatibility with system-level goals: 1. the driver’s output swing
must be nearly rail-to-rail; 2. the driver must be stable (from the standpoint of frequency
compensation) using minimal bias current for the specified range of CL values; 3. a
push/pull implementation is necessary for proper large signal behavior; and 4. for
enhanced battery life the driver should be designed in a manner that enables energy
recovery methods and class G/H efficiency improvement techniques (without inductors)
[31] [24]. For clarification, the actual implementation of these battery-life enhancement
methods (especially an on-chip version) is not the topic of this chapter but of future
work. The target here is to develop a circuit, without inductors, that includes the four
main features described and is compatible with a future implementation of such
schemes. The ultimate goal in a final implementation is charge/energy recycling
133
between CEFF and an as of yet undefined reservoir, perhaps the battery itself, to
minimize average battery current. It should be noted that this scheme is still lossy and
only a portion of the energy stored in CEFF is recoverable for reuse. To maximize overall
efficiency, resonant techniques [127], and/or a more typical class-D [128] [28] [129] or
class-E [130] approach is highly recommended for inductor compatible applications.
5.2 Choice of Design Direction
The pre-driver, whose output signal will be referred to as “VDRV” for the remaining
portion of this chapter, must both source and sink currents when driving the capacitive
load, closely following arbitrary voltage signals and forcing them across the low reactive
impedance. This point is illustrated in Figure 5-3, which represents the pre-driver or
buffer using a simplified Thevenin equivalent circuit.
Figure 5-3. Thevenin equivalent circuit representation of pre-driver.
RDRV is the effective output resistance of the driver and VTH the ideal unloaded
output drive waveform. CL is identical to CEFF for this discussion and the corresponding
load current IL is simply CL∙dVDRV/dt. Error in the desired VDRV signal should be
minimized and slewing should not take place. To meet these goals, RDRV should be low
and large signal bandwidth of the drive solution should include the max frequency of the
intended VDRV range. Specifically, if no slewing occurs, the system operates as a simple
RC low-pass filter with time constant τ = RDRV∙CL setting the 3dB frequency, above
134
which the drive speed is effectively limited. Because the value of CL is considered a
non-negotiable design specification, RDRV must be made small enough to meet the τ
constraint. With CL ≈ 8 nF, an RDRV < 200Ω is targeted allowing for an f3dB ≥ 100 kHz
and negligible phase shift in the desired signal band of 10k-20k Hz for the E-field sensor
application.
Rail-to-rail operation is desired to make best use of dynamic range and to reach
full capability of the SC ladder application. While external components are allowable for
driving the E-field sensor (see Chapter 1), none are allotted for use in the SC ladder
circuitry since it is intended for driving the piezo-wings of micro-robotic insects [19]; for
use in its final envisioned application, volume and mass are strictly limited to use of a
single IC and micro-battery [21] only.
A B
Figure 5-4. Output stages. A) Common-source and B) source-follower.
As a starting point, the standard common-source (CS) push-pull topology [86]
[46], shown in a simplified manner in Figure 5-4A along with an additional ground path
switch, is a strong contender for implementing the pre-driver. It can swing nearly rail-to-
135
rail and can source/sink current but has two drawbacks working against it here. Firstly,
with a large capacitive load being driven, we desire a drive scheme that allows for
recovery of charge (energy) during discharge; otherwise this charge is dumped to
ground making the overall system very inefficient. This recovery method must also have
minimal impact on signal integrity (waveform distortion, injection of noise, etc.). As
implied with the name of the CS topology, the source terminal is the "common" terminal
in the configuration and doesn't serve as the input or output. A recovery scheme might
then be considered that diverts the discharge current IDIS in the standard drive path
source connection of the NMOS “pull” device to an energy storage element, instead of
ground, as depicted with an ideal switch. However, since the MOSFET control voltage is
ultimately VGS as set by the A/B bias and drive circuitry, the source-voltage still plays a
pivotal role in controlling drive behavior. Any attempt to use this terminal has the
potential to disturb desired operation and impact signal quality; minimally it has potential
to limit output swing. Secondly, the effective open-loop output resistance of the CS
topology is the parallel combination of rop and ron, the small-signal output resistances of
the PMOS and NMOS output devices, respectively, assuming the hybrid pi model [86],
and is in general large for a given bias current. Feedback is typically applied to bring
this drive resistance down to acceptable levels.
The classic push-pull source-follower (SF) topology, depicted in Figure 5-4B, has
several topological advantages; for the same size devices, with the same bias current
and the same amount of local feedback as a comparable CS P-P stage, an SF output
stage displays an effective drive resistance decreased by a factor of ro/(1/gm) or gm*ro
(approximately ~100 for typically sized output devices). More importantly, the drain
136
connections are the common terminals and don’t play a major role in the drive behavior
(no impact on the primary control voltage, only through non-idealities such as channel-
length modulation is the output affected). Thus, the drain of the PMOS “pull” device is a
convenient point to apply an energy recovery scheme that diverts incoming current from
the load cap to an energy storage element, for direct reuse or indirectly back to the
battery, without significant degradation of the output voltage signal. This is supported by
the discrete (off-chip) piezo-driver scheme in [24]. The topology does, however, pose
challenges in terms of stability when driving a capacitive load [131] and typically
displays swings that are far from rail-to-rail. Overcoming these issues is a major part of
this work.
5.3 Bootstrapped Push-Pull Source-Follower for Rail-to-Rail Drive
In this work, a push-pull capacitive load driver is proposed that revisits use of an
SF output stage but with enhanced operation using isolated triple-well devices and a
pair of low-power self-bootstrapped local supplies for output swings comparable to CS
configurations within the same process node. A schematic of the circuit is provided in
Figure 5-5.
Two transconductance error amplifiers, for the push (OTA1) and pull (OTA2)
paths, provide shunt feedback to significantly decrease the already low intrinsic output
resistance of the SF output stage [132] [86]. Specifically, devices N7 and P7 are the
push and pull power devices, respectively. A translinear loop [46] of diode-connected
devices between the gates of the power devices (N8 and P8) ensures that only one
path (push or pull) is active at a given time and that very little bias current (class-AB) is
consumed in the power devices as shoot through. For this implementation, N8/P8
currents are set to nA levels by leaking currents between the OTA stages, implying
137
class-B operation. Furthermore, the combination of feedback with the translinear loop
forces the gate voltages of the power devices to follow each other, with a defined offset
of ~2∙|VGS|, even when one device is inactive.
Figure 5-5. Pre-driver prototype simplified schematic.
During normal operation, only one power device is appreciably active at a time,
but both OTAs can function simultaneously, their Gm contributions effectively adding
but their small-signal stage resistances loading each other (in parallel). In this way, the
system operates in an alternating “master/slave” configuration with the OTA of the
active path taking the lead role. To aid in this follower/leader behavior, the active-loads
138
of the OTAs (N5/N6 and P5/P6) are cascoded but the differential pair devices are not.
Thus, the small-signal output resistance (ro) of the differential pair devices, along with
their corresponding device transconductance (gm) values set the DC loop gain. RZ aids
in solving the stability issue with large CL, to be described subsequently in this chapter.
Table 5-1. Key device sizes
Function Device(s) W / L
Push FET N7 400/0.4
Pull FET P7 630/0.4 Diode N8 12.8/0.4 Diode P8 20/0.4
OTA1
N1,N2 20/1
P5,P6 40/0.8 P3,P4 10/0.35
OTA2
P1,P2 20/1
N5,N6 40/0.8
N3,N4 10/0.8
To keep operating power consumption as low as possible, while also maximizing
the gm/ID ratio [133], all devices operate in the subthreshold or weak-inversion regime
(aside from the Push and Pull power FETs under peak loading). Typical cascode
current sources/mirrors are used to decrease the number of current legs drawing from
the supplies, as opposed to the low-voltage “wide-swing“ cascode [101] that requires at
least one extra current leg for biasing. Tail currents for the OTAs are set to
approximately 1 μA (or 500nA per diff-pair device), and sizes for key devices are as
provided in Table 5-1. The translinear loop diodes N8 and P8 are scaled by a factor of
~30x with respect to their corresponding (N7 or P7) power device, as a balance
between matching and power consumption.
A unique feature of the driver is a supply bootstrapping technique that is both
highly integrated and more simple than some previously published methods [134] [135],
139
while providing boosted positive and negative (inverted) supply voltages that track the
output signal VDRV (or more precisely internal node VO). Functioning as a self-clocked
signal-frequency charge-pump, simplified waveforms for the proposed technique are
illustrated in Figure 5-6.
Figure 5-6. Waveforms depicting bootstrapped supply scheme.
Ignoring diode voltage drop VD, one bootstrapped supply is above the output
VDRV by ~VDD (referred to as VBTS-POS), peaking at ~2VDD; the other is below the output
by ~VDD (VBTS-NEG), reaching nearly one VDD below the substrate potential when the
output is at 0V. These supplies provide ~5uW each to the low-power error amplifiers
(OTAs) employed to drive the high-impedance gates of the push-pull power transistors
(the VHiZ-PUSH and VHIZ-PULL nodes, respectively). In addition to reducing output
resistance with shunt feedback, as previously explained, the gate voltages can go
above or below ground as needed for proper |VGS| control values and nearly rail-to-rail
drive, without the usual clipping which would occur with static supplies. At the same
time, the moving positive and negative voltage domains stay limited in magnitude to
VDD=3.3V, keeping devices safely within process voltage limits. The HiZ gate drive
140
nodes, shown in more detail in the simulation results of Figure 5-7, stay within a |VGS|
from VDRV ≈ VO at all times as set by the active primary feedback loop, alternating
between push or pull.
Figure 5-7. Simulated periodic steady-state waveforms using BSIM3v3 models.
It is important to recall that VDRV would ultimately act as VIN to the SC ladder
converter of Chapter 3 or would directly drive the described E-field sensor actuator,
represented by CL. Assume CL is initially discharged at start-up with application of VDD.
CBOOT1 then begins charging through on-chip diode D1 and positive bootstrapped supply
VBTS,POS sits one diode drop down from VDD. With application of rising VREF, the partially
functioning pre-driver begins charging CL through the push path and VO rises, current
flows outward through RZ and VDRV follows. Eventually VDRV (actually VO) is higher than
a diode drop such that CBOOT2 (initially discharged) begins charging through integrated
diode D2.
141
A
B
C
D
Figure 5-8. Simulated start-up operation for pre-driver. A) Primary voltage waveforms, B) bootstrap capacitor voltages and VDD, C) bootstrap capacitor currents, and D) power device (Push and Pull) currents.
The system is designed to bias properly with a static input value of VREF = VDD/2 =
VDRV (and only partially charged bootstrapping capacitors) but is only fully functional
142
with dynamic operation. Once an appropriately varying waveform is applied (in addition
to the bias), only a few signal periods are needed to charge CBOOT1 and CBOOT2 to their
peak levels, approaching VDD, allowing them to function as boosted (positive) and
inverted (negative) local supplies that recharge themselves naturally each cycle.
For example, simulated start-up operation is shown in detail in Figure 5-8 parts A
through D. VDD is ramped to 3.3V in 50μs, as displayed in Figure 5-8B. Also included
are voltages stored on the CBOOT1 and CBOOT2 bootstrapping capacitors, VCBOOT1 and
VCBOOT2, respectively.
At 100μs, VREF, the green signal shown in Figure 5-8A, is ramped to its bias
voltage value (VDD/2) and stays idle until dynamic operation begins at 0.3 ms with
application of a 10 kHz rail-to-rail sinusoid. VO tracks VREF almost immediately (they
essentially overlap) and diode-based charging of the CBOOT capacitors takes place, as
supported by the current waveforms in Figure 5-8C and 5-8D.
A
B
Figure 5-9. CBOOT waveforms in periodic steady-state. A) Voltage and B) current.
143
The bootstrapped supplies reach a periodic steady-state in about three or four
cycles, requiring only small ripple currents for CBOOT1 and CBOOT2. Details are shown in
the “zoomed” simulation results of Figure 5-9.
A B
Figure 5-10. Compatible efficiency improvement schemes. A) Class-G and B) energy recovery and recycling.
Each bootstrapped supply is loaded only by the total ~2.25 μA for the OTAs and
associated mirror. The push and pull power paths are separate from the bootstrapped
circuitry (see VDD-PWR and VSS-PWR) allowing for rail-to-rail VDRV (but not above or below
the supply). Since these supplies are the drain connections to the SF power devices,
these voltages can largely change as desired (as long as the active power device
remains in the MOS saturation region or in sub-threshold), making way for an eventual
class-G or charge ”recovery + recycling” scheme in a final solution or off-chip prototype.
144
Figure 5-10 illustrates the compatibility of these efficiency improvement techniques with
the pre-driver using a simplified representation of the circuit.
Figure 5-11. Bias distribution block with shielding devices.
The proposed design method does come with additional risk. Careful attention to
n-well and isolated p-well bias connections is necessary for the bootstrapped internal
nodes to avoid latch-up [123] and/or limited output swing for devices within the
bootstrapped voltage domains, especially those operating below ground potential.
Furthermore, precautions are necessary to ensure devices within a given voltage
domain and especially those at the interfaces between two domains (namely the IB,P
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and IB,N current sources in Figure 5-4) have oxide voltages that never exceed the
process rating. The increased potentials from bootstrapping must be safely divided over
several devices. For example, in the schematic of the bias distribution block of Figure 5-
11, stacked shielding devices (cascodes) were added for protection.
An additional challenge is ensuring that charge injected through the on-chip
diodes does not get collected elsewhere on the chip, infiltrating sensitive circuitry and
causing undesired behavior. Potentially, these issues can be overcome with thoughtful
bias connections for each and every well (N-well, triple-well) and generous use of guard
rings in the layout using an abundance of contacts, taking similar safeguards as in
inverting charge-pump circuits [136].
Figure 5-12 parts A through C show a detailed implementation of integrated
PMOS diode D1, which operates above the supply voltage. The desired behavior for
charging the bootstrap capacitor during the “on” state is activation of the FET by
enhancing the channel (|VGS| > |VTH|), as set by signal frequency fIN, device sizing,
current source loading level (the μA OTA currents), and CBOOT capacitance. In addition
to the MOS device itself, a parasitic PNP exists with two effective collectors as shown in
Figure 5-12B. If the source-gate voltage is large enough, the parasitic PNP will also
activate: its emitter-base junction, formed by the PMOS source and bulk (N-well)
connections, is “on”. In this case the emitter current (through the source connection of
the PMOS) will be split between the two collectors. The preferred path is the collector
formed by the drain/bulk connection since it actually feeds charge to the capacitor top
plate as part of the “anode”. The second collector is formed by the p-sub ground, a path
that represents charge loss. Since the existence of this secondary collector is
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unavoidable, measures should be taken during layout to minimize this loss of charge
and to protect surrounding circuitry that might subsequently absorb the charge,
interfering with intended operation. Specifically, N+ contacts must be closely placed
near the P+ source connection and it may be advisable for N-well spacing to be made
larger than minimum and to include addition of P+ guard rings in the N-well, at the
expense of increased parasitic capacitance. A cross-section is shown in Figure 5-12C.
A B D E
C F Figure 5-12. Implementation of integrated MOS diodes. A) Diode D1 equivalents, B)
Parasitic BJT for diode D1, C) Device cross-section for D1, D) Diode D2 equivalents, E) Parasitic BJTs for diode D2, F) Device cross-section for D2.
NMOS diode D2 is designed similarly to PMOS D1 but operates at negative
voltages below substrate potential, as detailed in Figure 5-12 parts D through F. When
the anode connection is above ground (the effective cathode of the diode), the desired
behavior is activation of the diode connected NMOS with VGS > VTH. This is the “on”
state for D2. Considering the conventions for the BJT symbols as drawn in Figure 5-
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12E, if VGS of the NMOS grows large enough, either or both of the parasitic NPN base-
emitter junctions will also be activated, forming diode connected BJTs in the forward-
active region. Furthermore, the parasitic PNP may also contribute, acting as a diode
connected BJT operating in the reverse active region. Since all of these currents are
flowing from the “anode” and are then directed to ground (the desired “cathode”
connection), desired rectifier behavior should not be significantly impacted. However,
guard rings should be included in the layout to avoid disturbing the operation of
surrounding circuitry by charges injected into the substrate.
During the desired “off” state for D2, when the anode is at ground potential or
below, the NPN structure operates, if at all, in the reverse active region. Current can
only flow if the base-collector junction (replacing the role of the usual base-emitter
junction) is activated; specifically, only if the bulk to drain voltage is above several
hundred mV can current flow (backwards) through the NPN. Since these terminals are
shorted, the NPN should remain in cutoff. The PNP structure, through inspection, also
operates in cutoff; its base-emitter junction is shorted and no current flows through it,
even with the bulk connection dropping well below ground. This description assumes
that the wires, as drawn, are implemented with negligibly low impedance. Otherwise, it
is possible to activate one of several parasitic SCR structures during a transient,
causing latch-up [101]. Also, it should be noted that designations such as “forward
active” and “reverse active” regions of operation are arbitrary here, based only on the
taken directions for the symbol connections (chosen to aid in understanding circuit
behavior); no account of doping concentrations is assumed here (i.e. the emitter is
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usually more highly doped than the collector, etc.) since these are parasitic devices and
if possible would have been avoided altogether.
A B
C
Figure 5-13. NMOS current-mirror operating below substrate potential. A) Schematic, B) parasitic BJTs, and C) cross-section.
A similar thought process is required for ensuring properly operating current-
mirrors either above the VDD supply voltage or below substrate potential. Figures 5-13
and 5-14 show detailed connections for the mirrors operating in the bootstrapped driver
circuit.
The most significant remaining challenge, frequency stability with large CL and
with the requirement of minimal power dissipation, is the subject of the next sub-section
of this chapter.
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A B
C Figure 5-14. PMOS current-mirror operating above supply potential. A) Schematic, B)
parasitic BJTs and C) cross-section.
5.4 Feedback Stability and Frequency Compensation
The choice of an SF-based push-pull output stage provides several topological
advantages for this application as covered in the previous sub-sections of this chapter.
However, the SF is prone to ringing or even oscillation when driving a capacitive load,
characterized by a low phase margin for the feedback loop(s) [131], unless specific
actions are taken otherwise (some form of frequency compensation [46]). A simple
conceptual explanation of this phenomenon can be understood by considering the
frequency dependence of the SF’s output impedance (for a single device) before
feedback is applied. At low frequencies it is essentially 1/gm [86] but as the frequency
increases the output impedance rises with it; it is thus inductive in nature [137]. This
inductive impedance interacts with the capacitive load causing a damped resonance
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and the application of feedback around the SF exacerbates the situation. To gain insight
into solving the problem a design-oriented analysis [138] [139] was conducted using a
simplified view of the pre-driver.
Figure 5-15. Simplified view of pre-driver for stability analysis.
As shown in Figure 5-15, the NMOS push path feedback loop was first analyzed
in isolation with the assumption that, like standard follower-based opamps as described
in [140], a stabilizing zero could be added to counteract an unwanted pole (the role of
RZERO, which works in opposition to small RDRV). The small-signal model used for loop-
gain analysis is provided in Figure 5-16 and is essentially identical for both the push and
pull loops.
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Figure 5-16. Small-signal model for loop analysis.
To find an expression for the loop-gain T (or, perhaps more accurately the return-
ratio [132]), VREF is made inactive (becomes ground potential), the feedback loop was
broken as shown and a test signal was applied at the IN- node (such that T=VO/IN-).
After some algebra and practical simplifying assumptions, an expression for T was
found. Specifically, with RZ << RL, RZ << RO, gm7RL >> 1, gm7RZ << 1 and CL >>
CGS(1+RO/RL), then
𝑇 = 𝑇𝐷𝐶 ∙(1+𝑠
𝐶𝐺𝑆𝑔𝑚7
)∙(1+𝑠𝑅𝑍𝐶𝐿)
𝑠2(𝑅𝑂𝐶𝐿(𝐶𝐺𝑆𝑔𝑚7
+𝑅𝑍𝐶𝐺𝐷))+𝑠(𝐶𝐿
𝑔𝑚7+𝑅𝑂𝐶𝐺𝐷)+1
(5-1),
where TDC≈GM∙RO.
After factoring and simplifying the denominator the pole locations are
𝑠1,2 =−1
2𝑅𝑂(𝐶𝐺𝑆+𝐶𝐺𝐷𝑔𝑚7𝑅𝑍)∙ [1 ∓ √1 −
4𝑔𝑚7𝑅𝑂𝐶𝐿𝐶𝐺𝑆
(𝐶𝐿+𝑔𝑚7𝑅𝑂𝐶𝐺𝐷)2 ] (5-2).
The expression may appear cumbersome but important conclusions can be made to
direct design decisions. First, it should be noted that in the analysis any parasitic
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capacitances at the source node (before RZ, at node VO) due to differential pair input
capacitance, loading by the pull network, etc., have been ignored as have the
unavoidable “mirror-poles” of the OTAs [131]. These contributors should be minimized
in design but are accounted for in simulation at the transistor level. While important,
their inclusion clouds the intents of the proposed design method. Under the above
simplifying conditions, the gain of the loop can be represented with two left-half plane
(LFP) poles and two LFP zeros and a DC gain term, as shown. Three stability
compensation strategies (at least) can be deduced from the loop-gain expression and
are compared below.
If gm7 were made extremely large, at the expense of excessive bias current, and
RZ removed (made 0Ω), the system would simplify to a single pole (due to Ro and CGD,
which essentially then acts as a compensation capacitor), without any zeros. It would
then be inherently stable with a phase margin of nearly 90°, effectively employing
dominant-pole compensation. In a practical design application (but one not requiring
minimal power consumption) a compensation capacitor could be directly added in
parallel with CGD to approximate this scenario in a robust manner.
Alternatively, if CGS (and CGD) could be made negligibly small, an unlikely
scenario in practice, a similar outcome would result. Specifically, the system would
again have only one pole and one zero, the zero itself due only to the addition of RZ and
the pole due to the interaction of the load capacitor and the resistance looking into the
source terminal (1/gm5). Under this condition, the system would have large bandwidth
and would still remain stable with RZ=0, implying dominant pole compensation at the
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output node. The zero could then be removed altogether, resulting in minimal added
drive resistance.
The approach taken here, an attempt to minimize power consumption while
meeting system-level requirements (nearly rail-to-rail, low closed-loop drive resistance),
is to minimize gm5 and to take advantage of the zero resulting from use of RZ (on the
order of 50 – 100 Ω, as will be shown) for stability of the output stage. Total RDRV (the
buffer’s ROUT, accounting for feedback, plus RZ) should still remain safely below the
200Ω target. A global loop, which must also be stable, could then be applied to
introduce additional shunt-feedback such that the overall drive resistance is decreased
considerably (to ≈ 1Ω). Moreover, during instances of large output current, the value of
RZ could be modified to dynamically track the momentary increase in gm5, increasing
the effective drive capability and slew-rate of the pre-driver. (For the fabricated
prototype, presented later in the chapter, these optional enhancements were not added
and likely not needed.) The actual choice of gm and RZ, as well as the effective value of
the remaining variables, will be “tuned” during accurate transistor level simulation.
To confirm the validity of the hand analysis (and associated assumptions) an
actual top-level transient simulation was run on a schematic including bond-wire
inductances and realistic external contributors. At four different transient time points,
when VO was at its minimum (1), at its maximum (2) and during falling (3) and rising (4)
points at mid-rail, STB simulations were run to gauge frequency stability. Noting the
apparent multi-loop nature of the circuit, it is important to place the STB probe at a point
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that breaks all loops simultaneously.2 This is illustrated in the simplified schematic of
Figure 5-17 with modified CBOOT connections (originals are in gray, dotted). In addition
to the main Push and Pull feedback loops, the bootstrapped supplies themselves are a
form of (positive) feedback. While these two supply loops (BTS,POS and BTS,NEG)
only weakly contribute to operation, ostensibly by modifying the effective impedance of
the active loads and current mirrors, the STB results do not seem trustworthy (loop
gains are exceedingly high or low) without them being “broken” in the proper manner.
Figure 5-17. Simplified schematic showing STB probe placement and four feedback loops.
2 In a true multi-loop feedback system, it is not possible to break all loops simultaneously. Assessment of
loop stability, even via simulation, becomes exceedingly more complex [165]
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The results of the described STB simulations are summarized in Figure 5-18
with part A showing loop-gain magnitude and part B the phase. Also included, for
comparison, is a plot of the loop-transfer function as calculated using Eq. (5-1) for one
transient operating point only (when the push NMOS is fully active and the PMOS off, or
equivalently when VO is mid-swing and rising).
A
B
Figure 5-18. STB simulation results at four transient operating points. A) Loop-gain magnitude and B) loop-gain phase.
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Parameter values for gm7, etc. were taken from the actual simulation using
BSIM3V3 models (see Table 5-2). The resulting simulated and calculated curves closely
resemble each other in terms of magnitude and are acceptably close in terms of
predicted phase response. Embedded into the phase plot is a table displaying the
phase-margin for each condition, with a worst-case value of 55° during a lull in load
current (very little current flowing through either power device). The hand-calculated
phase-margin is optimistic but generally captures key behavior. If a better aligned
phase-plot is required for accuracy, an additional pole at ~15-20MHz can be added and
is presumably a mirror-pole or represents the unaccounted capacitance at the gates of
the OTA diff-pair inverting-inputs. To check sensitivity with respect to RZ, if 50Ω is used
instead of the original 100Ω and all other conditions the same, then the simulated phase
margins for the four transient operating points are 30°, 52.6°, 56.9°, 75.1°, respectively,
with corresponding loop bandwidths of 230k, 309k, 690k, and 1.9M Hz.
Table 5-2. Extracted parameters for hand calculation
Parameter Value
Gm = gmN2 11.1 μS
RO = ro,N2 36 MΩ
CGS 507 fF
CGD 115 fF
gm7 14.1 mS
RZ 100Ω
CL 10 nF
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5.5 Measurement Results
A prototype of the SF-based bootstrapped driver, die photo in Figure 5-19, was
fabricated in a 1.2V/3.3V 0.13um triple-well CMOS process (with substrate-to-N-well
breakdown of ~10V). Primarily targeting the E-field sensor application, the prototype
utilizes two off-chip bootstrapping capacitors (typically 10 nF range) and RZ of 50-100Ω,
currently off-chip for flexibility in testing but easily integrated on-chip in the future. For a
final Micro-Flyer-dedicated version, the diode-based bootstrapping scheme (which
requires the external capacitors) would have to be replaced by a fully-integrated
alternative (presumably a compact charge-pump sub-block). For now, to mimic this
situation, extremely large off-chip capacitors in the μF range can be used to
appropriately bootstrap the supplies at frequencies between 50-500Hz for
measurements emulating the Micro-Flyer loading, although the diodes were not
originally sized for this range of CBOOT.
Figure 5-19. Die photo of pre-driver prototype.
For this Micro-Flyer emulation setup using a 50nF CL capacitance, Figure 5-20
shows the measurements of the properly operating prototype when only a DC bias at
mid-rail is applied to VREF. VDRV and VREF are essentially equal, no oscillation is visible,
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and VBTS,POS and VBTS,NEG are each a diode drop away from their respective supply
connections.
Figure 5-20. Properly functioning DC bias condition.
In Figure 5-21 a dynamic signal is shown as applied to VREF, in this case a 70Hz
rail-to-rail sinewave (the resonant frequency of the measured Micro-Flyer from Chapter
3), and the circuit operates appropriately. Although waveform distortion is visible, the
Micro-Flyer actuator and wing represent a high-Q system which should largely reject
harmonics outside the resonance band. Furthermore, as will be explained in Chapter 6
on “future work”, the fully-integrated bootstrapping scheme would likely be based on
local charge-pumps, using similar techniques as those described in Chapter 4. The self-
clocked diode-capacitor-based method proposed here is primarily for the E-Field
sensor, which recharges the capacitors in a signal dependent manner (at each peak in
the waveform) through a non-linear device. A charge-pump based bootstrapped supply
would be recharged at a much higher rate not directly related to the signal, which should
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result in lower distortion. This, of course, comes with more complexity than in the
currently employed method.
Figure 5-21. Proper operation while emulating Micro-Flyer application.
Even though the diode-based supply bootstrapping scheme for the pre-driver
prototype is incompatible with a final combined solution, for added credibility the CBOOT
= 47 μF setup was used to drive the original (Chapter 3) SC ladder 3x step-up
“amplifier” circuit along with the Micro-Flyer wing load. This amounts to a “Task 1” +
“Task 2” measurement, which is provided in Figure 5-22. Resistor RZ = 50Ω, clock
frequency fSW = 500kHz, and fIN = 69Hz (for resonance of the piezo-actuator). The
actuator voltage is labeled “VPZT” in the figure, peaking at ~8.7V for a peak VREF of 3V.
Also provided are the positive and negative bootstrapped supply voltages, VBTS,POS and
VBTS,NEG, to illustrate suitable pre-driver behavior. As shown, VBTS,POS peaks above the
VREF waveform by about 2.7V and, similarly, VBTS,NEG operates properly below ground.
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Figure 5-22. Combined measurement using all three prototypes: pre-driver (Chapter 5), SC ladder step-up (Chapter 3), and ARL Micro-Flyer PZT Wing.
The primary target for this prototype is the E-field sensor actuator driver
application described in Chapter 1. In this case, sinusoidal signals in the 10k-20k Hz
range (nominally 13 kHz) are needed to drive an 8-10 nF effective load. Measurements
emulating these conditions are provided in Figure 5-23 (for nominal 13 kHz operation)
and Figure 5-24A and 5-24B for 10 kHz and 20 kHz operation, respectively.
Figure 5-23. Proper operation while emulating E-field sensor application (fIN=13kHz).
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As in the Micro-Flyer emulation setup, cross-over distortion is apparent when the
waveform nears the rails (the points where capacitive load current is ~0μA but the
CBOOT capacitors charge through the D1 and D2); this is an expected consequence of
class-B operation, as designed, and is considered an acceptable trade-off to minimize
the driver’s power consumption. If this distortion is not satisfactorily rejected by the high-
Q nature of the E-field sensor actuator, then a class-AB approach (with associated
power penalty) could be used instead. This could presumably be implemented by
modifying the translinear loop in Figure 5-5 (transistors N7, P7, N8 and P8) to conduct
more current [86]. Additionally, a replica channel of the driver could be used exclusively
for bootstrapping the supplies, leaving a dedicated class-AB driver channel for the E-
field sensor.
Figure 5-24. Measured driver operation. A) 10kHz waveforms and B) 20kHz waveforms.
In all cases the current efficiency of the driver (ILOAD/ISUPPLY) is extremely high. As
an example, at 10kHz with a 10nF load, the total average supply current is about 320μA
while the average current spent directly on the bootstrapped driver is on the order of 5
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to 10 μA (~1 μA statically, 2.25 μA through each CBOOT, plus diode charging losses), for
a current efficiency of ~97%.
Figure 5-25. Measured total supply current vs. waveform frequency.
Measured total supply current is plotted in Figure 3-25 versus waveform
frequency. Also plotted are two dotted gray lines representing an ideal calculated supply
current (vs. frequency) for load capacitors of 10nF +/- 5%3, assuming an ideal driver
costing zero added current draw. The added “cost” of the real driver is almost
indistinguishable from the ideal case with the measured supply current falling in
between the idealized scenarios.
3The specified tolerance of many COTS components, and the example used for the measurement.
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5.6 Conclusions for Chapter 5
A highly integrated and current-efficient capacitive load driver design method was
proposed in this chapter to meet the primary requirements of “Task 2”, as defined in
Chapter 1. The SC ladder step-up drive stage of Chapters 3 and 4 (comprising “Task 1”)
presents a low and primarily capacitive impedance to preceding circuitry. An alternative
application, a low-voltage piezo-actuator based E-field sensor, is itself capacitive in
nature. Chapter 5 details a rail-to-rail class-B topology, enabled by a simple
bootstrapping technique, meeting the major design requirements for both applications,
as supported by simulations and measurement of a prototype. Namely, while driving
capacitive loads in the range of 8nF to 50nF, sourcing and sinking mA level currents,
the driver is free of oscillation and follows rail-to-rail input signals. Furthermore, the
topology is compatible with energy-saving schemes that can recover energy from the
capacitive load while requiring only micro-watt power levels to operate. If even a fraction
of the energy typically dissipated while driving a nF-range capacitive load (on the order
of mW with 3.3V swings at 10k-20k Hz) can be recovered4, then the ≤ 30μW solution is
essentially “cost free” from a power standpoint and “pays for itself”.
4 Assuming availability of a 1.2V “digital” supply in addition to the main VDD = 3.3V, system level energy
recovery/reuse simulations show an approximate 30% savings on a ~1mW average supply power without overly complex additional circuitry (a promising ~300μW saved vs. a ≤ 30μW Pre-Driver circuit). A suitable lab measurement is part of “future work” and not included in this PhD Dissertation.
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CHAPTER 6 SUMMARY AND FUTURE WORK
6.1 Summary
This dissertation discusses steps towards the design and implementation of a
fully-integrated piezo driver solution for the ARL Micro-Flyer with 2mm PZT wings. The
application calls for 0-9.9V arbitrary drive waveforms from DC-500 Hz with bidirectional
load currents and use of a nominal 3.3V supply voltage. A lack of compatible inductors,
particularly, motivates research for new methods in meeting the simultaneous demands
of extremely small size, limited available power, and high output voltage relative to
related battery technologies and standard CMOS process flows. The primary focus of
this work is the investigation of circuit bootstrapping techniques for distributing the drive
voltage over several devices while keeping MOS switch devices safely toggling
throughout the whole output range with nearly constant drive strength and opening up
the possibility of efficiency enhancement techniques and charge recovery from the
capacitive load. A secondary application, drive of a 3.3V 8nF PZT-based e-field sensor
with 10k-20k Hz waveforms, is also targeted.
As a balance between integration and voltage handling capability a 0.13 μm
triple-well 1.2V/3.3V CMOS technology (with ~10V NW-sub breakdown voltage) was
chosen. The overall goal has been split into two key tasks. “Task 1”: Safe creation of 0-
9.9V HV output signal on chip without external components while assuming availability
of a low-voltage (between the rails) input waveform with suitably low drive resistance.
“Task 2”: the development of a circuit to efficiently act as this “pre-drive” circuit, without
inductors, feeding the HV driver and providing the low-voltage waveform. The proposed
design techniques are of a general nature and applicable to a wide range of circuit
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applications requiring drive of capacitive loads with moderate (rail-to-rail) and high
(above both the supply and device rating) voltage signals in an oxide voltage limited
CMOS process.
Specifically, in Task 1 use of the SC ladder converter as a switched-mode step-
up amplifier has been proposed along with a voltage-compliant gate-drive technique.
Clock signals track the slowly varying input VIN and its multiple 2∙VIN, peaking at 3*VDD
or 9.9V, while keeping power switch resistance nearly constant over the whole output
range (0-9.9V) and oxide voltages safely limited to 3.3V for safe bidirectional drive of
capacitive loads. In the work presented in Chapter 3, these signals are created using
several instances of a proposed circuit called the Nested-Bootstrapped Switch (NBS)
cell. This “Task 1” circuit has been fabricated, proven in bench tests and was
demonstrated as a driver for a 4nF 10V 2mm wing prototype with a standard 50Ω signal
generator as the low-voltage input drive signal (playing the role of the pre-driver). A
summary of this work was published in [19] and later detailed in [113].
Chapter 4 documents the results of an investigation into enhancing the primary
“Task 1” circuitry initially presented in Chapter 3. A prototype implementing these
proposed improvements has not been created due to time constraints but detailed
simulations serve to verify the key concepts. Namely, it should be possible to fit two
copies of the resulting “Compact Dual-Phase SC ladder Drive Stage” in the same area
of the original with little or no penalty in performance.
Chapter 5 details the design of a pre-driver prototype for “Task 2”. The SC
switched-mode amplifier of Task 1 presents a large equivalent capacitive load (CEFF) to
the preceding circuit, but stays within the “low” voltage domain (between 0V and the
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3.3V supply). Thus, a rail-to-rail bootstrapped source-follower buffer has been
introduced to allow for efficiency enhancement techniques and charge recovery as
opposed to the more standard common-source topologies. One challenge in this
implementation is the existence of routine on-chip voltages that operate below ground
(substrate) potential and above the 3.3V positive supply, making latch-up and leakage
effects a concern. Significant precautions were taken in the planning and layout stages
to alleviate this risk and verified by simulation before fabrication. A prototype in the
0.13μm CMOS process has been measured, proving the validity of the design method.
A publication submission is planned for the near future.
6.2 Future Work
The research presented in this dissertation provides a solid framework towards a
complete solution for driving the Micro-Flyer wing prototype using bootstrapping
concepts and low-power switched capacitor circuits. The proposed techniques are also
applicable to a wide variety of circuits interacting with capacitive loads. Future work
primarily consists of combining the proven ideas for Tasks 1 and 2 into a single united
prototype. Figure 6-1 illustrates the most fundamental combination of pre-driver and
step-up drive stage. Wing actuator load capacitance is labeled CACT.
The step-up stage, as drawn, would include the enhancements described in
Chapter 4. Instead of the diode-capacitor scheme of Chapter 5, the OTAs in the Pre-
driver block are powered by small local charge-pumps that track the VO output signal,
one of positive polarity creating VBTSPOS and one operating below ground (“negative”)
creating VBTS,NEG. Due to the existence of the main SC ladder (also a “charge-pump”),
clock reference signals are already available and added overhead is low. Because the
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OTAs draw constant currents in the low μA range, the local BTS charge-pumps would
likely operate properly using capacitors in the 10 – 100 pF range, total, contributing
negligibly to chip area.
Figure 6-1. Diagram showing combined solution: pre-driver, local BTS charge-pumps and compact dual-phase step-up drive stage.
For an optimum implementation, the values of RZ and the switch resistances of
the first ladder stage (whose values add when charging the main flying capacitors)
should be designed jointly for a balance of efficiency of the SC ladder and stability of the
pre-driver. If variation is a concern, the value of RZ can be trimmed using standard
procedures [141]. Depending on distortion requirements, the pre-driver could be
modified for class-AB rather than class-B operation. Finally, two channels should be
included in the combined layout, one for “stroke” actuation and the other for “pitch” and
a complete solution would require an on-board oscillator [142] [143] and low-power
digital waveform synthesizer [144].
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Figure 6-2. Preliminary simulation results for the block diagram of Figure 6-1.
For added confidence in the design method, a first-pass version of the block
diagram in Figure 6-1 has been simulated at the transistor level using BSIM3v3 models
from the foundry but with ideal clock generation blocks, as presented in Figure 6-2.
Actuator capacitor CACT is set to 2nF and fIN = 500Hz. The bootstrapped supplies for the
pre-driver block, which is otherwise identical in design to the measured Chapter 5
circuit, are implemented with fully-integrated small local charge-pumps whose ripple is
made apparent by slightly thicker lines for the VBTSPOS and VBTSNEG signals during times
of maximum rise or fall; the voltage-drop of the diode-based method is no longer
observed. The step-up drive stage based on the compact dual-phase SC ladder of
Chapter 4 (same sizing, etc.) exhibits similar simulated performance of 9.7V peak
output with fSW = 1MHz, amounting to performance characterized by an ROUT of ~ 40kΩ.
While the ripple associated with the local BTS charge-pumps is also visible in the VDRV
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waveform, the low-pass nature of ROUT interacting with CACT filters it from the primary
VACT waveform.
Figure 6-3. Schematic with potential system-level augmentations.
System-level augmentations could also be investigated, as depicted in the
examples of Figure 6-3, and their benefits versus costs analyzed. Within the pre-driver
block, OTA3 monitors VDRV on the opposite side of RZ and applies supplementary shunt
feedback to further decrease the drive resistance. The output of the Compact Ladder
step-up stage, VACT, could also be better controlled with a dedicated and additional
global voltage feedback loop, represented by OTA4. Finally, the frequency fSW of clock
signal CLK could be set by either feed-forward (as depicted) or feedback impacting
ROUT “on-the-fly” but also allowing for significant reduction of dynamic power
consumption. The predominant challenge with applying any or all of these potential
improvements is the daunting task of ensuring system stability while holding power
consumption and solution size to a minimum. Moreover, the VDD-PWR and VSS-PWR
connections of the pre-driver are flexible and can be connected, when appropriate, to
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recover energy from CACT, to reshuffle energy between the two channels, or to aid in
powering the 1.2V digital “brain” of a more mature prototype insect.
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186
BIOGRAPHICAL SKETCH
Christopher Dougherty grew up in Florida and is from the Tampa Bay area. He
received the B.S. and M.S. degrees in electrical and computer engineering from the
University of Florida (UF) in 2008 and 2010, respectively. From 2008-2012 he was a
Research Assistant with the UF Integrated Circuits Research Lab while working as a
full-time PhD student. After taking leave for several Co-op terms with Texas
Instruments, in 2013 he joined Texas Instruments Deutschland GmbH in Freising,
Germany, as an Analog Design Engineer within the Precision Analog business unit,
meanwhile continuing as a part-time PhD student with the University of Florida. His
research interests include low-power and high-precision design techniques for CMOS
integrated circuits, feedback theory, and audio processing.
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