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Irene Fidone - Marco Bacis - Lara Cavinato -

Rationale behind FPGA

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Irene Fidone - Marco Bacis - Lara Cavinato -

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10X

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● Lower cost of development in respect to ASIC

● Adaptability of applied filters/analysis

● Reconfiguration for newer/different interfaces

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Politecnico di Milano, NECST lab for Xilinx Open Hardware Contest 2016 #XOHW16