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An easy approach for designing combinational circuit including 7- Segment display and Adders.
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Combinational 7 segment, comparator and Adder circuit
Digital Logic Design
7-Segment Display
a
b
c
d
e
f
g
Inputs Output
A B C D a
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
Inputs Output
A B C D a
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
Function Table for Segment ‘a’
Inputs Output
A B C D b
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
Inputs Output
A B C D b
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
Function Table for Segment ‘b’
Inputs Output
A B C D c
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
Inputs Output
A B C D c
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
Function Table for Segment ‘c’
Inputs Output
A B C D d
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
Inputs Output
A B C D d
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
Function Table for Segment ‘d’
Inputs Output
A B C D e
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
Inputs Output
A B C D e
1 0 0 0 1
1 0 0 1 0
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
Function Table for Segment ‘e’
Inputs Output
A B C D f
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
Inputs Output
A B C D f
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
Function Table for Segment ‘f’
Inputs Output
A B C D g
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
Inputs Output
A B C D g
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
Function Table for Segment ‘g’
Karnaugh Map for Segment ‘a’
AB\CD 00 01 11 10
00 1 0 1 1
01 0 1 1 1
11 x x x x
10 1 1 x x
DBBDCA
Karnaugh Map for Segment ‘b’
AB\CD 00 01 11 10
00 1 1 1 1
01 1 0 1 0
11 x x x x
10 1 1 x x
CDDCB
Karnaugh Map for Segment ‘c’
AB\CD 00 01 11 10
00 1 1 1 0
01 1 1 1 1
11 x x x x
10 1 1 x x
BDC
Karnaugh Map for Segment ‘d’
AB\CD 00 01 11 10
00 1 0 1 1
01 0 1 0 1
11 x x x x
10 1 1 x x
DCBDCCBDBA
Karnaugh Map for Segment ‘e’
AB\CD 00 01 11 10
00 1 0 0 1
01 0 0 0 1
11 x x x x
10 1 0 x x
DCDB
Karnaugh Map for Segment ‘f’
AB\CD 00 01 11 10
00 1 0 0 0
01 1 1 0 1
11 x x x x
10 1 1 x x
DBCBDCB
Karnaugh Map for Segment ‘g’
AB\CD 00 01 11 10
00 0 0 1 1
01 1 1 0 1
11 x x x x
10 1 1 x x
CBDCCBA
7-Segment Circuit
ab
cd
e
f gLogicCircuit
4-bitBCDinput
7-segmentoutput
Comparator Circuit
• Inputs two 2-bit binary numbers A and B• Has three outputs• A>B • A=B• A<B
Inputs Output
A1 A0 B1 B0 A>B
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
Inputs Output
A1 A0 B1 B0 A>B
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
Function Table for A>B
Inputs Output
A1 A0 B1 B0 A=B
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
Inputs Output
A1 A0 B1 B0 A=B
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Function Table for A=B
Inputs Output
A1 A0 B1 B0 A<B
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
Inputs Output
A1 A0 B1 B0 A<B
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
Function Table for A<B
Karnaugh Map for A>B
A1A0/B1B0
00 01 11 10
00 0 0 0 0
01 1 0 0 0
11 1 1 0 1
10 1 1 0 0
00101011 BAABBABA
Karnaugh Map for A=B
A1A0/B1B0
00 01 11 10
00 1 0 0 0
01 0 1 0 0
11 0 0 1 0
10 0 0 0 1
0101010101010101 BBAABBAABBAABBAA
Karnaugh Map for A<B
A1A0/B1B0
00 01 11 10
00 0 1 1 1
01 0 0 1 1
11 0 0 0 0
10 0 0 1 0
01000111 BBABAABA
Half & Full Adders
A
B
Cout
Inpu
t Bits
Out
put B
its
Half-Adder
A
B
Cin
CoutIn
put B
its
Out
put B
its
Full-Adder
Half-Adder
• Function Table• Expression• Logic Circuit
Half-Adder Function Table
Input Output
A B Sum Carry Out
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Half-Adder Circuit
A
B
Cout
BABABASum ABCarryOut
Full-Adder
• Function Table• Expression• Logic Circuit
Full-Adder Function Table
Input Output
A B Carry In (C)
Sum Carry Out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Sum Expression
ABCCBACBACBASum
)()( BCCBACBCBASum
)()( CBACBASum
CBASum
Carry Out Expression
ABCCABCBABCACarryOut
)()( CCABBABACCarryOut
ABBACCarryOut )(
Full-Adder Circuit
A
B
Cout
C
CBASum ABBACCarryOut )(
Full-Adder
• Full-Adder = Half-Adder + Half-Adder
Full-Adder based on Two Half-Adders
A
B
Cout
Half-Adder
A
B
Cout
Half-Adder
Cin
A
B
Cout
Parallel Binary Adder
• Multiple Single bit Full-Adder connected in Parallel
4-bit Parallel Adder
ABC
in
Cou
t
ABC
in
Cou
t
ABC
in
Cou
t
ABC
in
Cou
t
A0B0A1B1A2B2A3B3
S0S1S2S3Cout
0
