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DESCRIPTION
RTL Module Behavioral Simulation using Xilinx ISIM within MATLAB Environment
Citation preview
RTL Module Behavioral Simulation
within MATLAB Environment
By: Mohamed Abdelsalam
Outlines C/C++ vs Verilog ISIM ISIM fuse command Running Simulation EXE Test-bench MATLAB/ISIM Link runverilogmodule Algorithm Creating module test bench Calling Verilog Modules MATLAB Wrapper Function Short Circuit Module Example
C/C++ vs Verilog
MATLAB
func1 func2 funcN
Main Func.
Mex Func
Main Module
Test-bench
module1 module2 moduleN
Microsoft Visual Studio C/C++
MATLAB Mex func.
Microsoft Visual Studio C/C++
MATLAB Mex func.
Xilinx IDE/ISIM
MATLAB runverilogmodule func.
ISIM The Xilinx® ISE Simulator (ISim) is a Hardware
Description Language (HDL) simulator enables to perform functional and timing simulations
(VHDL, Verilog) This ISE Simulator environment is comprised of
the following key elements: Vhpcomp/ Vlogcomp VHDL/Verilog compiler fuse (HDL elaborator and linker) Simulation Executable isimgui (ISim Graphical User Interface) can be used
for debugging
ISIM fuse command The project file lists:
Names of modules including test-bench file (.v)
The used HW description language (Verilog) of each module
The stored library of each module. Fuse will parse the project file
compile and link all the sources for the design. Following completion of these steps, a
simulation executable will be created This exe is used to run a behavioral
simulation using standalone ISIM. The test bench defines the top design
unit, the input and the output, etc. Main sections of the test bench are shown
in a separate slide
fuse
Simulation EXE
Test bench
Project file
options
Modules
Dos Command
Running Simulation EXE The generated simulation EXE can be
called from within DOS command. In order to use DOS command, a
batch file is provided by Xilinx (settings) should be used.
The simulation exe calls the standalone ISIM.
ISIM applies behavioral simulation to the design stated at the test bench (TB).
TB can specify input and output files (vectors) for reading and writing, respectively.
TB Also specifies some other parameters which are described in the next slide
DOS Command
ISIM
TB
Settings64.bat
Input vectors(.txt)
Output vectors(.txt)
Sim EXE
Test-bench
I/O ports )input registers, output wires(
Instantiate the Unit Under Test )UUT(
Timescale/errorClock Period
Initialization)load input test vectors to memory(
Clock generation
Passing inputs to the moduleReading module outputs to o/p
vectors, finish after processing the required length
MATLAB/ISIM Link Function interface
I/P Set Cell: Specifies the name and fixed point formats
of each input to the module Example: {‘rx_ip’, ‘s2.1’; ‘ctr_sig’,’u1.0’}
O/P Set Cell Specifies the name and fixed point format of
each output from the module Example: {‘rx_op’, ‘s1.3’; ‘status_sig’,’u1.0’}
I/P Vector Cell Each row in this cell is corresponding to
input signal specified in the same row number in the I/P Set Cell.
Example: {[2.1, 3.6, 12.3, -3.7,..]T; [ 1, 1, 1, 1, 0, …]T}
O/P Vector Cell Each row in this cell is corresponding to
output signal specified in the same row number in the O/P Set Cell.
Example: {[31.6, 46.1, 120.2, -39.5,..]T; [ 1, 1, 1, 1, 1, …]T}
runverilogmodule
Module folder path
Module test-bench name
I/P Set Cell
O/P Set Cell
I/P Vec Cell
O/P Vec Cell
Use debug option
runverilogmodule Algorithm
Note: the function will ask for the path of Xilinx ISE at the first time only
Need re-making?
Adjust formatPath name need
Adjustment?
Prepare required Files and make simulation exe
read the input into files after applying the fixed
point processing as specified in the input
Settings Cell
Run module sim. exe
read the output vectors from files after applying
the fixed point processing as specified in the output Settings
Cell
start
Remove intermediate
files and finish
Creating module test bench Right click on the top module and select
New Source Select source type: Verilog Test Fixture and then enter file name (test bench name) click next select the top module to associate with the test bench click Next and then click Finish.
Calling Verilog Modules Download “runverilogmodule.m” file and place it
@ MATLAP PATH\work folder. This is one of the default matlap paths Functions placed at the work folder are seen as built-in
functions. Inside the module folder make sure that all
modules and the test-bench .v files exist Write a wrapper matlab function to interface with
“runverilogmodule”. Call the wrapper function inside the model.
MATLAB Wrapper Function Provides the usual interface of any matlab function
input/output signals (variables/vectors/matrices) Preparing inputs
Input vectors cell: Each row carries a vector corresponding to one of the inputs
Input settings cell: Each row carries two elements corresponding to the input
vector at the same row in the input vectors cell: Signal name Signal fixed point format
Note: Input signal names should match file names inside the test-bench
MATLAB Wrapper Function (contd.) Preparing outputs
Outputs vectors cell: Each row carries a vector corresponding to one of the
outputs Output settings cell:
Each row carries two elements corresponding to the output vector at the same row in the input vectors cell:
Signal name Signal fixed point format
Note: output signal names should match file names inside the test-bench
Short Circuit Module Example Test script
SC_Module folder structure
Short Circuit Module Example sc module MATLAB wrapper function
Short Circuit Module Example sc module test-bench (.v)
Short Circuit Module Example sc module test-bench (.v) - continued
Short Circuit Module Example sc module test-bench (.v) - continued
Short Circuit Module Example sc module
Short Circuit Module Example
0 10 20 30 40 50 60 70 80 90 100-2
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0x 10
-3
•Output
Source Code/Example: Please visit
http://www.mathworks.com/matlabcentral/fileexchange/43478-matlabxilinx-isim-link
ThankYou!
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